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Vehicle Battery Chargers

1

Fariborz Musavi

Department of Research, Engineering

Delta-q Technologies Corp.

Burnaby, BC, Canada

fmusavi@delta-q.com

University of British Columbia | 1 Okanagan | 2 Vancouver

1

Kelowna, BC, Canada | 2 Vancouver, BC, Canada

1

wilson.eberle@ubc.ca | 2 wgd@ece.ubc.ca

In the two-stage architecture, the PFC stage rectifies the

input AC voltage and transfers it into a regulated

intermediate DC link bus. At the same time, power factor

correction is achieved [4]. The boost circuit-based PFC

topology operated in CCM is employed in this study as the

main candidate for front end single-phase solutions for ACDC power factor corrected converters used in PHEV battery

chargers.

power factor corrected converter is proposed for plug in

hybrid electric vehicle battery chargers. The converter features

high efficiency at light loads and low lines, which is critical to

minimize the charger size, charging time and the amount and

cost of electricity drawn from the utility; the component count,

which reduces the charger cost; and reduced EMI. The

converter is ideally suited for automotive level I residential

charging applications.

The conventional boost topology shown in Fig.1 uses a

dedicated diode bridge to rectify the AC input voltage to DC,

which is then followed by the boost section. In this topology,

the output capacitor ripple current is very high [5] and is the

difference between diode current and the dc output current.

Furthermore, as the power level increases, the diode bridge

losses significantly degrade the efficiency, so dealing with

the heat dissipation in a limited area becomes problematic.

Due to these constraints, this topology is good for a low to

medium power range up to approximately 1kW. For power

levels >1kW, typically, designers parallel semiconductors in

order to deliver greater output power. The inductor volume

also becomes a problematic design issue at high power

because of permeability drops at higher load and heat

associated with core and copper losses.

analysis of this converter is presented. Experimental results of

a prototype boost converter, converting universal AC input

voltage to 400 V DC at 3.4 kW are given and the results are

compared to an interleaved boost converter to verify the proof

of concept, and analytical work reported. The results show a

power factor greater than 0.99 from 750 W to 3.4 kW, THD

less than 5% from half load to full load and a peak efficiency of

98.6 % at 240 V input and 1000 W load.

I.

INTRODUCTION

vehicle with a storage system that can be recharged by

connecting a plug to an external electric power source. The

charging AC outlet inevitably needs an on-board AC-DC

charger with power factor correction [1]. An on-board 3.4

kW charger could charge a depleted battery pack in PHEVs

to 95% charge in about four hours from a 240 V supply [2].

A variety of circuit topologies and control methods have

been developed for PHEV battery chargers. The two-stage

approach with cascaded PFC AC-DC and DC-DC converters

is the common architecture of choice for PHEV battery

chargers, where the power rating is relatively high, and

lithium-ion batteries are used as the main energy storage

system [3]. The single-stage approach is generally only

suitable for lead acid batteries due to large low frequency

ripple in the output current.

Corporation.

821

solutions.

The bridgeless configuration topology shown in Fig.2

avoids the need for the rectifier input bridge yet maintains

the classic boost topology [6-13]. It is an attractive solution

for applications >1kW, where power density and efficiency

are important. The bridgeless boost converter solves the

problem of heat management in the input rectifier diode

bridge, but it introduces increased EMI [14, 15]. Another

disadvantage of this topology is the floating input line with

respect to the PFC stage ground, which makes it impossible

to sense the input voltage without a low frequency

transformer or an optical coupler. Also in order to sense the

input current, complex circuitry is needed to sense the

current in the MOSFET and diode paths separately, since the

current path does not share the same ground during each

half-line cycle [8, 16].

II.

Fig.4 is proposed as a solution to address the problems

outlined in section I for the conventional boost, bridgeless

boost and interleaved boost topologies. This topology

features high efficiency at light loads and low lines, which is

critical to minimize the charger size, charging time and the

amount and cost of electricity drawn from the utility; the

component count, which reduces the charger cost; and

reduced EMI. The converter is ideally suited for automotive

level I residential charging applications in North America

where the typical supply is limited to 120V and 1.44kVA.

The proposed topology introduces two more slow diodes

(Da and Db) to the bridgeless configuration to link the

ground of the PFC to the input line. However, the current

does not always return through these diodes, so their

associated conduction losses are low. This occurs since the

inductors exhibit low impedance at the line frequency, a

large portion of the current flows through the FET intrinsic

body diodes. Also the gating signals for FETs are 180 out of

phase.

A detailed converter description and steady-state

operation analysis is given in the following section.

The interleaved boost converter shown in Fig.3 is simply

two boost converters in parallel operating 180 out of phase

[20-22]. The input current is the sum of the two inductor

currents. Because the inductors ripple currents are out of

phase, they tend to cancel each other and reduce the input

ripple current caused by the boost switching action. The

interleaved boost converter has the advantage of paralleled

semiconductors. Furthermore, by switching 180 out of

phase, it doubles the effective switching frequency and

introduces smaller input current ripple, so the input EMI

filter can be smaller [23-25]. This converter also has reduced

output capacitor high frequency ripple, but it still has the

problem of heat management for the input diode bridge

rectifiers.

III.

ANALYSIS

been separated into the positive and negative half-cycles as

explained in sub-sections A and B that follow. In addition,

the detailed circuit operation depends on the duty cycle.

Positive half-cycle operation analysis is provided for D > 0.5

in sub-section C and D < 0.5 in sub-section D.

A. Positive Half-Cycle Operation

Referring to Fig. 4, during the positive half-cycle, when

the AC input voltage is positive, Q1 turns on and current

flows through L1 and Q1 and continues through Q2 and then

L2, returning to the line while storing energy in L1 and L2.

When Q1 turns off, energy stored in L1 and L2 is released as

current flows through D1, through the load and returns

through the body diode of Q2/partially through Db back to

the input.

In the following section, a new phase shifted semibridgeless boost PFC converter is proposed in order to

improve overall efficiency of the AC-DC PFC converter,

822

Referring to Fig. 4, during the negative half-cycle, when

the AC input voltage is negative, Q2 turns on and current

flows through L2 and Q2 and continues through Q1 and then

L1, returning to the line while storing energy in L2 and L1.

When Q2 turns off, energy stored in L2 and L1 is released as

current flows through D2, through the load and returns split

between the body diode of Q1 and Da back to the input.

calculation of the input ripple current, which provides design

guidance to meet the required input current ripple standard.

D > 0.5

The detailed operation of the proposed converter depends

on the duty cycle. During any half-cycle, the converter duty

cycle is either greater than 0.5 (when the input voltage is

smaller than half of output voltage) or smaller than 0.5

(when the input voltage is greater than half of output

voltage). The three unique operating interval circuits of the

proposed converter are provided in Fig. 5 to Fig. 7 for duty

cycles larger than 0.5 during the positive half-cycle.

Waveforms at D > 0.5

During this interval, the current in series inductances L1 and

L2 increases linearly and stores the energy in these inductors.

The energy stored in Co provides energy to the load. The

ripple currents in Q1 and Q2 are the same as the current in

series inductances L1 and L2, where the ripple current is

given by:

v D

(1)

in Fig.6. During this interval, the current in series

inductances L1 and L2 continues to increase linearly and

store the energy in these inductors. The energy stored in Co

provides the load energy. The ripple currents in Q1 and body

diode of Q2 are the same as the current in series inductances

L1 and L2, where the ripple current is given by:

half-cycle operation with D>0.5 are shown in Fig. 8. The

intervals of operation are explained as follows. In addition,

823

v 1

D T

(2)

explained as follows.

1 is repeated, as shown in Fig. 5. During this interval, the

current in series inductances L1 and L2 increases linearly

and stores the energy in these inductors. The ripple currents

in Q1 and Q2 are the same as the ripple current in series

inductances L1 and L2, as shown in equation (1).

Interval 4 [t3-t4]: At t3, Q1 is off and Q2 is on, as shown I

Fig. 7. During this interval, the energy stored in L1 and L2 is

released to the output through L1, D1, Q2 and L2. The ripple

currents in D1 and Q2 are the same as the ripple currents in

L1 and L2:

(3)

conducting

waveforms at D < 0.5

During this interval, the energy stored in L1 and L2 are

released to the output through L1, D1, body diode of Q2 and

L2. The ripple currents in D1 and body diode of Q2 are the

same as the ripple currents in L1 and L2:

D T

(4)

in Fig.10. During this interval, the current in series

inductances L1 and L2 continues to increase linearly and

store the energy in these inductors. The energy stored in Co

provides energy to the load. The ripple currents in Q1 and

the body diode of Q2 are the same as the current in series

inductances L1 and L2, where the ripple current is given by:

D < 0.5

proposed converter are given in Fig. 9 to Fig. 11 for duty

cycles smaller than 0.5 during the positive half-cycle. The

waveforms of the proposed converter during these conditions

v DT

(5)

1 is repeated, as shown in Fig. 9. During this interval, the

current in series inductances L1 and L2 increases linearly

824

than the benchmark conventional boost and 7% lower than

the interleaved boost . Since the benchmark converter bridge

rectifier losses are large, it is expected that phase shifted

semi-bridgeless boost converter should have the lowest

losses among the topologies investigated. Additionally, it is

noted that the losses in the input bridge rectifiers are 63% of

total losses in the conventional PFC converter and 71% of

total losses in the interleaved PFC converter. Therefore,

eliminating the input bridge in PFC converters is justified

despite that the introduction of new losses.

in D1 and body diode of Q2 are the same as the ripple

current in series inductances L1 and L2, as shown in

equation (1).

Interval 4 [t3-t4]: At t3, Q1 is off and Q2 is on, as shown I

Fig. 11. During this interval, the energy stored in L1 and L2

is released to the output through L1, D1, Q2 and L2. The

ripple currents in D1 and Q2 are the same as the ripple

currents in L1 and L2:

(6)

V.

voltage half-cycle is similar to the operation of converter

during the positive input voltage half-cycle.

and an interleaved boost converter were built to verify the

proof-of-concept and analytical work presented in this paper

and to benchmark the proposed converter. The devices used

in experimental prototypes are provided in Table 1.

LOSS EVALUATION

provided in Fig. 13 at 70 kHz switching frequency, 240V

input and 3300W load for benchmark conventional boost and

interleaved boost converters and the proposed phase shifted

semi-bridgeless boost converter. The currents in regular

diodes Da and Db were assumed to be split with the current

going through intrinsic body diodes for phase shifted semibridgeless topology. The regular diodes in input bridge

rectifiers have the largest share of losses among the

topologies with the input bridge rectifier. The phase shifted

semi-bridgeless topology nearly eliminates this large loss

component (~30W). However, the tradeoff is that the FET

losses are higher and the intrinsic body diodes of FETs

conduct, producing new losses (~8W). The fast diodes in the

conventional and interleaved PFC have slightly lower power

losses, since the boost RMS current is higher in these

topologies.

Conventional Boost

Part # / Value

# of Devices

25ETS08S

Fast Diode

IDB06S60C

MOSFET

IPB60R099CP

Inductors

400 H

25ETS08S

Fast Diode

IDB06S60C

MOSFET

IPB60R099CP

Inductors

400 H

Regular Diode

Regular Diode

prototype are provided in Fig. 14. It consists of a control

board, a capacitor bank of 820 F and an IMS power board

attached to a heatsink with the PFC inductors.

6.9W

6.9W

9.8

4.1

20

10.8W

5.4W

21.6

30

10

Device

0.0W

0.0W

4.1

40

Interleaved Boost

30.0W

30.0W

50

Topology

47.7W

42.3W

39.4

60

Phase Shifted

Semi-bridgeless

PFC converter

IV.

EXPERIMENTAL RESULTS

Interleaved PFC

converter

Total

Losses

Intrinsic

Body

Diodes

FETs

Fast

Diodes

Regular

Diodes

Semiconductor Losses

Figure 13. Comparison of the estimated loss distribution in the

semiconductors at 70kHz switching frequency, 240V input, 3300W load at

400V

shifted semi-bridgeless topology, but the total loss for the

825

bridgeless boost converter and benchmark interleaved boost

converter is provided in Fig. 15 for 240V input and Fig. 17

for 120V input at 70 kHz switching frequency and 400 V

output. Loss reduction curves as a function of output power

are provided in Fig. 16 and Fig. 18 for 240V and 120V input,

respectively.

70

100

98

40

30

20

10

3500

3500

Vin=120

1800

1600

1400

1200

1000

800

600

400

200

91

Vin=240

3000

2500

2000

95

1500

Power factor

96

1.02

1

0.98

0.96

0.94

0.92

0.9

0.88

0.86

0.84

1000

97

92

1800

Figure 19. THD as a function of output power at Vin = 120 V and 240V,

Vo=400V and 70kHz switching frequency

98

93

1600

Vo=400V and 70kHz switching frequency

500

3000

2500

2000

1500

1000

500

3500

10

Vin=120

3000

20

Vin=240

2500

THD (%)

30

2000

40

45

40

35

30

25

20

15

10

5

0

1500

Converters at Vin = 240 V

1000

70

500

3500

3000

2500

2000

1500

1000

500

PFC converter achieves a peak efficiency of 98.6% at 1 kW

output power. Additionally, the light load efficiency of the

proposed converter is significantly better than that of the

interleaved PFC due to the absence of input bridge rectifier.

However, as the load increases, the efficiency drops due to

additional heat dissipation in the intrinsic body diodes of the

FETs.

Vo=400V and 70kHz switching frequency

94

1400

Vo=400V and 70kHz switching frequency

50

1200

60

1000

96

800

600

400

200

94

50

97

95

Efficiency (%)

Converters at Vin = 120 V

Efficiency (%)

99

60

Vo=400V and 70kHz switching frequency

Figure 20. Power Factor as a function of output power at Vin = 120 V and

240V, Vo=400V and 70kHz switching frequency

826

2.5

Amplitude (A)

Output Voltage

1.5

Amplitude (A) Vin = 120 V

1

Amplitude (A) Vin = 240 V

0.5

0

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

Inductor

Current

Harmonics Order

Input Voltage

Input Current

Figure 21. Harmonics orders at Vin = 120 V and 240V, compared against

EN61000-3-2 standard.

Figure 23. Inut current, inducotr current, input voltage and output voltage.

Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch3= IL1 10A/div. Ch4= Iin

10A/div.

current THD is shown in Fig.19. The power factor and

harmonic orders are given and compared with EN 61000-3-2

standard in Fig.20 and 21. It is noted that mains current THD

is less than 5% from 50% load to full load and it is compliant

to IEC 6100-3-2 (Fig. 19 and Fig. 21). The converter power

factor is shown over entire load range for 120 and 240V

input in Fig. 20. The power factor is greater than 0.99 from

50% load to full load.

Input

Current

prototype are provided in Fig. 22 through Fig. 26. The input

current, input voltage and output voltage are given in Fig. 22.

As it can be seen, the input current is in phase with the input

voltage and has a sinusoidal shape. Additionally, there is a

low frequency ripple on output voltage, which is inversely

proportional to the value of PFC bus output capacitors.

In Fig. 23, the inductor current is provided in addition to

the above mentioned waveforms from Fig. 22. It is noted that

during the positive half-cycle, the inductor current is the

same as input current. However, during the negative halfcycle, the input current is partially flowing through slow

diodes, Da and Db.

Inductor

Current

Figure 24. Inductor current, input current and sensed FET current.

Ch1= Sensed IQ1 2V/div. Ch3= IL1 / IDb 10A/div. Ch4= Iin 10A/div

Inductor Current

Output Voltage

Sensed FET

Current

Input Voltage

Gating Signal

Input Current

Figure 25. Gating signal, Inductor and sensed FET current for D < 0.5

Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div

Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch4= Iin 10A/div.

sensed in the FET through a current transformer are given.

827

current are provided for duty cycles less than 0.5, Fig 25, and

greater than 0.5, Fig. 26. These waveforms match the

theoretical models.

[2]

[3]

[4]

Inductor Current

[5]

[6]

[7]

Gating Signal

[8]

Figure 26. Gating signal, Inductor and sensed FET current for D > 0.5

Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div

VI.

[9]

CONCLUSIONS

[10]

AC-DC Boost converter topology has been presented in this

paper for the front-end AC-DC converter in PHEV battery

chargers. The proposed converter features high efficiency at

light loads and low lines, which is critical to minimize the

charger size, charging time and the amount and cost of

electricity drawn from the utility; the component count,

which reduces the charger cost; and reduced EMI. The

converter is ideally suited for automotive level I residential

charging applications in North America where the typical

supply is limited to 120V and 1.44kVA.

[11]

[12]

[13]

A breadboard converter circuit has been built to verify the

proof-of-concept. The theoretical waveforms were compared

with the results taken from prototype unit. Additionally, key

experimental waveforms were provided and input current

harmonics at each harmonic order were compared more

explicitly with the IEC 6100-3-2 standard limits.

[14]

[15]

[16]

THD is smaller than 5% from 50% load to full load and the

converter is compliant with the IEC 6100-3-2 standard. The

converter power factor was also provided for full power

range at 120 and 240V input. The power factor is greater

than 0.99 from 50% load to full load. The proposed

converter achieves a peak efficiency of 98.6 % at 240 V

input and 1 kW output power.

[17]

[18]

[19]

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828

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U. Moriconi, "A Bridgeless PFC Configuration based on L4981 PFC

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Woo-Young Choi; Jung-Min Kwon; Eung-Ho Kim; Jong-Jae Lee;

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2007.

Huber, L.; Yungtaek Jang; Jovanovic, M.M.; "Performance

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Frank, W.; Reddig, M.; Schlenk, M.; "New control methods for

rectifier-less PFC-stages," in Proc. EEE International Symposium on

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