+

..
.

..
.

Correco digital + Codificador

bN

..
.

A 65nm CMOS b1.2V 6b 1GS/s

Two-Step+ Subranging
ADC for Ultra Wideband
+

L. Roicado
lroicado@chipidea.com

IST - Technical
University of Lisbon
V
Lisboa,
Portugal
S/H
v

ChipIdea Microelectronica
Porto Salvo, Portugal

REFN

clk

buffers do sinal de relgio

Abstract

vI
111

UWB (Ultra Wideband) is a standard which is yet

in its normalization period, and even though several
entities are fighting to enforce their own specifications,
what we certainly know is that its a short range highbandwidth wireless data transmission system, using
spread spectrum techniques to minimize the interference with other wireless devices present at our homes
nowadays. Typical applications of UWB are HDTV
(High Definition Television) signals transmission, BluRay or some others less familiar to the common user
such as radar imaging.
This work presents the project of one of the main
components of the UWB system: the Analog-to-Digital
Converter, ADC. Knowing that the main requirement
of the ADC is a moderate resolution at a high sampling
frequency, parallel architectures are the most appropriate to fit this application. Following this idea, the Flash
ADC and the sub-family of two-step flash ADCs are
presented, giving a special emphasis to the Two-Step
Flash ADC with DAC and Subtractor and to the TwoStep Subranging Flash ADC. Then, the last two will be
studied in a more deep and careful way, explaining how
they work and showing their main advantages and disadvantages, which will lead us to choose the Two-Step
Subranging Flash ADC.
An existing 90nm CMOS 600MS/s ADC was studied, and based on this work, a 6-bit 1GS/s Two-Step
Subranging ADC has been designed in a more recent
technology of 65nm. This work presents the ADC architecture and describes its timing diagrams. After
that, each one of its main internal blocks are discussed
and the correspondent simulation results are given.
This dissertation also addresses one problem that has
affected the robustness of the implemented ADC; a solution was proposed to overcome this problem, after
which the necessary studies and simulations were performed and could validate the proposed solution.

110
101
100
011
010
001
000
t

TS

Figure 1: Analog signal digitalization.

The sampling operation performs a time discretization of the input voltage at a frequency fs = 1/Ts ,
but the amplitude of the resulting signal can still
take any value. Thus, the input range of the ADC
is divided into small regions called quantization steps
which have the width VLSB , and the sampled input
signal is approximated by one of these quantization
levels. The last step of the digitalization process - the
encoding - consists of assigning a binary number, the
output code, to each quantization level.

1.2. Characterization and Performance

There are several measurements and indicators useful in the characterization of ADCs. Hence, the resolution of the ADC corresponds to the number of bits
of its output, N , and the number of quantization steps
is given by 2N . If the full scale voltage of the ADC is
VF S , then

Keywords: Ultra Wideband, High Definition Television, Blu-Ray, Analog-to-Digital Converter, two-step
flash ADCs, Two-Step Subranging Flash ADC

VLSB =

VF S
2N

(1)

is the quantization step. The maximum error of each

quantization step (usually defined in terms of the absolute value) is half of this value,

1. Introduction
1.1. Basic Concepts
The ADC is an integrated electronic circuit that
converts continuous-time / continuous-amplitude signals (usually voltages) into discrete-time / discreteamplitude signals. This is accomplished in 3 phases,
specifically Sampling, Quantization and Encoding.
Fig. 1 illustrates the digitalization of an analog signal.

|eq (t)|

VLSB
,
2

(2)

and therefore, each bit increased in the ADC resolution leads to a decrease of both VLSB and |eq (t)| to
half of their previous values.

Fase I
(durao constante)

Vin3

Fase II
(declive constante)

Vin2

1.3. High Speed ADCs Vin1

The Signal-to-Noise Ratio (SNR) is the relation between the signal power and the noise power. The maximum achievable SNR of an ideal ADC is given [4] by
SN R[dB] |M AX = 6.02N + 1.76

The largest conversion rate is achievable with the

T1
flash ADC. It has a throughput
of one binary word per
clock cycle and its general architecture is shown in Fig.
T2 (trs valores paras trs entradas
2.

(3)

which comes from the quantization error.

Pre
amplifiers

Latched
comparators

..
.

Bubble Correction + Encoder

VREFP

Due to their non-idealities, all real ADCs generate

spectral components at frequencies multiples of fi harmonics. The Total Harmonic Distortion (THD) is
the relation between the power of all harmonics above
the fundamental one and the power of the input signal,
!
NX
H +1
2
2
T HD[dB] = 10 log10
An.fi /Afi
(4)

..
.

n=2

where An.fi represents the magnitude of the

spectral component at n.fi and NH is the number of
harmonics considered.
The Signal-to-Noise-and-Distortion Ratio (SINAD
or SNDR) defines the relation between the signal power
and the power of all undesired spectral components
(harmonics + noise). It can be obtained from the SNR
and the THD,
!
SIN AD[dB] = 10 log10 10

T HD[DB]
10

+ 10

SN R[DB]
10

VREFN
vI
clk

VT [k] VT ideal [k]

=
VLSB

(6)

(7)

VT [k] VT ideal [1]

(k 1), k = 1 . . . 2N 1.
VLSB
The Diferential Non-Linearity (DNL) is the difference between two consecutive code transition levels,
normalized to the quantization step:
=

DN L[k] =

VT [k + 1] VT [k] VLSB
=
VLSB

b1

vIS
Clock buffers

In an N -bit flash ADC there are 2N 1 preamplifiers and latched comparators and one resistive
ladder that divides the input range in 2N quantization levels. A sample-and-hold performs the sampling
operation and the pre-amplifiers subtract the sampled
signal from the reference voltages. If the differen-111
tial input voltage of the k th pre-amplifier is positive,110
(vIS VREFk ) > 0, its differential output voltage will101
also be positive and the latched comparator after it will100
regenerate the logic level high (the opposite occurs if011
(vIS VREFk ) < 0). Thus, considering a growing ramp010
input, the outputs of the latched comparators will be
active (high logic level) one after another, from bottom001
to top, resembling the mercury scale of a thermometer.000
Finally, a ROM is usually employed to encode this output to the final binary word. Due to large number of
pre-amplifiers and latched comparators required, the
power dissipated by these ADCs makes them apropriated for resolutions no greater than 8 bit. To overcome
this limitation, two-step flash ADCs are employed and
the necessary hardware and power can be weighty
reduced. The blocks diagram of an 8-bit Two-Step
Flash ADC with DAC (Digital-to-Analog Converter)
and Subtractor is depicted in Fig. 3. A coarse flash

This is a very useful parameter when characterizing

ADCs because it shows how far from the ideal converter is the performance of the ADC being tested.
The characterization of nonlinear errors is done using two parameters. The Integral Non-Linearity (INL)
is the diference between the ideal and measured transition level of each output code, normalized to que quantization step VLSB :
IN L[k] =

..
.

Figure 2: General architecture of a Flash ADC.

(5)
The Effective Number Of Bits (ENOB) indicates the
number of bits that an ideal converter would have to
achieve the measured SINAD,
SIN AD[DB] 1.76
EN OB =
.
6.02

S/H

bN

(8)
vIN

VT [k + 1] VT [k]
=
1, k = 1 . . . 2N 2,
VLSB
where VT [k] is the input voltage where the transition from code k 1 to code k occurs. From (8) we can
conclude that when the transition level of two consecutive codes is the same, VT [k + 1] = VT [k], DNL=-1.
This is an extreme case of non-linearity of the ADC.

4bit
MSB
ADC

4bit
DAC

vDAC

_+

eq

16

4bit
LSB
ADC

Amplifier

4 least
significant bits

4 most
significant bits

Figure 3: Two-Step ADC with DAC and Subtractor.

vI

ADC obtains the 4 most significant bits (MSBs), which

the DAC uses to generate a rough approximation of
the input signal. The output of the DAC is, then, subtracted from the input signal yielding the residue, that
corresponds to the error eq made in the coarse quantization. This residue is multiplied by a factor of 16 and
finally, the fine ADC quantizes the amplified residue
and obtains the 4 least significant bits (LSBs). This
architecture requires only 2NM SB +2NLSB 2 = 30 preamplifiers and latched comparators, where the flash
ADC needed 255. However, this converter employs a
DAC, a subtractor and an amplifier, whose linearity,
gain error and settling speed are critical parameters
that limit the resolution and sampling frequency.
The requirements of high linearity can be suppressed
if we choose a Two-Step Subranging Flash ADC. It performs the same operations of the two-step converter
shown in Fig. 3 but the digital-to-analog conversion
and the subtraction are done in a way that avoids using highly linear components, therefore, improving high
frequency performance. The architecture of a 3-bit
two-step subranging flash ADC (1 bit MSB + 2 bit
LSBs) is depicted in Fig. 4.

Besides reducing the linearity requirements of its components, this architecture also reduces the necessary
hardware and power dissipation with respect to the
flash ADC.

1.4. Introduction to UWB

Ultra Wideband is a short range high bandwidth
wireless data transmission system using spread spectrum techniques to avoid electromagnetic interference
with other wireless devices. Its main goal is to
overcome the bitrate limitations of other technologies
such as Bluetooth, leading to Personal Area Networks
(PANs) with bitrates from 480 Mb/s to several Gb/s.
Thus, it will become possible to connect a video camera
to a flat panel display or a laptop to a video projector without needing any cable. The electromagnetic
spectrum region between 3.1 GHz and 10.6 GHz has
been reserved for UWB since February 2002, and the
maximum Effective Isotropic Radiated Power (EIRP)
of any UWB device is established in -41.3 dBm/MHz,
as depicted in Fig. 5.

VREFP

Power

Narrow Band (10 kHz)

VREF LSBs

MSB0

Bus

sw12=MSB0

subrange 1

875 mV

Wide Band
CDMA (5 MHz)

sw11=MSB0

comp2LSB

750 mV

500 mV

subrange 0

sw02=MSB0

MSB0

Encoder

Full range

sw10=MSB0

comp1LSB

b2

T1

b1

comp0LSB

According to [2], [7] and [3], besides the large bandwidth UWB typically requires ADCs with moderate
resolutions from 4 to 6 bit. Therefore, the two-step
subranging ADC presented before seems to be the
natural choice to equip UWB devices with. Although
it is intrinsically slower than the flash ADC, it uses
less comparators to obtain the same resolution, which
hopefully results in smaller power dissipation and
area. These are key factors when we think of portable
devices wich generally work on batteries, thus, having
limited energy resources.

VREFN
vI

Frequency

Figure 5: Comparison between the bandwidth covered

by UWB and other radio signals, in the electromagnetic spectrum.

sw01=MSB0

sw00=MSB0

UWB (several GHz)

41.3
dBm/MHz

b3

S/H

Figure 4: Two-Step Subranging Flash ADC.

The S/H samples the input signal which is applied
to both (Coarse and Fine) ADCs. Assuming that the
sampled signal is about 800 mV and the full scale voltage applied to the reference ladder is 1 V, the only
comparator of the coarse ADC (M SB0 ) will decide 1.
Based on this decision, a selection logic will short the
3 upper most switches passing the reference voltages
to the 3 comparators of the fine ADC. Now, in the
second step of conversion, the fine ADC uses these references and obtains the 2 LSBs (comp2LSB decides 0,
comp1LSB and comp0LSB decide 1). Finally, the encoder joins the MSB with the LSBs and generates the
binary word. In this way, the reference ladder has a
double function: generates the reference voltages to
the coarse ADC and, in combination with the reference selection switches performs the digital-to-analog
conversion. The subtraction between the (sampled)
input signal and the DAC result (Fig. 3) is done is a
distributed way by the pre-amplifiers of the fine ADC.

2. General Architecture
The ADC has been implemented in a 65nm CMOS
technology and shall be able to operate between -40
and 125 . Its top-level architecture is shown in Fig. 6.
There is a 2.5 bit Coarse ADC (CADC) that makes a
rough estimation of the input signal position and quantizes the MSBs. Then, the set of reference voltages that
are closer to the input signal are selected and applied
to the Fine ADC (FADC), which quantizes the LSBs.
This architecture uses less comparators but it is intrinsically slower than the Flash ADC: after sampling the
input signal, the coarse ADC must quantize the MSBs
and the fine ADC has to wait for the settling of the reference voltages in order to correcty obtain the LSBs.
3

vI

VCM

ph1+ph4

clk

VRP

Encoder and Error Correction

Reference Ladder

Fine ADC A
(4 bit)

Coarse ADC
(2.5 bit)

Fine ADC B
(4 bit)

clk
ph1+ph4

vIP

clk

ph2
CS

vIN

b5 ... b0

Qz

clk

clk
ph2+ph3
clk

VRN
clk

VCM

ph2+ph3
ph4

Figure 8: Coarse ADC sampling network plus latched

comparators.

Figure 6: 6b two-step subranging architecture.

one of them is latched in each clock cycle. The reason
for this time interleave has its origins in the sampling
technique. The input sampling is made by connecting
to the inputs the capacitors that have stored the reference voltage, and then, connect them to the inputs of
the dynamic comparators. By doing this, before connecting the capacitors that have stored the reference
voltage, the differential voltage stored in the parasitic
capacitance of each dynamic comparator must be discharged, or else the reference voltage will be corrupted
by this voltage that consists in comparators kick-back
noise. This parasitic capacitance discharge is made in
the idle phase of the comparator, and is implemented
by starting the input sampling of the dynamic comparator when the input network is sampling the references voltages, and the dynamic comparator input
nodes are being short-circuited.

Thus, at least two clock cycles are needed to obtain

a digital word, making the sampling frequency of this
topology fall to half of the Flash ADCs one. To overcome this speed limitation, two 4 bit sub-Fine ADCs
were employed working in a time-interleaved way, as
depicted in Fig. 7.
ph1

ph2

ph3

ph4

ph1

Coarse
ADC

Samples
vI[1]

Makes decision
about
vI[1]

Samples
vI[2]

Makes decision
about
vI[2]

Samples
vI[3]

Fine
ADC A

Samples
vI[1]

Regenerates
offset voltage

Connects input
capacitors to
reference
voltages

Makes decision
about
vI[1]

Samples
vI[3]

Fine
ADC B

Connects input
capacitors to
reference
voltages

Makes decision
about
vI[0]

Samples
vI[2]

Regenerates
offset voltage

Connects input
capacitors to
reference
voltages

clk

0.5

1st sample
quantized

3.1. Redundancy and Offset Voltage

1.5

The offset voltage is a key factor in the design of

the comparators, and has its origin in the random deviations that affect the design (e.g. dimensions) and
electrical parameters of the devices during the fabrication process. Due to the offset voltage, a pre-amplifier
with zero differential input voltage has a non-zero differential output voltage, and this can cause deviations
in the output characteristic of the ADC with respect to
the ideal one. Redundancy is a thechique employed in
the Coarse ADC to ease the offset specifications of the
comparators. To implement redundancy, the Coarse
ADC resolution is increased by 1 bit and the range
of reference voltages passed to the Fine ADC is twice
larger than the quantization step of the Coarse ADC,
as we can see in Fig. 9. Thus, the Fine ADC can recover from a wrong decision of the Coarse ADC if the
transition levels of its (Coarse ADC) comparators are
shifted no more than 62.5 mV. This error margin corresponds to the difference between the higher reference
voltage of the Coarse ADC and the higher one passed
to the fine ADC (the same applies to the lower limits),
and this value would correspond to the maximum offset
permitted to those comparators in the absence of other
effects beyond the offset itself. However, there are some
other high-frequency related non-idealities that affect
the performance of the ADC, such as the difference between the input voltage sampled by the Coarse ADC
and the Fine ADC, and the difference in the propagation times of the clock signals through the distribution
trees. Monte Carlo simulations were performed to ensure that the standard deviation of the offset voltage
of one comparator, (VOS ), is far bellow that value.
The obtained results are shown in Table 1.

2.5 t[ns]

2nd sample
quantized

Figure 7: Timming diagram of the ADC.

The coarse ADC works simultaneously with each
one of the two fine ADCs. In ph1 the CADC samples vI [1] together with the FADC A. During ph2 the
CADC quantizes the MSBs so that the set of reference
voltages nearer vI [1] are applied to the FADC A in ph3
leading to the quantization of the LSBs in ph4. The
FADC B executes the same operations after a delay of
two fases: it samples vI [2] in ph3 (together with the
CADC), connects its input capacitors to the reference
voltages in ph1 and quantizes the LSBs in ph2. The
shaded areas (during ph2 and ph4) will be discussed
later in section 4.1.

3. Coarse ADC
The coarse ADC has a resolution of 2.5 bit, defining 7 different quantization levels by the usage of 6
comparators. The 0.5 bit extra bit is to be used as redundancy, which will be discussed in section 3.1. Fig.
8 looks inside one of those 6 comparators. The Coarse
ADC works with 2 banks of dynamic comparators in
time-interleave. This means that each capacitive network is connected to the 2 comparators, but only one of
them is sampling the input at the same time, and only
4

ph1

vIN

VREFsN
ph3

Selection according
to the MSBs

VR2

CompMSB2
vI

CompLSB15
CompLSB14
CompLSB13
CompLSB12
CompLSB11
CompLSB10
CompLSB9
CompLSB8
CompLSB7
CompLSB6
CompLSB5
CompLSB4
CompLSB3
CompLSB2
CompLSB1

VR1

CompMSB1

CCAL

are shorted and it amplifies its own offset voltage. During ph2 the FADC A is waiting for the CADC decision
and, thus, could be idle. Instead, a calibration scheme
was implemented in this phase and will be presented
in section 4.1. In ph3, the reference voltages indicated
by the coarse ADC are applied (through one of the
VREF s P switch plus one VREF s N switch) to the sampling capacitor CS , so that (vCP vCN ) is now proportional to the difference between the input signal and
the corresponding reference voltage.

4.1. Calibration
VOS1

S1
vI

gm1

S2

i1

vOA

VOSl
+
-

Range where the

threshold of
CompMSB2 may lie
without causing
errors in the
transfer function
of the ADC

CP

+
-

CompMSB3

R0
VOS2
if CompMSB2
decides low

VMAX
VMIN

Figure 9: Redundancy and references passed to the

Fine ADC.

meaning
min. abs. value of VOS
max. abs. value of VOS
average value of VOS
standard deviation of VOS

S3

vCAL

gm2

i2

S5
CP

CS
Selection
Logic

Figure 11: Offset elimination technique used inside the

comparators of the Fine ADC.

Table 1: Statistic indicators of the offset voltage of one

Coarse ADC comparator, after 100 Monte Carlo runs.
Indicator
|VOS |min
|VOS |M AX
x(VOS )
(VOS )

+
-

S4
if CompMSB2
decides high

unit
The latched comparator makes a decision based on
mV
mV the preamplifier output voltage at the end of ph1. The
mV result is determined by the offset voltage of the commV plete comparator chain, and is used to activate the
control logic that adjusts the calibration voltage at the
input of an auxiliary differential pair. This is made by
pre-charging CP to either VMAX or VMIN, depending on the comparators decision, and then switching
4. Fine ADC
CP to CCAL. CP is not an explicit capacitance, it is
The 4 LSBs are obtained from a Fine ADC that
a parasitic one, thus, CCAL can be made much larger
has 2 sub-Fine ADCs working in time-interleave: the
(CCAL>>CP) and the calibration voltage is adjusted
FADC A and the FADC B. In this way it is possible to
in small steps. After some hundreds of clock cycles, the
have an overall sampling frequency of 1 GHz although
auxiliary differential pair injects a current that cancels
both FADC A and FADC B sample the input signal
the offset voltages of both the pre-amplifier and latched
only at each 2 ns. Fig. 10 depicts one of the comparacomparator. This is a process that is always running
tors used in the FADC A (FADC B is equal, except for
in background during ph2 and does not affect the basic
the timming).
functions of the ADC. Fig. 12 shows the response of
the ADC to a ramp input.
Preamplifier
Input Capacitive Network
At the beginning the calibration is OFF and output
codes of the ADC are far from having a monotonic evolution. After 128 clock cycles (128 ns) the calibration
Auxiliary Differential Pair
is switched ON and we can see that the results arent
instantly better: it takes a while to vCAL to rise and
bias the auxialiary differential pair. In the end we have
an output characteristic of the ADC much linear as a
result of this calibration scheme.

value
0.4
19.6
-0.9
6.3

VDD

VREFsP
ph3

vIP

vIN

R0

VCM

ph4

S1a

ph1

S2

clk

vCP

ph1
ph1

CS

M1

clk

M2

VMAX

vCN

IB

VCALP

VMIN

VCALN

VMIN

VMAX

S1b

ph4

VREFsN
ph3

Latched
Comparator

R0

CP

CCAL

CCAL

CP

VCM

Selection
Logic

Selection according
to the MSBs

4.2. Bubble Correction

In an ideal ADC, bellow each comparator with a
high level output there should exist only other comparators with the same logic level. The low-to-high
transition is usually used to address a ROM that encodes the thermometer code output into a binary word.
However, due to non-idealities, some bubbles can occur in the middle of the thermometer code. A digital
block inside the fine ADC implements the correction

Figure 10: Sampling network and comparator used in

the Fine ADCs.
All phases (ph1 to ph4) referred from now on are
relative to Fig. 7. The input signal is sampled in a
distributed way during ph1 in the capacitive input network; at the same time, the inputs of the pre-amplifier
VOS1

gm1

S2

i1

vOA

VOSl

+
-

+
-

S1

vI

R0

VOS2

VMIN

+
-

S4
VMAX

S3

vCAL

gm2

i2

S5
CP

CS
Selection
Logic

CALN

VMIN

VCM

vIN

CompLSB15
CompLSB14
CompLSB13
CompLSB12
CompLSB11
CompLSB10
CompLSB9
CompLSB8
CompLSB7
CompLSB6
CompLSB5
CompLSB4
CompLSB3
CompLSB2
CompLSB1

IB

S1b

ph4

VR3

CALP

vCN

CCAL

CP

64

and two 500 MHz clock signals in quadrature, as depicted in Fig. 14. This is a totally digital block, made

56

T=1 ns

OutputCode

48

40

clk

32

clk_half
2T=2 ns

24

clkf_half
16

Figure 14: Top-level clock signals of the ADC.

8

50

100

150

200

250
300
ClockCycles

calibrationOFF

350

400

450

500

mostly with latches, shift registers and strings of inverters to introduce delays in the signals path.

calibrationON

Figure 12: Output codes of the ADC (ramp input)

with calibration OFF (until 128 ns) and then ON.

5.1. Level Converters

There was a problem affecting the input switches of
the sampling networks inside the comparators: their
ON resistance was too high in some simulations conditions (slow devices, -40), what leads to bad sampling
due to the increase of the time required to perform it.
Those input switches were CMOS pass gates, and the
idea was to implement them with a single thick oxide
transistor, also called high voltage transistor. This solution was able to reduce the ON resistance almost 2
orders of magnitude, from 87 k to 1.4 k in the worst
case. However, these high voltage transistors require
2.5 V in the logic level Hi instead of 1.2 V, and it was
necessary to build a level converter inside the phases
generator. This level converter receives the external
1.2 V clock and generates a 2.5 V clock signal with
the same frequency. Although this is a commonly used
circuit, its most usual topology cannot be used in this
case because it introduces great distortion in the duty
cycle when working at high frequencies. Depending on
the simulation conditions, duty cycles from 38% to 67%
were observed; these results are absolutely unacceptable at 1 GHz, and a new topology of level converter
was studied and implemented to overcome this weakness of common level converters. Fig. 15 shows the
output of the new level converter on the typical corner (the top black square wave) and on the worst cases
(bellow, with slow transistors, at 125 and voltage
levels variations of 10%).
In all tested conditions, within the set of 80 simulations performed, the duty cycle of the output signal
was in the range of 49.0% to 52.2%, having the almost ideal value of 49.9% on the typical case. Table 2
summarizes the results obtained. Parameters tpLH/HL
represent the rise/fall times of the output, with respect
to 10% and 90% of V DDHV (2.5 V). In the other hand,
td RR/F F represent the delay in the rise/fall edge, from
the input to the output of the level converter.

input15

input14

input13

input12

input11

input10

input9

input8

input7

input6

input5

input4

input3

1.2

input2

input1

1.2

input0

1.2

[lsb3]

6.7u

[lsb2]

6.03u

[lsb1]

1.2

[lsb0]

1.2

volt (lin)
volt (lin)
volt (lin)
(lin) volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)
volt (lin)

scheme presented in [8], and we can check its validness

in the simulation depicted in Fig. 13, where 3 errors
were present at the input of the ADC.
0

2n

1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0
1.2
0.6
0

4n

6n

8n

10n

12n

14n

6n

8n

2:8.7n
10n
(lin)

12n

3:13.7n
14n

16n

18n

16n

18n

-4n
-9.03n

2n

4n

1:4.7n

printed Mon Oct 8 2007 22:45:43 by lroicado on pc-lroicado

Sandwork Design, Inc. (c) 2000-2006

Figure 13: Simulation of the bubble correction logic.

Each comparator changes its decision if it disagrees
with both neighbours. The equation that represents
this correction scheme is
CN = C(N 1) CN + CN C(N +1) +C(N 1) C(N +1) ,
(9)
where CN is the output of the N th comparator without
correction and CN represents the same output after
correction. Taking the 2nd error applied to the input
of this logic block, the 7th comparator which is responsible for the bubble at 8.7 ns will change its decision
from 0 to 1, and the corresponding corrected binary
word is 9, as indicated by the output signals lsb0 to
lsb3 .

6. Top Simulations and Results

In order to characterize the performance of the overall ADC, a 120 MHz sine wave was applied to its input, and based on the corresponding digital words it
is possible to compute a Fast Fourier Transform and
calculate some performance indicators of the ADC.

5. Phases Generator
This ADC has a top-level block that receives the
external clock signal and generates the 3 clock phases
that control other blocks: one clock signal at 1 GHz
6

400p

600p

800p

1n

1.2n

1.4n

1.6n

1.8n

2n

2.2n

vindiff

2
RT

65.1p

FT

63.4p

1.5

[outDig]

195n

200n

205n

190n

195n

200n

205n

210n

215n

210n

215n

220n

60
volt (lin)

volt (lin)

190n
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4

volt (lin)

ph:avddk=1:avddhvk=12.5

DC 49.9%

50
40
30
20
10

0.5
[outSin]

60
50
(lin)

ph:avddk=1:avddhvk=1
ph:avddk=0.9:avddhvk=1.1
ph:avddk=1.1:avddhvk=0.9
2.5
ph:avddk=0.9:avddhvk=0.9
ph:avddk=1.1:avddhvk=1.1

30
20
10

RT

60p

FT

[outSin]
[outDig]

63.1p

60
50
(lin)

volt (lin)

40

1.5

40
30
20

10

DC 50.7%

0.5

(lin)

printed Wed Oct 10 2007 11:48:23 by lroicado on pc-lroicado

Figure 16: Digitalization of a 120 MHz sine wave with

1 V peak-to-peak amplitude.

0
400p

600p

800p

1n

1.2n

(lin)

1.4n

1.6n

printed Fri Sep 21 2007 16:09:15 by lroicado on pc-lroicado

1.8n

2n

220n
Sandwork Design, Inc. (c) 2000-2006

2.2n

Sandwork Design, Inc. (c) 2000-2006

Figure 15: Output of the new level converter, on the

typical case (above) and on the worst cases (bellow).
Table 3: Performance Measurements of the ADC before and after calibration.
Table 2: Results obtained with the new level converter,
on a simulation with 16 PVT corners and independent
variations of 10% on the supply voltages.
Parameter
tpLH
tpHL
td RR
td F F
factor de ciclo

Min
40
36
297
294
49.0

Typ
65
63
438
438
49.9

Max
101
104
631
652
52.2

Indicator
THD
SNR
ENOB

Unit
ps
ps
ps
ps
%

Initial
-37.1
29.9
4.7

Final
-38.8
33.3
5.2

Unit
dB
dB
bit

each one supplying different sections, as shown in Table 4. Thus, it was possible to draw the pie charts
showing the obtained results, as depicted in Fig. 18.
The total power dissipation of the ADC is 79 mW and
its overall current consumption is about 46 mA.

6.1. Sine Wave Sampling

Fig. 16 shows the analog input signal (vindif f ) and
the digital output codes of the ADC (outDig), as well
as the sine wave outSin that best fits the input signal
and was generated from the output digital words. As
we can see, the output signal matches (except for the
phase) the input sine wave.

Table 4: Voltage sources used to simulate the ADC

and corresponding sections supplied.

6.2. Evolution of the Performance of the

ADC with Calibration.
In order to check the efficiency of the calibration
mechanism, several performance measurements of the
ADC were calculated before the calibration starts and
in the end of this process. One of them - the ENOB
- was also tracked during this process. The results
obtained are shown in Table 3, where THD is the Total
Harmonic Distortion and SNR is the Signal-to-Noise
Ratio. We denote a decrease of almost 2 dB for the
THD, an increase of more than 3 dB for the SNR and
an improvement of 0.5 bit on the Effective Number of
Bits of this ADC.

Name
vavddref
vdvdd

#
#1
#2

Volt.
1.2
1.2

vavdd

#3

1.2

vavddhv

#4

2.5

Sections
CADC/FADC resistive ladders
digital correction, CADC
and FADCs digital blocks
CADC/FADC analog blocks,
IBias, top-level phases generat.
top/local level phases generat.,
samp. networks input switches

7. Conclusions and Future Work

This document presented an overview of the architecture, specifications, main design blocks and simulation results of a 65 nm CMOS 1.2 V 6-bit 1 GS/s TwoStep Subranging ADC, suitable for High-Frequency applications such as Ultra Wideband.
Flash architectures are the ones that allow us to
achieve the highest conversion rates. However, they
require (exponentially) more hardware and dissipate
more power. Employing a Two-Step Subranging ADC
the power consumption can be reduced at the same
time that the requirements of highly linear components is supressed. Two-Step Subranging ADCs are

Fig. 17 shows the evolution of the ENOB after

calibration is switched on. We can denote the initially
fast rising of this parameter from clock cycle to clock
cycle, starting from 4.7 bit and settling near the final
value of 5.2 bit.
In order to evaluate the power and current distribution in the ADC, several voltage sources were used,
7

bust, and allowed to obtain duty cycles in the range of

49.0 % to 52.2%, achieving the almost ideal value of
49.9% on the typical PVT corner.
The increase of 44 % in the power dissipated was
the price to pay to overcome these problems: while the
previous 600 MHz ADC dissipated 55 mW, this one,
running at 1 GHz, dissipates 79 mW and consumes 46
mA.

5.25
5.2
5.15
5.1
ENOB(bit)

5.05
5
4.95

After the ADC has been designed at an electrical

level, the next step would be to make its layout, after
which an RC extraction would be useful to verify if
the assumed and real parasitic resistances and capacitances are similar.
In what concerns the architecture, there is a suspect
that the pre-amplifier inside the Fine ADCs comparators can be eliminated. As it is implemented now, its
gain is 1 and thus it is acting as a buffer between the
sampling network and the latched comparator. This
could lead to a significant reduction in the power dissipated, as this is a static pre-amplifier biased with a
160 A current.

4.9
4.85
4.8
4.75
4.7
4.65

27

47

67
87
107 127 147 167
Clockcyclesaftercalibrationstarts

187

207

Figure 17: ENOB evolution with calibration.

VDD
27%
#3

VDD
8.5%
#2

VDDHV
57%
#4

VDD
7.5%
#1

(a) Power (% of 79 mW)

I(VDD)
5.6mA
#2
I(VDD)
17.9mA
#3

8. Acknowledgements
I(VDDHV)
18.0mA
#4

I thank Dr. Joao Vital for the excellent opportunity to accomplish this work at ChipIdea, Dr. Pedro
Figueiredo for all the support and transmitted knowledge, Engs. Ana Lopes, Goncalo Minderico and Paulo
Cardoso for their help, and my colleagues for their
friendship and technical discussions at lunch time.

I(VDD)
4.9mA
#1

(b) Current (mA)

References

Figure 18: Power dissipated and supply current distribution in the ADC, according to sections presented in
Table 4.

[1] B. Dudhia. Ultra Wide Band (UWB) Compatibility

Study. IEE Savoy Place London, July 2002. Science
& Technology Unit - Radiocommunications Agency.
[2] B. Ginsburg and A. Chandrakasan. A 500MS/s 5b
ADC in 65nm CMOS. Symposium on VLSI Circuits
Digest of Technical Papers, 2006.
[3] C. Sandner, M. Clara, A. Santner, T. Hartig, F.
Kuttner. A 6bit, 1.2GSps Low-Power Flash-ADC in
0.13pm Digital CMOS. Infineon Technologies, Austria.
[4] D. Johns and K. Martin. Analog Integrated Circuits
Design. John Wiley & Sons, 2004.
[5] J. Fernandes. Conversores A/D com Arquitecturas de
Tipo Paralelo. PhD thesis, Instituto Superior Tcnico,
Lisboa, Maro 2000.
[6] P. Figueiredo. High-Speed CMOS Analog-to-Digital
Converters. PhD thesis, IST, June 2006.
[7] L. Rong, E. Gustafsson, A. Rusu, M. Ismail. Systematic Design of a Flash ADC for UWB Applications. Electronics and Computer Systems Department, Royal Institute of Technology, Sweden, 2007.
[8] C. Mangelsdorf. A 400-MHz Input Flash Converter
with Error Correction. IEEE Journal of Solid-State
Circuits, 25(1), February 1990.
[9] P. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N.
Hamanishi, K. Tanabe, J. Vital. A 90nm CMOS 1.2V
6b 1GS/s Two-Step Subranging ADC. ISSCC, 2006.
[10] R. Geiger, P. Allen and N. Strader. VLSI Design Techniques for Analog and Digital Circuits. McGraw Hill,
1990.
[11] S. Lewis, H. Fetterman, G. Gross, R. Ramachandran
and T. Viswanathan. A 10-b 20-Msample/s analogto-digital converter. IEEE J. Solid-State Circuits,
27:351358, March 1992.
[12] A. Sedra and K. Smith. Microelectronics Circuits. Oxford University Press, 2004.
[13] Y. Tsividis. Mixed Analog-Digital VLSI Devices and
Technology. World Scientific, 3rd edition, 2005.

intrinsically slower than the Flash ADC, thus, 2 timeinterleaved Fine ADCs were employed to overcome this
speed limitation. The time constant of the reference
voltages during its settling period is about 60 ps. This
is short enough to ensure a right settling much before
the next sampling phase.
The offset voltage specifications of the Coarse ADC
is relaxed by the usage of redundancy. The maximum
offset voltage allowed to its comparators is 62.5 mV,
and Monte Carlo simulations on the typical PVT corner indicated (VOS )=6.3 mV, which is low enough.
The 2 Fine ADCs have implemented a calibration
mechanism that cancels offset voltages within a range
of 50 mV. Monte Carlo simulations showed that the
offset voltage of these comparators are lower than 5
mV. The calibration was also responsible for an increase of the ENOB from 4.7 bit to 5.2 bit and an
increase of the SNR greater than 3 dB.
To overcome the problem of high resistance of the
sampling networks input switches, a new switch with
a single thick-oxide transistor was studied and implemented. With this new switch, the maximum ON resistance has decreased from 87 k to 1.3 k on the
worst case PVT corner.
To drive these switches a new topology of level converter had to be studied and implemented to transform
1.2 V clock phases into 2.5 V clock phases. Common
level converters introduce great distortion on the duty
cycle at high frequencies. This level converter is ro8