Академический Документы
Профессиональный Документы
Культура Документы
AN60631 covers PSoC 3 and PSoC 5LP's highly versatile and reconfigurable clocking system. This application
note describes PSoC 3 and PSoC 5LP's oscillators and clock sources, phase-locked loop (PLL), and clock
distribution network. However, it does not cover the details of the external crystal oscillators (ECOs). For those
details, see AN54439 - PSoC 3 and PSoC 5LP External Crystal Oscillator.
Introduction
Clock Sources
Figure 1. PSoC 3 and PSoC 5LP Clock Source Options in the MHz Range
PSoC 5LP
Only
Legend
Phase-locked loop (PLL)
IMO Doubler
MHz external crystal oscillator (ECO)
Internal main oscillator (IMO)
10
20
30
40
50
60
70
80
www.cypress.com
MHz-range ECO
The MHz ECO contains an internal Pierce Oscillator circuit
that can be used with an external crystal or ceramic
resonator to generate frequencies within its operating
range of 4-25 MHz. This circuitry is shown in Figure 3.
ECOs typically offer much more accurate clock frequency
generation than built-in oscillators. The accuracy of the
ECO is determined by the specifications of the crystal or
resonator used, along with its loading capacitors. Typical
MHz resonator accuracies range in the tens of parts per
million (PPM). The MHz ECO in particular is especially
useful for high-speed communication where clock
accuracy is critical, such as in CAN or I2S communication,
or digital audio reproduction.
www.cypress.com
Xi
CL1
Xo
X1
CL2
32.768-kHz ECO
The 32.768 kHz ECO contains an internal Pierce
Oscillator circuit that can be used with an external crystal
resonator to generate a 32.768 kHz clock signal. The kHz
ECO has a dedicated 15-bit counter may be used to
derive a once per second interrupt. The kHz ECO is
especially useful for accurate timekeeping using PSoC 3
and PSoC 5LPs real-time clock (RTC).
Note AN54439 - PSoC 3 and PSoC 5LP External Crystal
Oscillators further explains usage of the MHz and kHz
ECOs.
Clocking Tree
PSoC 3 and PSoC 5LPs clocks can be understood in the
context of the clock tree. The clock tree divides down and
distributes clock signals in the part. PSoC 3 and
PSoC 5LPs clock propagation is shown in Figure 4.
USB Clock
PSoC 3 and PSoC 5LPs clocking architecture allows the
device to automatically trim the IMO to the USB traffic
External I/O
or DSI
0 - 33 MHz
12 MHz 48 MHz
Doubler
1/33/100 kHz
ILO
clk_imo2x
clk_imo
clk_pll
clk_dsi_glb
USB
Master
Clock Mux
PLL
8-bit Clock
Divider
clk_pll
clk_sync_d
7
dsi_d[n]
Digital (User)
Clock Mux and
16-Bit Divider
...
clk_sync_d
clk_imo
clk_xtal
clk_ilo
4
5
clk_pll
clk_32k
clk_dsi_glb
www.cypress.com
CPU Clock
BUS Clock
7
dsi_a[n]
clk_sync_a[n]
Analog (User)
Clock Mux and
16-Bit Divider
s
k
e
w
clk_a[n]
To DSI
...
x8
clk_ilo
clk_32k
clk_xtal
clk_dsi_glb
P3 Only
clk_imo
clk_imo2x
32.768 kHz
ECO
dsi_clkin
4 MHz - 25
MHz ECO
x4
www.cypress.com
www.cypress.com
16 Bit
Divider
1
2
clk_xtal
...
to DSI
clk_sync_d
clk_imo
clk_ilo
x8
4
5
clk_pll
clk_32k
clk_dsi
clk_d[n]
sync
Each user clock contains a dedicated input mux and a 16bit divider. User clocks may be resynchronized with the
master clock after division, if desired. Analog user clocks
may also be resynchronized with a phase-shifted version
of the master clock.
The input options for user clocks can be seen in Figure 8
and Figure 9. They include all 7 signals normally carried
on the clock bus, as well as dedicated DSI signals. These
dedicated signals include one dedicated DSI signal for
each user clock, and one dedicated phase-shifted version
of the master clock for each analog user clock.
There are three ways to create user clocks:
www.cypress.com
www.cypress.com
Both the IMO and the ILO trim registers can be modified
during operation to improve frequency accuracy. If a
reference clock source is available, this can improve the
accuracy of the IMO and ILO outputs significantly.
PSoC 3 and PSoC 5LP IMO and ILO trimming at runtime
are discussed in detail in AN80248, which also provides
an example project.
Implementing a system to trim clock sources at run time
requires measuring clock error against a reference clock
source, and modifying trim to improve the error. Measuring
error with a reference clock source can be implemented
multiple ways. If the signals are slow, such as the ILO, a
simple software counter can be implemented. A software
counter uses an interrupt to increment a count, and the
count is checked and cleared every second or so. Thus,
the detected frequency is equal to the count. For faster
clocks, digital hardware should be used. PSoC 3 and
PSoC 5LPs Counter component provides the perfect tool
for counting the number of MHz frequency clock edges in
a given period of time. The low frequency reference clock
should be used as the capture input to the Counter.
The IMO is trimmed using registers IMO_TR1 and
IMO_TR0. The 3 highest bits of IMO_TR0 make up the
least significant bits (LSB) of the 11 bit total trim. The
8 bits of IMO_TR1 are the most significant bits (MSB). The
IMOs frequency range from maximum to minimum trim is
approximately -33%/+25%. At 11 bits total, this results in
resolution of about 333 PPM per bit. At 333 PPM per bit,
trim can achieve 167 PPM or lower error every time.
Compared to the 1% or 2% accuracy of the IMO across
temperature at 3 MHz, a runtime trimmed system could be
much more accurate.
Summary
PSoC 3 and PSoC 5LPs powerful clocking systems offer
nearly infinite configuration possibilities. Understanding
this clock system will help optimize your project for
maximum performance.
Max Kingsbury
Title:
Background:
www.cypress.com
Document History
Document Title: AN60631 PSoC 3 and PSoC 5LP Clocking Resources
Document Number: 001-60631
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2901619
MAXK
03/30/2010
*A
3206913
MAXK
03/27/2011
*B
3348446
MAXK
08/22/2011
Clarified text.
Updated electrical specs in clock propagation diagram.
*C
3558896
MAXK
03/22/2012
*D
3714572
MAXK
08/16/2012
Added PSoC 5
Updated Diagrams and PLL Description
*E
3819235
MAXK
11/22/2012
*F
4341009
MEH
4/7/2014
*G
4670664
MEH
03/04/2015
Updated Figures 1 and 4 to reflect the 80 MHz clock option for 5LP.
Clarified some of the clock terminology
www.cypress.com
PSoC Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
Interface
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
Technical Support
cypress.com/go/support
PSoC is a registered trademark of Cypress Semiconductor Corp. PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or
registered trademarks referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
Cypress Semiconductor Corporation, 2010-2015. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
10