Pyxis Tool Working Flow

Right click on Desktop & open in terminal.

Type following command in terminal.

It will invoke Pyxis Navigator- Pyxis Project Manager window as shown below. Follow
the instructions as shown:-

 A New Project window will be open. It requires Project path & Library path. Browse the
appropriate location.

 Library path will be path of PDK as shown below.

After browsing the Library path, following windows will be shown. Click OK.

Will invoke another window as shown below. Click Add Standard Libraries.

 Following window will be shown. Click OK.

Following window will be shown. Right click on your Project name. Select New ->
Library.

 Give a name to Library.

Right click on your Library. Select New -> Cell

 Give a suitable name to Cell.

Right Click on your Cell. Select Schematic. Give a name to Schematic. Click Ok.

 Pyxis Schematic Window will be open as below.

Add Instance by clicking the icons as shown below or by pressing I key of keyboard.

 Browse generic 13 -> Symbols -> pmos or nmos. Place them on worksheet , as shown on
below figures.

 Create the Schematics as shown below. For VDD & Ground symbol, Instance by pressing
I key then browse generic_lib. Select VDD & Ground one by one from there. Give
name to the nets by selecting net names icons.

 Go to Add -> Generate Symbol to generate a symbol for your design.

Selecting Choose shape one can select shape of choice. But not mandatory. Click OK.

 Symbols for design is generated as follows.

Check and save by clicking the below shown icons.

 Make corrections if any error is shown else close the window.

Create a new cell under your library by giving a suitable name for generating a
schematic to functionally verify the created designs (in this case nand gate)

 Instance the symbol generated for your design by browsing library (nand) -> cell (nand)
using I- key of keyboard or instance icon.

Add appropriate sources to the symbol of design as shown below. Sources can be found
in sources_lib. Desired change in the sources can be done by right click on source and
selecting edit object or pressing Q-key.

 Create design as shown below.

Perform check and save by clicking check & save icon to find if there is any error.

 Enter in simulation mode by clicking icons shown in below fig.

Select New Design Configuration. Give a name to Design Configuration and click OK.

 Setup Simulation by clicking icons shown below.

In Analyses Select TRAN and make changes as shown below.

 In Libraries click Import Library.

Browse lib.eldo present in PDK -> Generic13 ->models-> lib.eldo and then click OK.

 Click OK

Using slider go to the bottom of window and click OK & Run

 This will simulate our designs. Once Simulation completed successfully comes in the
Message Area. We can see the waves by going to View Waves->Plot Latest Waves as
shown below.

A new window will pop up of EZwave.

 By clicking V(A), V(B) & V(Y). We can see the waves and functionally verify our design.

Now we need to create layout of our design. Go to cell of design right click then select
New & then Layout. Dont make any change in cell name.

 New Layout window will be open with following specifications. Click OK.

A SDL window of Pyxis Layout will be open. In /nand tab select Inst and place the
instance on Pyxis Layout window. Then select Port and place all ports on Pyxis Layout
window.

 In the following figure Instances (pmos & nmos) are placed on window after selecting
the Inst.

 In the following figure Ports are placed on window after selecting the Ports. Note that all
ports should be placed as a metal layer (M1). Layer can be changed by hitting Space
key.

Now we need to route the designs following yellow flying lines using Iroute icon. To
connect Poly and metal layer right click on port select via generator as shown below. Hit
space key after bringing cursor on port to generate Poly- Metal contact.

 Add psub towards nmos and nwell towards pnmos. To do this click from left most Icon
bar
Add device -> select $gb_p as shown in figure & complete the layout as
shown below.
To add name on ports. Select Add from Menu bar -> Add text on ports. Thus layout
design is completed.

Now to verify the designs. We need to use Calibre tools. To perform this, go to Tools
from menu bar go to Calibre -> Run DRC

 Click Run DRC.

Following fig shows DRC Summary Report.

Following this Calibre- RVE window pops up which enlists performed rules check and
violations. Correct the required rules violations.

 To perform LVS again go to Tools-> Calibre -> Run LVS

Run LVS. Make sure in Inputs Export from Layout & Export from Netlist are Marked, as
shown below.

 Following fig. shows LVS Report File.

A smiley ensures that Layout vs Schematic check has been verified successfully. If not
then cross check can be performed by selecting view-> Schematics. A comparison
window will be open as shown below.

 To perform parasitic extraction. Again go to Tools -> Calibre -> Run PEX.

Following figure Shows Parasitic Extracted Netlists. Desired format can be selected by
selecting Outputs in the window.