Chapter 7

Registers and Counters

Overview

Register
Shift register counters
Asynchronous counters
Synchronous counters
Design of synchronous
binary counters
Self-starting counters

Introduction
Register a set of flip flops used to store
binary data or information
Counter device used to count clock
pulses or number of events

Register

store and shift it

Serial in/ serial out

Serial in/ parallel out
Parallel in/ parallel out
Rotate right

Shift registers

Serial in/ serial out

The new bit is shifted into the register one bit at a time
4-bit shift register

Series in/ parallel out

Same result like series in/ series out register

Register with tri-state outputs

The data is usually sent through common data lines
called the data bus.
A bus is a group of wires that perform a common
function.
To prevent damage to outputs of inactive registers, the
outputs of the registers are connected to tri-state buffers.

*CE=Chip enable

Several registers can be connected to a data bus

Application Example: Parallel Adder with Accumulator

Register (store data)

adder
1 bit
X = x3x2x1x0 is stored in the accumulator
then the number Y = y3y2y1y0 is applied to the full adder
the sum of X and Y, S = X + Y.
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Shift register counters

Normally a rotate register
to produce a special sequences

Ring Counters
A ring counter is a circular shift register with one flip-flop in state 1 at a
particular time to produce a sequence of timing signals.

The shift registers serial output is fed back to the serial input.

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ring counter

Outputs:

*able to create 4 sequences

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To get more sequences, you required a special connection

Johnson counters (twisted-ring counters)

Not E,
but E
Feed back

the complement of the serial output E

fed back into the serial input.
For n-bit, the counter will have 2n unique
states.

*created 8 sequences
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Asynchronous counters
Idea to get more sequences
Ripple counter, state changes are not controllered by a
common clock pulse
Other FF
control by output

Only 1st FF
control by CLK

Because of propagation delays, the FFs

never trigger simultaneously
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Cumulative delay (limits)

Count sequence is 7, 6, 5, 4, 3, 2, 1, 0, repeats,
binary down counter
How to get binary up counter?
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Synchronous counters
Flip-flops are clocked simultaneously with a common
clock pulse

Example: a 3-bits synchronous counter

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Before

After

0
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Example: a modulo-N counters

Count from state 0 to state N-1 and repeats.

If N=10, we have a decade counter (mod-10)

0,1,2,3,4,5,6,7,8,9,0,1,2,3..

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0 1

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Extra Example: Up/down counters

An up/down counter or bi-directional counter can count in
either direction through any specified sequence of states

Have sequence of
*Please refer to Floyd p476 or Roth p335 for explanation.
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Design of Synchronous Binary Counters

to design a special sequence counter

to design finite state machine (finite = limited)
Counters with any count sequence can be
constructed with D, T, S-R, and J-K flip-flops
Systematic approach: use state table to relate
the next output to the present output

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4 steps to design a counter:

1)State Diagram
2)State Table
3)Logic Equations
4)Logic Circuit
General steps:
State Diagram

- specify the counter sequence and draw a state

diagram.
State Table
- Derive a next-state table
- Develop the flip-flop transition table showing
the excitation inputs required for each transition.
Logic Equations - Derive the K-maps for each input of each flipflop in the counter.
- Obtain the logic expressions for flip-flop
Logic Diagram - implement the counter (or logic circuit)
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Design a 3-bit synchronous counter using T flip flops.

1) State diagram

2) State Table

Need to know!

or this

Excitation inputs

State table of FF

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3) Logic Equations
TA =1
K-maps

4) Logic Circuit

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Design a 3 bit synchronous counter using D flip flops.

1) State diagram

2) State Table

Need to know!

or this

State table of FF

Excitation inputs

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3) Logic Equations

K-maps

4) Logic Circuit

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Design a counter using T flip-flops that count the

sequence 000, 100, 111, 010, 011, 000 and repeats.

1) State diagram

2) State Table
TC TB

TA
State table of FF

Excitation signal

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3) Logic Equations

K-maps

4) Logic Circuit

Please try this at home!!!

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Design a counter using S-R flip-flops that count the

sequence 000, 100, 111, 010, 011, 000 and repeats.

1) State diagram

2) State Table

State table of FF

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3) Logic Equations

K-maps

4) Logic Circuit
Please try to draw this yourself!!!

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Design a counter using J-K flip-flops that count the

sequence 000, 100, 111, 010, 011, 000 and repeats.

1) State diagram

2) State Table

State table of FF

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3) Logic Equations

K-maps

4) Logic Circuit
Please try to draw this yourself!!!
Now you should able to design a counter that count
any sequence using any D, T, SR or J-K flip flops.
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Self-starting Counters

When power is first applied, the

initial states of the flip-flops are not
predictable.
For counters that do not use all the
state combinations, we may start
with an invalid state and never
enter the designed sequence at all
A self-starting counters is one
where every possible state
including those not in the desired
count sequence, has a sequence
of transitions that eventually leads
to a valid counter state.

Example:

What would
happen if we start
with 001, 101 or
110?

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 It all depends on how the dont cares have been

mapped in the design.

Checking if counter is self-starting

Replace the dont cares in the K-maps with the actually
assigned 1s and 0s.
Remap the K-maps to obtain the effects on each flipflops state
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Replace the dont cares

Before

After

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If eventually no enter
to design sequence:
NEED to
Remap the K-maps
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