ECE 274 - Digital Logic

Chapter 8: Synchronous Sequential Circuits

Lecture 20 - State Minimization

Implication Tables (not in book)

Partitioning Method (8.6)

ECE 274 - Digital Logic

State Reduction (State Minimization)

Goal: Reduce number of states in FSM without changing behavior

Consider the two FSMs below with input sequence x =1, 1, 0, 0

Fewer states potentially reduces size of state register

Inputs: x; Outputs: y
x

x
x
S1

y=0

y=0
S1

x
S2

y=1
S0

state
x

x
x

S0

S1

x
S3

S0

y=1
S2

S1

y=0
S2

S0

state
x

y=1

S1

S1

S0

S0

For the same sequence of inputs,

the output of the two FSMs is the same

if x = 1,1,0,0
then y = 0,1,1,0,0

ECE 274 - Digital Logic

State Reduction: Equivalent States

Two states are equivalent if:

1. They assign the same values to
outputs

S0 and S2 both assign y to 0,

S1 and S3 both assign y to 1

2. AND, for all possible sequences of

inputs, the FSM outputs will be the
same starting from either state

Inputs: x; Outputs: y
x

x
x

S1

S2

S3

y=0

y=1

y=0

y=1

States S0 and S2 equivalent

States S1 and S3 equivalent
merge
equivalent
states

e.g. say x=1,1,0,0,

x
x

S0

starting from S1, y=1,1,0,0,

starting from S3, y=1,1,0,0,

x
S0,
S2
y=0

x
x

S1,
S3
y=1

ECE 274 - Digital Logic

State Reduction: Example with no Equivalencies
Inputs: x; Outputs: y

Another example

State S0 is not equivalent with

any other state since its output
(y=0) differs from other states
output

Consider state S1 and S3

x
S1

y=0

y=1

Initially the same (y=1)

From S1, when x=0, go to S2

where y=1
From S3, when x=0, go to S0
where y=0
Outputs differ, so S1 and S3
are not equivalent.

x
S2

S3

y=1

y=1

x
x

S0
y=0

x
x

S1
y=1

Start from S3, x=0

x
x

S0

x
x

S2

S3

y=1

y=1

y=0

Continue checking all possibilities

S0

All possible inputs, yield same

outputs

Start from S1, x=0

Output Assignment

x
x

S1
y=1

x
x

S2

S3

y=1

y=1

ECE 274 - Digital Logic

State Reduction with Implication Tables

State reduction through visual inspection (what we did in the last few slides)
isnt reliable and cannot be automated a more methodical approach is
needed: implication tables

Inputs: x; Outputs: y
x

x
x

S0
y=0

x
x

S1

y=0

y=1

S0

x
S2

S1

Redundant

S3
y=1

To compare every
pair of states,
construct a table of
state pairs

S2
Diagonal

S3
S0 S1 S2 S3

S1
S2

Remove state pairs along

the diagonal since a state
is equivalent to itself

S3
S0 S1 S2

Remove redundant state

pairs

ECE 274 - Digital Logic

State Reduction with Implication Tables

Step 1: Mark (with an X) state pairs with

different outputs as non-equivalent:

(S1,S0): At S1, y=1 and at S0, y=0. So

S1 and S0 are non-equivalent.
(S2, S0): At S2, y=0 and at S0, y=0. So
we dont mark S2 and S0 now.
(S2, S1): Non-equivalent
(S3, S0): Non-equivalent
(S3, S1): Dont mark
(S3, S2): Non-equivalent

After first pass

S2 & S0 might be equivalent

S3 & S1 might be equivalent

Only if their next states are equivalent

Inputs: x; Outputs: y
x

x
x

x
x

S0

S1

S2

S3

y=0

y=1

y=0

y=1

S1
S2
S3
S0

S1

S2

ECE 274 - Digital Logic

State Reduction with Implication Tables

Step 2: Check each unmarked state pairs next

states

Inputs: x; Outputs: y
x

x
x

x
x

S0

S1

S2

S3

y=0

y=1

y=0

y=1

(S2, S0)

Start by listing what each unmarked state pairs

next states are for every combination of inputs

From S2, when x=1 go to S3

From S0, when x=1 go to S1
So we add (S3, S1) as a next state pair
From S2, when x=0 go to S2
From S0, when x=0 go to S0
So we add (S2, S0) as a next state pair

S1
(S3, S1)
(S2, S0)

S2

(S3, S1)
(S0, S2)

S3

(S3, S1)

S0

By a similar process, we add the next state pairs

(S3, S1) and (S0, S2)

S1

S2

ECE 274 - Digital Logic

State Reduction with Implication Tables

Step 3: Next we check every unmarked state

pairs next state pairs

Inputs: x; Outputs: y
x

x
x

x
x

S0

S1

S2

S3

y=0

y=1

y=0

y=1

(S2, S0)

We mark the state pair if one of its next state

pairs is marked (i.e. not equivalent)

Next state pair (S3, S1) is not marked

Next state pair (S2, S0) is not marked
So we do nothing and move on

(S3, S1)
(S2, S0)

S2

(S3, S1)

S1

Next state pair (S3, S1) is not marked

Next state pair (S0, S2) is not marked
So we do nothing and move on

(S3, S1)
(S0, S2)

S3
S0

S1

S2

ECE 274 - Digital Logic

State Reduction with Implication Tables

We just made one pass through the

implication table

Make additional passes until no change

occurs

Step 4: merge the unmarked state pairs

as they are equivalent

Inputs: x; Outputs: y
x

x
x

S1,S3

y=0

y=1

S1

S2

S3

y=0

y=1

y=0

y=1

S1
S2

(S3, S1)
(S2, S0)
(S3, S1)
(S0, S2)

S3

x
S0,S2

x
x

S0

S0

S1

S2

ECE 274 - Digital Logic

State Minimization Using Implication Tables

Step

Description

Mark state pairs having different outputs as

nonequivalent

States having different outputs

obviously cannot be equivalent

For each unmarked state pair, write the next

state pairs for the same input values

For each unmarked state pair, mark state pairs

having nonequivalent next-state pairs as
nonequivalent. Repeat this step until no change
occurs, or until all states are marked.

States with nonequivalent next states

for the same input values cannot be
equivalent. Each time through this step
is called a pass.

Merge remaining state pairs

Remaining state pairs must be

equivalent.

10

ECE 274 - Digital Logic

State Reduction Example

Given FSM on the right

Inputs: x; Outputs: y

Step 1: Mark state pairs having

different outputs as nonequivalent

x
x

x
x

S0

S1

S2

S3

y=0

y=1

y=1

y=1

S1
S2
S3
S0

S1

S2

11

ECE 274 - Digital Logic

State Reduction Example

Given FSM on the right

Step 1: Mark state pairs having

different outputs as nonequivalent

Inputs: x; Outputs: y
x

x
x

Step 2: For each unmarked state

pair, write the next state pairs for
the same input values

x
x

S0

S1

S2

S3

y=0

y=1

y=1

y=1

S1

For pair (S2, S1)

For pair (S3, S1)

S2

(S2, S2)
(S3, S1)

S3

(S0, S2) (S0, S2)

(S3, S1) (S3, S3)

For pair (S3, S2)

X=0
S2 goes to S2
S1 goes to S2

X=0
S3 goes to S0
S1 goes to S2

X=0
S3 goes to S0
S2 goes to S2

X=1
S2 goes to S3
S1 goes to S1

X=1
S3 goes to S3
S1 goes to S1

X=1
S3 goes to S3
S2 goes to S3

S0

S1

S2

12

ECE 274 - Digital Logic

State Reduction Example
Inputs: x; Outputs: y

Given FSM on the right

Step 1: Mark state pairs having

different outputs as nonequivalent
Step 2: For each unmarked state pair,
write the next state pairs for the same
input values

x
S2

S3

y=0

y=1

y=1

y=1

S2

(S2, S2)
(S3, S1)

S3

(S0, S2) (S0, S2)

(S3, S1) (S3, S3)

Repeat this step until no change occurs,

or until all states are marked.
S2 = S2? Yes

x
x

S1

S1

Step 3: For each unmarked state pair,

mark state pairs having nonequivalent
next state pairs as nonequivalent.

x
x

S0

S0

S1

S2

Repeat

S3 = S1? Unsure

S2 = S2? Yes

S0 = S2? NO!

S3 = S1? NO!

S0 = S2? NO!
13

ECE 274 - Digital Logic

State Reduction Example
Inputs: x; Outputs: y

Given FSM on the right

x
x

Step 2: For each unmarked state pair,

write the next state pairs for the same
input values

x
x

S0

S1

S2

S3

y=0

y=1

y=1

y=1

S1

Step 3: For each unmarked state pair,

mark state pairs having nonequivalent
next state pairs as nonequivalent.

Step 1: Mark state pairs having

different outputs as nonequivalent

S2

(S2, S2)
(S3, S1)

S3

(S0, S2) (S0, S2)

(S3, S1) (S3, S3)

Repeat this step until no change occurs,

or until all states are marked.

S0

S1

S2

Step 4: Merge remaining state pairs

All state pairs are marked there are no
equivalent state pairs to merge
14

ECE 274 - Digital Logic

A Larger State Reduction Example

Inputs: x; Outputs: y

Try another example

Step 1: Mark state pairs having different

outputs as nonequivalent

x
S3

y=0

S0

S4

y=0

y=0

x x

(S1,S0)? No

S2

S1

y=1

y=1

(S2,S0)? No
(S2,S1)? OK

S1

(S3,S0)? OK
(S3,S1)? No
(S3,S2)? No

S2

S3

(S4,S0)? OK
(S4,S1)? No
(S4,S2)? No

S4
S0

S1

S2

S3

(S4,S3)? OK
15

ECE 274 - Digital Logic

A Larger State Reduction Example

Inputs: x; Outputs: y

Try another example

Step 1: Mark state pairs having different

outputs as nonequivalent

y=0

x
S3

S0

S4

y=0

y=0

x x

Step 2: For each unmarked state pair,

write the next state pairs for the same
input values

S2

S1

y=1

y=1

S1

For pair (S3, S0)

For pair (S2, S1)

X=0
S2 goes to S3
S1 goes to S4

X=0
S3 goes to S3
S0 goes to S2

X=1
S2 goes to S2
S1 goes to S1

X=1
S3 goes to S0
S0 goes to S1

Repeat for
(S4, S0) pair
(S4, S3) pair

(S3,S4)
(S2,S1)

S2
S3 (S3,S2)
(S0,S1)
S4

(S4,S3)
(S0,S0)

(S4,S2)
(S0,S1)
S0

S1

S2

S3

16

ECE 274 - Digital Logic

A Larger State Reduction Example

Try another example

Inputs: x; Outputs: y
x

Step 1: Mark state pairs having

different outputs as nonequivalent

y=0

x
S3

Repeat this step until no change

occurs, or until all states are
marked.

S0

S4

y=0

y=0

x x

Step 2: For each unmarked state

pair, write the next state pairs for
the same input values
Step 3: For each unmarked state
pair, mark state pairs having
nonequivalent next state pairs as
nonequivalent.

x
x
S2

S1

y=1

y=1

S1

(S3,S4) - OK
(S2,S1) - OK

(S3,S4)
(S2,S1)

S2

(S3,S2) - NO
(S4,S2) - NO
(S4,S3) - OK

S3 (S3,S2)
(S0,S1)

(S0,S0) - OK

(S4,S3)
(S0,S0)

(S4,S2)
S4
(S0,S1)
S0

S1

S2

S3

17

ECE 274 - Digital Logic

A Larger State Reduction Example

Try another example

Step 1: Mark state pairs having

different outputs as
nonequivalent

Inputs: x; Outputs: y
x

x
S3

y=0

S0

S4

y=0

y=0

x x

Step 2: For each unmarked state

pair, write the next state pairs for
the same input values
Step 3: For each unmarked state
pair, mark state pairs having
nonequivalent next state pairs as
nonequivalent.
Step 4: Merge remaining state
pairs
Combine (S2, S1) and (S4, S3)

S2

S1

y=1

y=1

S1
(S3,S4)
(S2,S1)

S2
S3 (S3,S2)
(S0,S1)
S4

(S4,S3)
(S0,S0)

(S4,S2)
(S0,S1)
S0

S1

S2

S3

18

ECE 274 - Digital Logic

A Larger State Reduction Example

Try another example

Step 1: Mark state pairs having

different outputs as
nonequivalent

Inputs: x; Outputs: y
x

x
x

S3

y=0

y=0

S0

S4
x

y=0

x x

S2

Step 2: For each unmarked state

pair, write the next state pairs for
the same input values
Step 3: For each unmarked state
pair, mark state pairs having
nonequivalent next state pairs as
nonequivalent.

y=1

Step 4: Merge remaining state

pairs

y=1
Combine (S2, S1)
and (S4, S3)

Inputs: x; Outputs: y
x

S3,S4
y=0

S1

S0

S1,S2

y=0

y=1

19

ECE 274 - Digital Logic

Partitioning Method

State Minimization

Partitioning method using State Table

Create partitions (groups) of
equivalent states

States in same partition might be

equivalent
States in different partitions are not
equivalent

Creating partitions uses same

equivalence test

Two states are equivalent if

They assign the same values to outputs

AND, for all possible sequences of
inputs, the FSM outputs will be the
same starting from either state

Inputs

Outputs

Current
State

Next
State

A
A
B

0
1
0

B
C
D

1
1
1

B
C
C
D

1
0
1
0

F
F
E
B

1
0
0
1

E
E
F

0
1
0

F
G
G

1
0
1

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

20

ECE 274 - Digital Logic

Partitioning Method

Initial partition contains all

states
First test

Group according to states

output value

Group (ABD) outputs 1

Group (CEFG) outputs 0

P1 = (ABDCEFG)
P2 = (ABD)(CEFG)

Inputs

Outputs

Current
State

Next
State

A
A
B
B
C
C
D

0
1
0
1
0
1
0

B
C
D
F
F
E
B

1
1
1
1
0
0
1

E
E
F
F
G
G

0
1
0
1
0
1

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

21

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

P2 = (ABD)(CEFG)

When w = 0
A goes to B
B goes to D
D goes to B

When w = 1
A goes to C
B goes to F
D goes to G

B, D, and B are in
same partition so
maybe same state

C, F, and G are in
same partition so
maybe same state

Outputs

Current
State

Next
State

A
B

1
0

C
D

1
1

C
C
D

0
1
0

F
E
B

0
0
1

E
F

1
0

F
G

1
0

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

22

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

P2 = (ABD)(CEFG)

When w = 0
C goes to F
E goes to F
F goes to E
G goes to F

When w = 1
C goes to E
E goes to C
F goes to D
G goes to G

F, F, E, and F are in
same partition

D is in different
partition then E, C, G!

Outputs

Current
State

Next
State

A
A
B

0
1
0

B
C
D

1
1
1

B
C
C
D

1
0
1
0

F
F
E
B

1
0
0
1

E
E
F

0
1
0

F
G
G

1
0
1

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

Move F into its own

partition

23

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

P3 = (ABD)(CEG)(F)

New partitions start over!

When w = 0
A goes to B
B goes to D
D goes to B

When w = 1
A goes to C
B goes to F
D goes to G

B, D, and B are in
same partition

F is in different
partition than C and G!
Move B to its own
partition.

Outputs

Current
State

Next
State

A
A
B
B
C
C
D

0
1
0
1
0
1
0

B
C
D
F
F
E
B

1
1
1
1
0
0
1

E
E
F
F
G
G

0
1
0
1
0
1

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

24

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

P4 = (AD)(B)(CEG)(F)

New partitions start over!

When w = 0
A goes to B
D goes to B

When w = 1
A goes to C
D goes to G

B and B in same
partition

C and G in same
partition

Outputs

Current
State

Next
State

A
B

1
0

C
D

1
1

C
C
D

0
1
0

F
E
B

0
0
1

E
F

1
0

F
G

1
0

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

25

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

P4 = (AD)(B)(CEG)(F)

B should be
equivalent to itself,
move to next group

Outputs

Current
State

Next
State

A
A
B

0
1
0

B
C
D

1
1
1

B
C
C
D

1
0
1
0

F
F
E
B

1
0
0
1

E
E
F

0
1
0

F
G
G

1
0
1

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

26

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

P4 = (AD)(B)(CEG)(F)

When w = 0
C goes to F
E goes to F
G goes to F

When w = 1
C goes to E
E goes to C
G goes to G

F, F, F in same
partition

E, C, G in same
partition

Outputs

Current
State

Next
State

A
A
B
B
C
C
D

0
1
0
1
0
1
0

B
C
D
F
F
E
B

1
1
1
1
0
0
1

E
E
F
F
G
G

0
1
0
1
0
1

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

27

ECE 274 - Digital Logic

Partitioning Method

Inputs

Second test

For all possible sequences of inputs,

the FSM outputs will be the same
starting from either state

Next
State

A
B

1
0

C
D

1
1

P4 = (AD)(B)(CEG)(F)

F should be
equivalent to itself,
move to next group

No new partitions generated Done!

Outputs

Current
State

C
C
D

0
1
0

F
E
B

0
0
1

E
F

1
0

F
G

1
0

F
C
E
D
F
G

0
0
0
0
0
0

** Use state name instead of

encoding to simply table

Combine (AD) and (CEG)

28

ECE 274 - Digital Logic

Need for Automation

What happens when FSM get even bigger?

Table for large FSM too big for humans to work with
100 states would have table with 100*100=100,000 state pairs cells

Automation needed

State reduction typically automated

Often using heuristics to reduce compute time
Inputs: x; Outputs: z
x
x

SB

SI
SO

SH

SA
x

z=1

z=0
z=1

SC
z=0

z=0

x
x

SD

x
x

SG
z=0

z=1
x

SK
SF

SE
z=0

z=0

z=0

x'
SM

SJ
x

z=1

z=1

SL
x

z=0

SN
x

z=1

z=1

29