Spring 2016

ECE 445 - Computer Organization

INTERRUPTS
ECE 445 Computer Organization
Dr. Craig Lorie
Electrical and Computer Engineering
Lecture #16

Spring 2016

ECE 445 - Computer Organization

Learning Objectives
Interrupts, exceptions, and traps.
Maskable and non-maskable interrupts.
Non-vectored, vectored, and auto-vectored interrupts.
Interrupt priorities.
Interrupt handling and interrupt service routines (ISR).

Spring 2016

Assigned Reading
H/P 4.9

ECE 445 - Computer Organization

Spring 2016

ECE 445 - Computer Organization

INTERRUPTS
Interrupts, exceptions, and traps.
Maskable and non-maskable interrupts.
Non-vectored and vectored interrupts.
Interrupt priorities.

Spring 2016

ECE 445 - Computer Organization

Interrupts
An interrupt is a signal, generated by hardware or software, to

the processor that indicates the occurrence of an event that

needs immediate attention.
Interrupts change the normal flow of program execution.
Interrupts are handled similarly to function calls.
An interrupt, more generally, refers to

Interrupts
2. Exceptions
3. Traps
1.

Sometimes referred to as discontinuities

Handling a Discontinuity

A discontinuity can be handled in a similar way to

the way in which a procedure call (and return)
is handled.

Spring 2016

ECE 445 - Computer Organization

Spring 2016

ECE 445 - Computer Organization

Interrupts
An event caused by an external (I/O) device.
A device, such as the keyboard or mouse, requests service.
A hardware device fails (i.e. hardware failure).
An external signal (from the device to the processor) indicates

the occurrence of an interrupt.

Known as an interrupt request (IRQ) signal.

The processor must stop execution of the current program and

handle the interrupt.

Spring 2016

ECE 445 - Computer Organization

Exceptions
An event generated internally by the processor.
The result of an erroneous condition encountered during

program execution.
Divide-by-zero.
Illegal instruction.

An internal signal indicates the occurrence of an exception.

The program being executed (which caused the exception)

must handle the exception.

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ECE 445 - Computer Organization

Traps
An event generated internally by the processor.
Also known as a software interrupt.
The program requests service from the system
For example, to communicate with the disk controller.
System call
Uses special (i.e. privileged) instructions.
An internal signal indicates the occurrence of a trap.
The operating system must handle traps.
Traps cannot be handled by the executing program.

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Maskable and Non-maskable

Maskable Interrupts
Can be masked (or disabled) through special flag bits.
Global Interrupt Enable (GIE) bit.
Interrupt Enable (IE) bit of external (I/O) device.

Most common type of interrupt.

By default, all maskable interrupts are disabled when executing an

interrupt service routine (ISR).

An interrupt service routine (ISR) is special code used to handle an interrupt.

Non-maskable Interrupts
Cannot be masked (or disabled).
Thus, non-maskable interrupts are always serviced.
They are reserved for system critical events.

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Interrupt Handling

ECE 445 - Computer Organization

1.
2.
3.

4.
5.
6.

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CPU receives interrupt request.

CPU saves state and clears GIE bit
(disables maskable interrupts).
PC loaded with starting address of
interrupt service routine (ISR) for
the device that caused the
interrupt.
Interrupt service routine is
executed.
CPU state restored and GIE bit set
(enables maskable interrupts).
Interrupted program is resumed.

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Detecting Interrupts
Exceptions
Illegal instructions are detected by the control unit.
Arithmetic overflow (V) is detected by the ALU.
Traps
A trap is detected when a system call (i.e. special instruction) is executed.
Interrupts (external)
Additional signals must be included in the datapath to support interrupts.
Interrupt Request (IRQ or INTR)
Interrupt Acknowledge (IACK or INTA)

The interrupting device asserts the interrupt request line.

Multiple devices can assert the IRQ line at the same time.

The processor may respond by asserting the interrupt acknowledge line.

Detecting a Discontinuity

An interrupt can occur at any time during

instruction execution.
Even in the middle of the instruction.

When should the interrupt be detected?

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Detecting a Discontinuity
The processor should check for interrupts only after
the current instruction has completed execution.
The processor samples the INT line to determine if
there is a pending interrupt.
If there is a pending interrupt it must be handled.
If not, the processor continues executing program
instructions normally.

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The Control Unit FSM

Fetch

Decode

INT = no

Execute

INT = yes

INT

After EXECUTE state, check for pending interrupts.

If pending interrupts exist, branch to INT state.
Else, branch to FETCH state to begin fetch/decode/execute of next
program instruction.
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Interrupt Identification Methods

Non-vectored Interrupts
Single, multi-drop interrupt request (IRQ) line.
One interrupt service routine (ISR) for all interrupting devices.
CPU identifies interrupt source by polling service request (SRQ) flags.

Introduction to Embedded Systems using Microcontrollers and the MSP430; Jimenez, Palomera, Couvertier; p. 305

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Interrupt Identification Methods

Vectored Interrupts
Requires an Interrupt Acknowledgement (INTA) cycle.
The interrupting device generates an ID number (or vector) as part of the
interrupt acknowledgement (INTA) cycle.
The vector is used to determine the location of the interrupt service
routine (ISR) in the program memory.

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Interrupt Identification Methods

Auto-vectored Interrupts
Each interrupting device has a fixed vector or a fixed ISR address.
No interrupt acknowledgement (INTA) cycle or vector issuing required.
CPU loads the ISR address of the interrupting device directly into the PC
to execute the interrupt service routine (ISR).
The MSP430 MCUs use auto-vectored interrupts.

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Interrupt Vector Table

A table (in memory) that contains the starting address of each

interrupt service routine (ISR).

Each interrupt has an associated interrupt service routine.

Each interrupt is assigned a unique ID (or vector).

The vector serves as an index into the interrupt vector table.
For vectored interrupts, the CPU uses the interrupt vector table

to determine the address of the ISR for the interrupting device.

Spring 2016

ECE 445 - Computer Organization

Interrupt Vector Table

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ECE 445 - Computer Organization

Interrupt Vector Table

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Interrupts and the IVT

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Interrupt Priority Handling

Interrupt Priority Management
Strategy to resolve multiple, simultaneous interrupt requests.
The priority scheme determines which interrupt is serviced first.
Non-vectored Interrupts
The polling order of the SRQ flags determines the interrupt priority.
Vectored and Auto-vectored Interrupts
Hardware supported.
Daisy-chain based.
Interrupt controller based.

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Interrupt Priority Handling

Daisy-chain based Arbitration
Devices connected in a daisy-chain configuration.
Interrupt priority of each device established by the hardware.
The closer the device to the CPU the higher the priority.

Introduction to Embedded Systems using Microcontrollers and the MSP430; Jimenez, Palomera, Couvertier; p. 307

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Interrupt Priority Handling

Interrupt Controller based Arbitration
Uses a central arbiter for resolving priorities.
Reduces interface overhead for vectored interrupts.
Allows priority scheme to be configured.

Introduction to Embedded Systems using Microcontrollers and the MSP430; Jimenez, Palomera, Couvertier; p. 309

Handling Interrupts

What if a second interrupt (or exception or trap)

occurs while the first is being handled?
How are nested (i.e. cascaded) interrupts handled?

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Cascaded Interrupts
Disable interrupts while handling the first.
However, processor must be able to handle
multiple interrupts.
So, disable interrupts while in INT state.
should be disabled implicitly by hardware.

Transfer control to interrupt handler

Where interrupts are, again, enabled.

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ECE 445 - Computer Organization

MIPS (MULTI-CYCLE)
Interrupt (exception) handling.

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MIPS (Multi-Cycle)
The multi-cycle implementation of the MIPS processor has

been designed to handle two different exceptions:

Illegal Instruction
2. Arithmetic Overflow
1.

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ECE 445 - Computer Organization

MIPS (Multi-Cycle)

Computer Organization and Design, 3rd Edition; Hennessey and Patterson; p. 344

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ECE 445 - Computer Organization

MIPS (Multi-Cycle Datapath)

Datapath components added to the MIPS multi-cycle

implementation to support interrupt handling.

Stores the address of the instruction that

caused the exception (interrupt).

Exception Program Counter

Cause Register
Stores a code that indicates the reason
for the exception (interrupt).

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ECE 445 - Computer Organization

MIPS (Multi-Cycle Control Unit)

Control signals added to the MIPS multi-cycle

implementation to support interrupt handling.

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MIPS (Multi-Cycle Control Unit)

Computer Organization and Design, 3rd Edition; Hennessey and Patterson; p. 345

Spring 2016

ECE 445 - Computer Organization

MIPS (Multi-Cycle Control Unit)

Additional states added to the Control Unit FSM

to support interrupt handling.

Arithmetic Overflow

Illegal Instruction

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MIPS (Multi-Cycle) Exceptions

The MIPS detects the different exceptions at different stages of

instruction processing.
An illegal instruction is detected after the instruction is decoded.
An arithmetic overflow is detected after the calculation is performed.

The MIPS handles exceptions as follows

1. Saves the address of the instruction that caused the exception.
R[EPC] = R[PC] 4
2. Loads the exception code into the Cause register.
R[Cause] = exception code
3. Loads the address of the interrupt service routine into the PC.
R[PC] = address of interrupt service routine
4. Executes the interrupt service routine.
5. If possible, returns to interrupted program.

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ECE 445 - Computer Organization

MIPS (PIPELINED)
Interrupt (exception) handling.

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Spring 2016

ECE 445 - Computer Organization

MIPS (Pipelined) Exceptions

See pp. 327 332 of B/V text.

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Spring 2016

ECE 445 - Computer Organization

Questions?

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