THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 1014
DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=684
Semester II 2009

1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

2
Combinational Logic using Multiplexers

Lab Weighting:

4%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Year 1 Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 1014

Theoretical content link: given at top of page
Pre-Requisites None
To undertake this lab, students should be able to:

Recommended
prior knowledge
and skills3:
Course Staff
Lucien Ngalamou
Marcus George

Position/Role
Lecturer
Instructor

Estimated total
study hours1:

E-mail

lucien.ngalamou@sta.uwi.tt
marcus.george@sta.uwi.tt

Phone


Office
room 202
room 203

Office
Hours

Lab 2: Combinational Logic using Multiplexers

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Use a multiplexer to construct a comparator and a parity generator and test
the circuit.
2. Use an N- input multiplexer to implement a truth table containing 2N
inputs.
3. Troubleshoot a simulated failure in a test circuit.

3.

PRE-LAB

Due Date:
Submission
Procedure:
Estimated time to
completion:

N/A
N/A
1 hour

3.1. Required Reading Resources

3.2. Recommended Reading Resources
Floyd, Digital Fundamentals with PLD Programming, Chapter 8, "Functions of
Combinational Logic," Sections 8-4 through 8-10
3.3. Other Resources

Cognitive
Level
C, Ap
C, Ap
C

Lab 2: Combinational Logic using Multiplexers

3.4. Pre-Lab Exercise

3.4.1 Reading Exercise: Summary of Theory
The multiplexer or data selector connects anyone of several inputs to a single output. The
opposite function, in which a single input is directed to one of several outputs, is called a
demultiplexer or a decoder. These definitions are illustrated in Figure 12-1. Control is determined
by additional logic signals called the select (or address) inputs.

Multiplexers (MUXs) and demultiplexers (DMUXs) have many applications in digital

logic. One useful application for MUXs is implementation of combinational logic functions
directly from the truth table. For example, an overflow error detection circuit is described by the
truth table shown in Figure 12-2(a). Overflow is an error that occurs when the addition of signed
numbers produces an answer that is too large for the register to which it is assigned. The truth
table indicates that output X should be logic 1 (indicating overflow) if the inputs (labeled A4, B4,
4) are 0, 0, 1, or 1, 1, 0, which happen when there is an overflow error. Notice that each of the
lines on the truth table corresponds to one of the 8 inputs on the MUX. On the MUX, the 001 and
110 lines are lines D1 and D6. The data itself controls which line is active by connecting it to the
Select inputs. The D1 and D6 lines are tied HIGH, so when they are selected the output of the
MUX will also be HIGH. All other data inputs on the MUX are tied to a LOW. When one of the
other inputs is selected, a LOW is routed to the output, thus implementing the truth table. This
idea is shown conceptually in the diagram in Figure l2-2(b).
Actually, an 8-input MUX is not required to implement the overflow detection logic. Any

Lab 2: Combinational Logic using Multiplexers

N-input MUX can generate the output function for 2N inputs. To illustrate, we reorganize the
truth table in pairs, as shown in Figure 12-3(a). The inputs labeled A4 and B4 are used to select a
data line. Connected to that line can be a logic 0, 1, 4, or

4.

For example, from the truth

table, if A4 = 0 and B4 = 1, the D1 input is selected. Since both outputs are the same (in this case
a logic 0), then D1 is connected to a logic O. If the outputs were different, such as in the first and
fourth rows, then the third input variable, 4, would be compared with the output. Either the true
(or NOT) form of that variable then would be selected. The results are shown conceptually in
Figure 12-3(b), which is equivalent to but simpler than the circuit in Figure 12-2(b).

In this experiment you will use an 8:1 MUX to implement a 4-input truth table (with 16
combinations). First you will develop the circuit to implement a special comparator. In the For
Further Investigation section the circuit is modified to make a parity generator for a 4-bit code.
Parity is an extra bit attached to a code to check that the code has been received correctly. Odd
parity means that the number of l's in the code, including the parity bit, is an odd number. Odd or
even parity can be generated with exclusive-OR gates, and parity generators are available in IC

Lab 2: Combinational Logic using Multiplexers

form. However, the implementing of an arbitrary truth table using MUXs is the important
concept.

Lab 2: Combinational Logic using Multiplexers

4.

IN-LAB

Allotted Completion 3 hours

Time:
1 - Oscilloscope
Required lab
1 - Lamda Dual Power Supply
Equipment:
1 - breadboard
1 - 74151A data selector/multiplexer
1 - 7404 hex inverter
1 - LED (yellow)
Resistors: one 330 , four 1.0 k

4.1. In-Lab Procedure

Special 2-Bit Comparator
1. Assume you needed to compare two 2-bit numbers called A and B to find whether A is equal to
or greater than B. You could use a comparator and OR the A > B and A = B outputs. Another
technique is to use an 8:1 MUX with the method shown in the Summary of Theory section.
The partially completed truth table for the comparator is shown as Table 12-1 in the report.

The inputs are A2, A1 and B2, B1, representing the two numbers to be compared. Notice
that the A2, A1 and B2 bits are connected to the SELECT inputs of the MUX. The B1 bit
is available to be connected as needed. It is therefore listed in a separate column of the
truth table.

Determine the logic in which the output represents A > B and complete the X column of
truth Table 12-1. The first two entries are completed as an example.

2. Look at the output X, in groups of two. The first pair of entries in X is the complement of the
corresponding entries in B1; therefore, the data should be connected to

1,

as shown in the first

line. Complete Table 12-1 by filling in the last column with either 0, 1, B1, or

3. Using the data from Table 12-1, complete the circuit drawing shown as Figure 12-4 in the
report. The X output on the truth table is equivalent to the Y output on the 74151A. From the
manufacturer's data sheet, determine how to connect the STROBE input (labeled

1).

Construct

the circuit and test its operation by checking every possible input. Demonstrate your working
circuit to your instructor.

Lab 2: Combinational Logic using Multiplexers

4.2 Further Investigation Procedure

Parity Generator Using a Multiplexer
The technique to implement an arbitrary function can also generate either odd or even parity.
The MUX can generate both odd and even parity at the same time because there are two
complementary outputs. One interesting aspect of the parity generator circuit is that any of the four
inputs can turn the LED on or off in a manner similar to the way in which 3-way switches can turn
a light on or off from more than one location. The truth table is shown in the report as Table 12-2.
Four of the bits (A3 through Ao) represent the information, and the fifth bit (X), which is the
output, represents the parity bit (this will be taken from the Y output of the 7415IA). The
requirement is for a circuit that generates both odd and even parity; however, the truth table will be
set up for even parity. Even parity means that the sum of the 5 bits, including the output parity bit,
must be equal to an even number.
1. Complete truth Table 12-2 to reflect this requirement. The first line has been completed as an
example. The even parity bit is taken from the Y output of the 74151A. The

output will be

LOW when Y is HIGH and lights the LED.

2. Using the truth table completed in Step 1, complete the schematic for the even parity generator
that is started in Figure 12-5 of the report. Change your original circuit into the parity circuit
and test its operation.

Lab 2: Combinational Logic using Multiplexers

4.3 Report for Lab 2

4.3.1 Data and Observations [total = 11 marks]

General Note for filling out Table 12-1:

Output to connect data to
Input B1

B1

Logic 0 (Connected to GND)

Logic 1 (Connected to VCC)

Lab 2: Combinational Logic using Multiplexers

4.3.2 Further Investigation Results [total = 11 marks]

General Note for filling out Table 12-2:

Output to connect data to
Input A0

A0

Logic 0 (Connected to GND)

Logic 1 (Connected to VCC)

Lab 2: Combinational Logic using Multiplexers

4.3.3 Evaluation and Review Questions [total = 20 marks]

1. Design a invalid code detector for the range of numbers 0 7, using a 74151A. For this detector
the numbers 0, 1, 4 and 7 are seen as valid while 2, 3, 5 and 6 are seen as invalid. Show the
connections for your design on Figure 12-6.For this question lets consider that the input
port A0 is used to indicate validity of the numbers as shown in the Further
investigation section of this lab. A0 (logic 1) indicates that the number is invalid while
(logic 0) indicates that the number is valid.[8 marks]

2. Can you reverse the procedure of this experiment? That is, given the circuit, can you find the
Boolean expression? The circuit shown in Figure 12-7 uses a 4: 1 MUX. The inputs are
called A2, A1, and Ao. The first term is obtained, by observing that when both select lines are
LOW, A2 is routed to the output; therefore the first minterm is written A2 1 0 Using this as
an example, find the remaining minterms. Show all working. [4 marks]
X = A2

+ ___________________________________________________

Lab 2: Combinational Logic using Multiplexers

3. Assume the circuit shown in Figure 12-4 had the correct output for the first half of the truth
table but had some incorrect outputs for the second half of the truth table. You decide to change
ICs (not necessarily the best choice!) but the problem persists.
a. What is the most likely cause of the problem? [1 mark]

b. How would you test the circuit for your suspected problem? [1 mark]

4. Assume the circuit in Figure 12-4 had a short to ground on the output of the inverter.
a. What effect would this have on the output logic? [1 mark]

b. What procedure would you use to find the problem? [2 marks]

5. Assume that the input to the 7404 in Figure 12-4 was open, making the output, 1 a constant
LOW. Which lines on the truth table would give incorrect readings on the output? [2 mark]

6. How can both odd and even parity be obtained from the circuit in Figure 12-5? [1 mark]

Lab 2: Combinational Logic using Multiplexers

Proceed to post-lab exercise.

Lab 2: Combinational Logic using Multiplexers

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:

Hard copies of the report must be submitted to the graduate

assistant immediately at the end of the laboratory exercise.

Please write your Name, ID number, and group letter and the data
at the front of the lab script.

Deliverables:

Students are expected to complete the lab scripts for this exercise
and submit at the end of the lab exercise.

End of Lab 2: Combinational Logic using Multiplexers

Lab 2: Combinational Logic using Multiplexers