Digital Manual

Shankersinh Vaghela Bapu Institute Of Technology.
Digital Electronics
Enroll. No:
SHANKERSINH VAGHELA BAPU INSTITUTE OF

TECHNOLOGY
DIGITAL ELECTRONICS
[2131004]
LABORATORY MANUAL
B.E. 3rd SEMESTER-2014-15
SHANKERSINH VAGHELA BAPU INSTITUTE OF

TECHNOLOGY
Gandhinagar-Mansa Road, PO. Vasan,
0

Digital Electronics
Gandhinagar District, Gujarat,

Pin. 382650
INDEX
Sr.
No.
Title
Page
1.
Verify truth table of all logic gates.
Prove NAND & NOR as Universal Gates.
3.
Realization of half and full adder and half &

full subtractor.
4.
Design and realization of binary to gray code

converter.
5.
Study of multiplexer and realization of

Boolean function using it.
6.
To design binary to seven segments LED

display circuit.
7.
Verification of truth tables of RS, D, JK and

T flip flops.
8.
To design and realize modulo N Synchronous

counter using JK flip-flops.
9.
To design and realize modulo N Ripple

counter using T flip flops.
Date
Sign
Marks

Digital Electronics
10.
To realize shift register.
Date:
/20
Exp. No.: 1.
Title
: Logic Gates
____________________________________________________________________________
_
AIM : To verify truth tables of all logic gates.
EQUIPMENTS:
[1] Logic trainer
[2] IC 7400 ,
[3] IC7402,
[4] IC7408,
[5] IC7432,
[6] IC7486,
[7] Connecting wires.
THEORY:
A gate is a logic circuit that has one or more inputs and one or more outputs. The output of the
gate will depend upon the set of input conditions. The digital signal has two distinct states
LOW (0) and HIGH (1). Using gates we can implement variety of logic circuit that performs a
particular task. For an example we can implement various arithmetic, logical and control units
depending upon our requirements. Various types of gates are described below.
[1] NOT Gate: This gate has one input and one output. This gate inverts input at the output.
When input is LOW output is HIGH and vice versa.
BOOLEAN EXPRESSION:
Y=
TRUTH TABLE:
A
LOGIC SYMBOL
Y
[2] AND Gate: This gate has two or more inputs and one output. Output of AND gate will go
HIGH when all inputs are HIGH, otherwise output will remain LOW.
BOOLEAN EXPRESSION:
Y=
TRUTH TABLE:
A
LOGIC SYMBOL
Y

Digital Electronics
[3] OR Gate: This gate has two or more inputs and one output. Output of OR gate will go
HIGH when
Any of the input is HIGH; output is LOW when all inputs are LOW.
BOOLEAN EXPRESSION:
Y=
TRUTH TABLE:
A
LOGIC SYMBOL
Y
[4] XOR Gate: This gate has two or more inputs and one output. Output will go HIGH when
all inputs are not of the same logic level (i.e. all inputs are not LOW or not HIGH at a time).
BOOLEAN EXPRESSION:
Y=
TRUTH TABLE:
A
LOGIC SYMBOL
Y
[5] NAND Gate: If we put one inverter at the output of AND logic gate will be NAND gate.
BOOLEAN EXPRESSION:
TRUTH TABLE:
A
Y=
LOGIC SYMBOL
[6] NOR Gate: If we put one inverter at the output of OR gate resulting logic gate will be not
NOR gate.
BOOLEAN EXPRESSION:
Y=

Digital Electronics
TRUTH TABLE:
A
LOGIC SYMBOL
Y
PROCEDURE:
[1] Select appropriate IC for each logic gate.
[2] Get the pin diagram from data book and make the connections according to the
requirements.
[3] Make sure the connections of Vcc and ground are at their respective pins.
[4] Switch on the power and apply sequence of inputs and observe outputs.
CONCLUSION:

Digital Electronics
Exp. No.: 2.
Date:
/ /20
Title
: Universal Gates
____________________________________________________________________________
AIM
: To prove NAND & NOR as Universal Gates.
EQUIPMENTS:
[1] Logic trainer
[2] IC7400
[3] IC7402,
THEORY:
We can realize basic & derived logic gate using only NAND & NOR gate. So, NAND and
NOR gates are known as universal gates.
NOT Using NAND & NOR GATE.
AND Using NAND & NOR GATE.

Digital Electronics
Ex-NOR
Using
NAND
& NOR
GATE.
OR Using
NAND
& NOR
GATE.
Ex-OR Using NAND & NOR GATE.

Digital Electronics
PROCEDURE:
[6] Get the pin diagram from data book and make the connections according to the
requirements.
[7] Make sure the connections of Vcc and ground are at their respective pins.
[8] Switch on the power and apply sequence of inputs and observe outputs.
CONCLUSION:

Digital Electronics
Answer the following question.

[1] "NAND and NOR gates are universal gates." Justify.
[2] What is TTL logic levels for HIGH and LOW states?
[3] What is positive logic and negative logic?
[4] Define term (a)Propagation Delay

(b)Fan In/Out
(c)Power dissipation

Digital Electronics
14
13
12
11
10
14
+ VCC
13
12
11
10
+ VCC
7408
7400
GND
GND
14
13
12
11
10
14
13
12
11
10
+ VCC
+VCC
7402
7432
GND
GND
14
13
12
11
10
14
13
12
11
10
+ VCC
+ VCC
7404
7486
GND
GND
FIG. : BASIC DIGITAL IC's

Digital Electronics
Roll No:
Date: / /20
Exp. No.: 3.
Title
: Binary Arithmetic Circuits.
____________________________________________________________________________
__
AIM : To realize binary half adder, full adder, half subtractor, and full subtractor.
EQUIPMENTS:
[1] Logic trainer
[2] IC 7408
[3] IC 7432
[4] IC 7486
THEORY:
Digital computers perform variety of information processing task. Among the basic functions
encountered are the various types of arithmetic operations. Here we will see how these
operations can be performed using digital hardware.
(1) Half adder: This adder adds only two bits and carry from the previous stage will not be
added. The outputs of the adder are SUM and CARRY. Truth table of half adder is given below.
TRUTH TABLE:
A
Expression for Sum and Carry Out:

S = A'B + AB' = A + B
and
Co
Co = AB
(2) Full adder: This adder adds two bits and carries from the previous stage. The outputs of the
adder are SUM and CARRY. Truth table and simplified expression for sum and carry are given
below.
TRUTH TABLE:
A
Ci
10
Co

Digital Electronics
EXPRESSION FOR SUM AND CARRY OUT:

S = A'B'Ci + A'BCi' + AB'Ci' + ABCi = A + B + C
and
Co = AB + BCi + ACi
(3) Half subtractor: This subtractor subtracts one bit from another but ignores any borrow
from the previous stage. The outputs of the half adder are DIFFERENCE and BORROW. Truth
table and expression for difference and borrow are given below.
TRUTH TABLE:
A
Bo
EXPRESSION FOR DIFFERENCE AND BORROW OUT:

D = AB + AB' = A + B
and
Bo = A'B
(4) Full subtractor: This subtractor subtracts binary digits along with borrow from the
previous stage. The outputs of the subtractor are difference and borrow out.
TRUTH TABLE:
A
Bi
Bo
EXPRESSION FOR DIFFERENCE AND BORROW OUT:

D = A'B'Bi + A'BBi' + AB'Bi' + ABBi = A + B + C
and
Bo = AB + A'Bi + BBi
PROCEDURE:
[1]
[2]
[3]
[4]
From the Boolean expression draw the logic diagram using suitable gates.
Select suitable ICs to implement the Boolean functions
Connect circuit and switch on the power supply.
Apply set of inputs and observe output and note down the logic state in table.
11

Digital Electronics
BINARY HALF ADDER
BINARY FULL ADDER
BINARY HALF SUBTRACTOR
BINARY FULL SUBTRACTOR
CONCLUSION:
Answer the following questions:
12

Digital Electronics
Conclusion:

[1] What is the difference between binary full adder and half adder?
[2] Develop logic to multiply two binary numbers.
[3] Develop logic to divide two binary numbers.
[4] Implement full adder using half adders.
13

Digital Electronics
Roll No:
Date: / /20
Exp. No.: 4.
Title
: Code Converter.
____________________________________________________________________________
__
AIM
: Design and realization of Binary to Gray code converter.
EQUIPMENTS:
[1] Logic trainer,
[2] LEDs,
[3] digital IC 7486,
THEORY:
Computers and other digital circuits are required to handle data which may be numeral,
alphabet or special character. Since digital circuit in binary fashion, the numerals, alphabets and
other special characters are required to be converted into binary format. There are various
possible ways of doing this which is called encoding. Some commonly used binary codes are
BCD, Excess-3, Gray, etc..
Many physical systems provide continuous data at their output. This data must be converted in
to digital form before they are applied to a digital system. Continuous analog information is
converted to digital form by means of analog to digital converter. Here it is useful to use the
reflected (or gray) code to represent digital data converted from analog data. The advantage of
reflected code over pure binary number is that the reflected code changes only by one bit as it
proceeds from one number to the next.
PROCEDURE:
[1] Write down the code conversion table. Simplify Boolean function for each bit using Kmap.
[2] Select appropriate ICs to realize the simplified Boolean function.
[3] Switch ON the power supply.
[4] Apply appropriate set of inputs and observe the output.
14

Digital Electronics
OBSERVATION:
DEC.
NO.
0.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
B3
BINARY
B2
B1
B0
CONCLUSION:
15
G3
GRAY
G2
G1
G0

Digital Electronics

[1] Why data need to be coded?
[2] What is weighted code?
[3] Give one examples of non weighted code.
[4] Design code converter ckt using mode control switch which performs both function Gray to
Binary and Binary to Gray.
[5] What is self complementary code? Give example and justify it.
16

Digital Electronics
Roll No:
Date: / /20
Exp. No.: 5.
Title
: Multiplexer.
____________________________________________________________________________
__
AIM : To realize Boolean function using multiplexer.
EQUIPMENTS:
[1] Trainer Board
[2] IC 74151
[3] IC 7404
THEORY:
Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines. Multiplexer is a combinational circuit that selects binary information from
one of the many input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. Normally for 2 n input lines whose bit
combinations determine the input line to be selected.
PROCEDURE:
[1] First write down the Boolean function of interest in minterm form.
[2] Design it using multiplexer of appropriate size.
[3] Connect the circuit.
[4] Observe the output levels and note down the logic level in table.
OBSERVATION:
Y (A, B, C, D) = (
MINTERMS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
)
B
17

Digital Electronics
FIG. : 4 - 1 CIRCUIT DIAGRAM OF MULTIPLEXER

CONCLUSION:
18

Digital Electronics

[1] List a practical system which uses multiplexes.
[2] Why multiplexer is needed?
[3] What is difference between decoder and demultiplexer?
[4] Develop a Full subtractor ckt using line Mux.
[5] "Multiplexer can be used to minimize hard ware and space Justify the statement.
19

Digital Electronics
Roll No:
Date: / /20
Exp. No.: 6.
Title
: Interfacing Of Display Devices.
____________________________________________________________________________
__
AIM
: To design BCD to seven segment decoder.
EQUIPMENTS:
[1] Logic trainer,
[2] IC 7447,
[3] seven segment LED display
THEORY:
In digital systems like computers, calculators seven segment displays are used, in which digits
are displayed, using LEDs. Display devices provide useful interface between human and digital
processing circuits. The digital circuit designed to perform particular task will contain set of
input and then input will generate output which depends upon the digital logic. This output is
however in the coded form which cannot be understood by unskilled user easily. If we decode
this output in form which can be understood easily by a layman then our circuit or product will
become more versatile and easy to use. For this purpose we can use decoder and its output is
given to display device through driver. Here in this experiment we will be using BCD to seven
segment decoder driver (7447) to convert BCD data to decimal equivalent number.
CODE TABLE:
A
INPUTS
B
C
OUTPUT BIT PATTERN

c
d
e
f
PROCEDURE:
[1] Connect the display circuit to the four input terminals.
[2] Apply logic 0 or logic 1 signal according to input bit pattern.
[3] Observe the output display of 0 to 9.
20
CODE
g

Digital Electronics
CONCLUSION:

[1] What is a decoder?
[2] Why we need driver along with decoder to interface LEDs?
[3] Give all steps of generating BCD to equivalent seven segment code.
[4] List name of some other display devices which are frequently used in daily life.
[5] What is LCD? How it differs from LEDs?
21

Digital Electronics
Roll No:
Date: / /20
Exp. No: 7.
Title : Flip-Flops.
____________________________________________________________________________
__
AIM
: To verify characteristic tables of RS, JK, D and T flip-flops.
EQUIPMENTS:
[1] Logic trainer Board,
[2] IC 7400,
[3] IC74112,
THEORY:
Logic circuits are classified into two groups namely combinational and sequential. a
combinational circuit consists of logic gates whose output at any time is determined directly
from the present combination of inputs without regard to previous inputs. Sequential circuits
involve timing and memory devices. The external inputs along with state of memory elements
determine the binary value at the output terminals of the sequential circuit. Thus a sequential
circuit is specified by a time sequence of inputs, outputs and internal states.
[1] R-S FLIP-FLOP: It has two inputs R (Reset) & S (Set). The two outputs are Q & Q'. The
two outputs are always complimentary. The truth table is as below.
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Q(t)
0
1
0
1
0
1
0
1
Q(t+1)
0
1
0
0
1
1
*
*
Q (t) = Present Output,

Q (t + 1) = Next output,
* = Invalid condition.
[2] J-K FLIP- FLOP: J-K flip-flop is refinement of the R-S flip-flop in that the indeterminate
state of R-S type is defined in the J-K flip-flop. Inputs J & K behave like S & R of R-S flipflop. When inputs are applied to both J & K simultaneously, the flip flop switches to its
complement state, i.e., if Q = 0 it switches to Q = 0, and vice versa. The truth table is as below.
22

Digital Electronics
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
Q(t)
0
1
0
1
0
1
0
1
Q(t+1)
0
1
0
0
1
1
1
0
[3] T FLIP- FLOP: The T flip-flop is single input version of the J-K flip flop. The T flip-flop
is obtained from J-K type if both the inputs are tied together. The designation T comes from the
ability of the flip-flop to toggle the current state. Regardless of the present state of the flip-flop,
it assumes the complement state when the clock pulse occurs while input T is at logic 1. The
truth table is as below.
T Q(t) Q(t+1)
0
0
0
0
1
1
1
0
1
1
1
0
[4] D FLIP-FLOP: D flip-flop transfers its input data to the output when clock will hit to the
flip flop. This flip-flop is use to latch data and hold it till next clock comes. It is used in
implementation of shift registers and counters. The truth table is as below.
D
0
0
1
1
Q(t)
0
1
0
1
Q(t+1)
0
0
1
1
PROCEDURE:
[2] Get the pin diagram from the data book and do the connections accordingly.
[3] Switch on the power supply.
[4] Verify the truth table.
CONCLUSION:
23

Digital Electronics

[1] What is the difference between combinational and sequential circuits?
[2] What is the need of the clock in sequential circuits?
[3] What is the difference between flip flop and latch?
[4] What is race around problem in the JK flip flops? What is the reason behind this problem?
[5] What is difference between event driven circuits and clocked driven circuits?
24

Digital Electronics
Roll No:
Date: / /20
Exp. No: 8.
Title : Synchronous Counter.
____________________________________________________________________________
__
AIM
: To design and realize modulo 10 binary synchronous counter using J-K flip-flops.
EQUIPMENTS:
[1] Logic trainer Board
[2] IC74112
[3] IC7432,
[4] IC7408
[5] IC7400
THEORY:
A sequential circuit that goes through a prescribed sequence of states on application of input
pulses is called a counter. The input pulses may be count pulses, may be clock pulses or they
may originate from an external source and may occur at prescribed intervals of time or at
random. In a counter, the sequence of states may follow a binary count or any other sequence
of states. Such counters are used for counting the number of occurrence of an event and are
useful for generating timing sequence to control operations in a digital system.
The number of distinct states through which counter passes before it starts its count sequence
again, is known as modulus of the counter. A counter that follows binary sequences called
binary counter. An N-bit binary counter consists of N-flip flops and can count from 0 to (2n 1). Mainly digital counters are of two types:
SYNCHRONOUS COUNTER: In this same clock pulse is applied to all the flip-flops.
RIPPLE COUNTER: In this type of counter clock pulse is applied only to the first flip-flop and
the ripples at the output of flip-flops serve as clock to the next flip-flops.
PROCEDURE:
[1] Select the desired value of N, i.e. modulo N-counter.
[2] Estimate minimum no. of JK flip-flops required to implement the counter.
[3] Draw the state diagram and state table.
[4] Derive input function expression for input of various flip-flops.
[5] Draw the logic diagram for the counter.
[6] Connect the circuit according to the logic diagram using various digital ICs.
[7] Switch on the power apply clock pulse, observe and note down the output sequence.
OBSERVATION:
N = _______
25

Digital Electronics
COUN
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q8
Q4
Q2
Q1
CONCLUSION:
26

Digital Electronics

[1] What are the applications of counters?
[2] What is synchronous counter?
[3] What is modulo of counter?
[4] How many JK flip flops are required to implement modulo 83 counters?
[5] What is difference between timer and counter?
27

Digital Electronics
Roll No:
Date: / /20
Exp. No: 9.
Title : Ripple Counter.
____________________________________________________________________________
__
AIM
: To design and realize modulo N ripple counter using T flip-flops.
EQUIPMENTS:
[1] Logic trainer Board,
[2] IC 74112
[3] IC7432,
[4] IC7408,
[5] IC7400,
THEORY:
Ripple counter is also known as divide by N counter or asynchronous counter. In this counter
same clock pulse is not applied to all flip-flops hence this counter is known as asynchronous
counter. Since ripples at the output of one flip-flop trigger the next flip-flop, it is known as
ripple counter. Every stage of this counter divides its input frequency by two in the output
hence is known as divide by N counter.
PROCEDURE:
[1] Select the desired value of N, i.e. modulo N-counter.
[2] Estimate minimum no. of JK flip-flops required to implement the counter.
[3] Draw the state diagram and state table.
[4] Derive Boolean function expression for CLR input of various flip-flops.
[5] Draw the logic diagram for the counter.
[6] Connect the circuit according to the logic diagram using various digital ICs.
[7] Switch on the power apply clock pulse, observe and note down the output sequence.
28

Digital Electronics
OBSERVATION:
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
N=
Q8
Q4
Q2
Q1
CONCLUSION:

[1] What is the difference between synchronous and ripple counter ?
[2] What is difference between Timer and Counter?
29

Digital Electronics
[3] How many JK flip-flops are required to implement modulo 5 counter?
[4] What are applications of counters?
[5] What is up counter and down counter?
[6] Find out the general equation for N-bit up/down counter and draw a circuit diagram which
will
perform both functions using selection line logic.
30

Digital Electronics
Roll No:
Date: / /20
Exp. No.: 10.
Title
: Shift Registers
____________________________________________________________________________
__
AIM
: To study universal shift register.
EQUIPMENTS:
[1] Logic trainer
[2] IC 74194
[3] Connecting wires
[4] CRO.
THEORY:
A flip flop can store one bit of datum. It is also referred as a 1-bit register. An array of flip flop
is required to store binary information and the number of flip flops required is equal to the
number of bits in the binary word and is referred as a register. Registers find applications in a
variety of digital systems including microprocessors.
A typical example of a shift register at work is found within a calculator. As we enter each digit
on the keypad, the number shifts to the left on the display. In other words, each cell is a
temporary memory and thus holds the number on the display even after the release of the key.
It also shifts the number to the left each time a next key is pressed. This memory and shifting
characteristic make the shift register extremely valuable in most digital electronic systems. We
can classify the registers according to the way data they take from and the data they deliver to
the external circuits.
[1] Serial in serial out registers: Here data is taken serially one bit at a time and data is placed
serially on the external line.
[2] Serial in parallel out registers: In this type of registers the data is accepted serially and data
is placed simultaneously on the external bus.
[3] Parallel in serial out registers: The data is loaded simultaneously and data is taken from the
register one by one bit at time.
[4] Parallel in parallel out registers: The data is loaded simultaneously and is taken out
simultaneously from the shift register.
Registers can be further classified according to the data shifting direction; they may be shift left
registers or shift right registers.
31

Digital Electronics
UNIVERSAL SHIFT REGISTER (IC 74194):

This bi-directional shift register is designed to incorporate virtually all of the features a system
designer may want. It has four distinct modes of operation, namely
(1) Parallel load
(2) Shift right
(3) Shift left
(4) Inhibit clock (do nothing).
MODE CONFIGURATION TABLE:
S1
0
0
1
1
S0
0
1
0
1
MODE
PROCEDURE:
[1] Select appropriate for the shift register.
[2] Connect 0 & +5 volt D.C. supply to the IC.
Select particular mode with proper logic level at S1 and S0.
[3] Apply clock pulse and sequence of input bits and observe the output sequence.
[4] Prepare the timing diagram and operation table for all possible modes.
CONCLUSION:
32

Digital Electronics

[1] Give few examples of practical systems which use shift registers.
[2] "Shift register can be used to provide timing delay." Justify the statement.
[3] "Shift registers can be used as a memory." Justify the statement.
[4] What do you mean by universal shift register?
[5] Why we need serial to parallel and parallel to serial conversion?
[6] Can one use shift register as time delay device? If yes how?
33

Digital Electronics
Roll No:
Date: / /20
Exp. No.: 11.
Title
: Arithmetic Logic Unit
___________________________________________________________________________
AIM: Perform an experiment, which demonstrates function of 4 bit or 8-bit ALU.
EQUIPMENTS:
[1] Logic trainer
[2] IC 74181
[3] Connecting wires
[4] CRO.
THEORY:
The Arithmetic Logic Unit (ALU) is the kernel block of a central processing unit (CPU).
The ALU can perform various arithmetic operations such as parallel addition and
subtraction. You have already learned the adder structure. The adder introduced is a one-bit
adder. However, data to be handled and processed in the ALU are often represented by
several bits (usually the width of a CPU word). Therefore the ALU is normally required to
have the ability to perform parallel addition and subtraction, so that addition and
subtraction of several bits can be performed simultaneously. Apart from speed, the ALU is
also required to have flexibility. The function of the ALU can be controlled or programmed
to carry out different arithmetic functions.
The ALU device used in this experiment is 74181 and its pin assignment is shown in Fig.
1. 74181 consists of four parallel full adder/subtractor circuits. Data applied on the inputs
Ais and Bis are processed and the sum or difference is available at the output in a parallel
format. Selection of the desired ALU function is controlled by five control lines, S0S3,
and mode, M.
The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the
four Function Select inputs (S0S3) and the Mode Control input (M), it can perform all the
16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active
LOW operands. The Function Table lists these operations. When the Mode Control input
(M) is HIGH, all internal carries are inhibited and the device performs logic operations on
the individual bits as listed. When the Mode Control input is LOW, the carries are enabled
and the device performs arithmetic operations on the two 4-bit words.
The A = B output from the device goes HIGH when all four F outputs are HIGH and can be
used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The
A = B output is open collector and can be wired AND with other A = B outputs to give a
comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal
to indicate A > B and A < B.
The Function Table lists the arithmetic operations that are performed without a carry in. An
incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B
minus 1 (2s complement notation) without a carry in and generates A minus B when a carry
is applied. Because subtraction is actually performed by complementary addition (1s
34

Digital Electronics
complement), a carry out means borrow; thus a carry is generated when there is no
underflow and no carry is generated when there is underflow. As indicated,
this device can be used with either active LOW inputs producing active LOW outputs or
with active HIGH inputs producing active HIGH outputs. For either case the table lists the
operations that are performed to the operands labelled inside the logic symbol.
Fig. 1. 74181 4-bit ALU
35

Digital Electronics
Experiment: Parallel Adder

Connect A0-A2, and B0-B2 to six switches. Connect A3 and B3 to the ground and F0-F3 to
four LEDs. The select lines S0-S3, mode M, and carry-in signal CN, are set to the addition
function. Note that A0 and B0 are the LSBs of the input data, and A3 and B3 are the MSBs
of the input data. F0 and F3 are respectively the LSB and MSB of the output data. Now
perform the addition function of 74181 by setting the input switches to the appropriate
values as shown in Table 1. Record the output data from the LEDs (when an LED lights
up, it indicates the output is logic high) and verify the outcomes.
36

Digital Electronics
Table1.Inputsforaddition,F=A+B
A2
A1
A0
B2
B1
B0
Conclusion:
37
F3
F2
F1
F0

Digital Manual

Загружено:

Сведения о документе

Исходное описание:

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Digital Manual

Загружено:

Авторское право:

Доступные форматы

Shankersinh Vaghela Bapu Institute Of Technology.

SHANKERSINH VAGHELA BAPU INSTITUTE OF

SHANKERSINH VAGHELA BAPU INSTITUTE OF

Shankersinh Vaghela Bapu Institute Of Technology.

Gandhinagar District, Gujarat,

Verify truth table of all logic gates.

Prove NAND & NOR as Universal Gates.

Realization of half and full adder and half &

Design and realization of binary to gray code

Study of multiplexer and realization of

To design binary to seven segments LED

Verification of truth tables of RS, D, JK and

To design and realize modulo N Synchronous

To design and realize modulo N Ripple

Shankersinh Vaghela Bapu Institute Of Technology.

To realize shift register.

Shankersinh Vaghela Bapu Institute Of Technology.

Shankersinh Vaghela Bapu Institute Of Technology.

Shankersinh Vaghela Bapu Institute Of Technology.

: To prove NAND & NOR as Universal Gates.

AND Using NAND & NOR GATE.

Shankersinh Vaghela Bapu Institute Of Technology.

Ex-OR Using NAND & NOR GATE.

Shankersinh Vaghela Bapu Institute Of Technology.

Shankersinh Vaghela Bapu Institute Of Technology.

Answer the following question.

[3] What is positive logic and negative logic?

[4] Define term (a)Propagation Delay

Shankersinh Vaghela Bapu Institute Of Technology.

FIG. : BASIC DIGITAL IC's

Shankersinh Vaghela Bapu Institute Of Technology.

Expression for Sum and Carry Out:

Shankersinh Vaghela Bapu Institute Of Technology.

EXPRESSION FOR SUM AND CARRY OUT:

EXPRESSION FOR DIFFERENCE AND BORROW OUT:

EXPRESSION FOR DIFFERENCE AND BORROW OUT:

Shankersinh Vaghela Bapu Institute Of Technology.

BINARY HALF ADDER

BINARY FULL ADDER

BINARY HALF SUBTRACTOR

BINARY FULL SUBTRACTOR

Shankersinh Vaghela Bapu Institute Of Technology.

Answer the following question.

[2] Develop logic to multiply two binary numbers.

[3] Develop logic to divide two binary numbers.

[4] Implement full adder using half adders.

Shankersinh Vaghela Bapu Institute Of Technology.

: Design and realization of Binary to Gray code converter.

Shankersinh Vaghela Bapu Institute Of Technology.

Shankersinh Vaghela Bapu Institute Of Technology.

Answer the following question.

[2] What is weighted code?

[3] Give one examples of non weighted code.

Shankersinh Vaghela Bapu Institute Of Technology.

Shankersinh Vaghela Bapu Institute Of Technology.

FIG. : 4 - 1 CIRCUIT DIAGRAM OF MULTIPLEXER

Shankersinh Vaghela Bapu Institute Of Technology.

Answer the following questions:

[2] Why multiplexer is needed?

[3] What is difference between decoder and demultiplexer?

[4] Develop a Full subtractor ckt using line Mux.

Shankersinh Vaghela Bapu Institute Of Technology.

: To design BCD to seven segment decoder.