EXPERIMENT NO.

3
Aim: To implement D-Flipflop using static and dynamic latches and calculate setup time, hold time,
clock -to-Q delay and data to-Q delay.
1. Transmission Gate based Static Master-Slave D-Flipflop
2. Dynamic Transmission Gate Edge Triggered D-Flipflop
3. 2 D-Flipflop
4. True Single Phase Clocked (TSPC) D-Fliplfop
Theory:
Timing Metrics for D-Flipflop

There are three important timing parameters associated with a register as illustrated in above
figure. The set-up time ( ) is the time that the data inputs (D input) must be valid before the clock
transition (this is, the 0 to 1 transition for a positive edge-triggered register). The hold time ( ) is the
time the data input must remain valid after the clock edge. Assuming that the set-up and hold-times are
met, the data at the D input is copied to the Q output after a worst-case propagation delay (with reference
to the clock edge) denoted by
1. Transmission Gate based Static Master-Slave D-Flipflop

Above figure shows reduced clock load static master-slave D-FF. The transmission gate (1 ) and its
source driver must overpower the feedback inverter (2 ) to switch the state of the cross-coupled inverter.
The sizing requirements for the transmission gates can be derived using a similar analysis as performed
for the SR flip-flop. The input to the inverter 1 must be brought below its switching threshold in order to
make a transition. If minimum-sized devices are to be used in the transmission gates, it is essential that
the transistors of inverter I2 should be made even weaker. This can be accomplished by making their
channel-lengths larger than minimum. Using minimum or close-to minimum size devices in the
transmission gates is desirable to reduce the power dissipation in the latches and the clock distribution
network. Problem with this scheme is the reverse conduction this is, the second stage can affect the
state of the first latch. When the slave stage is on, it is possible for the combination of 2 and 4 to
influence the data stored in 1 2 latch. As long as 4 is a weak device, this is fortunately not a major
problem. Another problem is the clock skew which may cause failure.

Schematic Diagram:

VDD

VDD

VDD
VDD
M2

M4

CLKBAR

CLK

M1

M7

VDD

M6

Data

VDD

M0

gnd

M10

M8

gnd

CLK

gnd

CLKBAR

gnd
VDD

CLK

gnd

VDD
CLK

VDD

val0=1.8
val1=0

M13

gnd

M3
CLK

M5

CLKBAR
Data

M12

val0=1.8
val1=0

M9

M11

gnd

gnd
gnd

Simulation Results:

Data

gnd

1.8
1.6
1.4
1.2
V

1
0.8
0.6

CLK

0.4
SEL>>
-0.1
1.8
1.6
1.4
1.2
V

1
0.8

Data

0.6
0.4
0.2
0
1.8
1.6
1.4
1.2

1
0.8
Q

0.6
0.4
0.2
0
12n

15n

18n

21n

24n

A1:(15.50000ns, 900.00000mV); A2:(14.85940ns, 900.00000mV); dif:(640.60000ps, -2.55351fV)

time, s

27n

30n

33n

36n

39n

40n

The D-input edge is skewed relative to the clock signal until the output Q stops following D-input.
For a skew of 640.6 ps, the incorrect value of input D is sampled and an incorrect value propagates
to the output Q .
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4

CLK

SEL>>
-0.1
1.8
1.6
1.4

1.2

Data

1
0.8
0.6
0.4
0.2
0
1.8
1.6
1.4

1.2
1
0.8
Q

0.6
0.4
0.2
0
12n

15n

18n

21n

24n

A1:(15.50000ns, 900.00000mV); A2:(14.85930ns, 900.00000mV); dif:(640.70000ps, -1.22125fV)

time, s

27n

30n

33n

For a skew of 640.7 ps, output Q follows D-input.

= 40.

36n

39n

40n

1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4

CLK

SEL>>
-0.1
1.8
1.6
1.4
1.2

1
0.8
0.6
0.4
0.2

Data

0
1.8
1.6
1.4
1.2

1
0.8
0.6
0.4
0.2
0

12n

15n

18n

21n

24n

A1:(15.96080ns, 900.00000mV); A2:(15.50000ns, 900.00000mV); dif:(460.80000ps, 3.88578fV)

27n
time, s

30n

33n

36n

39n

40n

After the D-input is set for correct setup time, the transaction edge on D-input is skewed relative to
the clock signal until the circuit gives incorrect output.
For a skew of 460.8 ps, the incorrect value of input D is sampled and an incorrect value propagates
to the output Q.
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
SEL>>

CLK

-0.1
1.8
1.6
1.4

1.2
1
0.8
0.6
0.4
0.2
Data

0
1.8
1.6
1.4

1.2
1
0.8
0.6
0.4
0.2
Q

0
12n

15n

18n

21n

24n

A1:(15.96090ns, 900.00000mV); A2:(15.50000ns, 900.00000mV); dif:(460.90000ps, 0.00000V)

27n
time, s

For a skew of 460.9 ps, output Q follows D-input.

= .

30n

33n

36n

39n

40n

Date/Time Run: 4/3/2016 8:31:09 AM

1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
SEL>>
-0.1

CLK
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0

Data
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0
12n

14n

16n

18n

20n

22n

24n

26n

28n

Q
time, s
A1:(15.77636ns, 900.00000mV); A2:(15.50000ns, 900.00000mV); dif:(276.36484ps, 0.00000V)
SymSpice

Clock-to-Q delay
= .

Date/Time Run: 4/3/2016 8:31:09 AM

1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
SEL>>
-0.1

CLK
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0

Data
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0
12n

14n

16n

18n

20n

Q
time, s
A1:(15.77636ns, 900.00000mV); A2:(14.85930ns, 900.00000mV); dif:(917.06484ps, 0.00000V)
SymSpice

22n

24n

Data-to-Q delay
= .

26n

28n