CML-SerDes

Presented By:Mohit Singh Choudhary

M.Tech. Communication and Signal Processing
Discipline of Electrical Engineering
IIT Indore
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Guided By:Dr. Santosh Kumar Vishvakarma

Assistant Professor,
Discipline of Electrical Engineering
IIT Indore

Contents
Motivation
Introduction

Literature Review
Implementation
Application
Future Work
References
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Motivation
Parallel Interconnections

Large I/O Pins

More Power consumed
Problem in meeting timing requirement
On Chip-area is more

Sender

Receiver

David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer
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Motivation
Large Distance Transmission
Infeasible to transmit parallel data to a large distance.

David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer
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Introduction
SerDes ( Serializer and Deserializer)
Multiplexing bit data to bit of interconnect and at receiver demultiplexing bit of
interconnect to bit data(< ).

Serializer

Deserializer

David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer
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Introduction
Types of SerDes on the basis of design techniques.

SerDes

IIT-Indore | EE 799 | M.Tech. Project Stage 1

Introduction
Serialization
Serializer uses mux to convert parallel data into serial output.
1
5
3
7

6
4

/4

/2

Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip networking," in Circuits and Systems
(ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Introduction
Deserialization
Deserializer uses DFF to deserialize input bits.

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

IIT-Indore | EE 799 | M.Tech. Project Stage 1

Introduction
CML (Current Mode Logic)
Current mode logic provides true differential operation, low noise level and noise
immunity with low dynamic power dissipation.

1
1.2

1
0

1.2
0.7

2
2

0
= 0 ,

Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference
(SOCC), 2014 27th IEEE International, pp.5-10, 2-5 Sept. 2014
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Literature Review
1

"1"

DETFF

"0"

DETFF
3

DETFF
7

DETFF

VDD

DETFF
6

DETFF

VDD/2

DETFF
8

0
/4

/2

1. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip networking," in Circuits

and Systems (ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011.
2. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-timed SerDes transceiver for multi-core communication,"
in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012
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Literature Review

a). Serializer b). Deserializer

11

Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference
(SOCC), 2014 27th IEEE International, pp.5-10, 2-5 Sept. 2014
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Literature Review

Serializer Architecture

12

Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer," in Micro-Nanoelectronics, Technology and Applications, 2009. EAMTA 2009.
Argentine School of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Implementation
Serializer

We have implemented serializer using CML.

Input CMOS data is converted into CML.
Then CML mux is used to serialize data.
CML serialized output is converted back into CMOS for transmission.

0
CMOS to CML

13

MUX

CML to CMOS

Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference
(SOCC), 2014 27th IEEE International, pp.5-10, 2-5 Sept. 2014
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Implementation
Serializer
Serializer is implemented in 65nm UMC CMOS technology.

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IIT-Indore | EE 799 | M.Tech. Project Stage 1

Implementation
Serializer
Serialization we got at 16.64Gbps speed.

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Implementation
Deserializer
At the receiver deserialization is done using two parallel chain of DFF.
Half clock is used and bits are shifted at both edges
8

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

/2

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Implementation
Deserializer
Deserializer we have implemented with the help of CML DFF which is build using CML
latch.

0
CML Latch

17

Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference
(SOCC), 2014 27th IEEE International, pp.5-10, 2-5 Sept. 2014
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Implementation
Deserializer
Deserializer is implemented in 65nm UMC CMOS technology.

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IIT-Indore | EE 799 | M.Tech. Project Stage 1

Implementation
Results

PVT Corners of various SerDes techniques

()
()

1.08

125

11.49 /

15.36 /

1.2

27

12.67 /

16.64 /

ff

1.32

45

13.75 /

16.96 /

Comparison of various SerDes techniques

19

()

()

[4]

65

16

18.1

[2]

65

12.67

14.3

CMOS CML[5]

45/65

10

50/106

65

16.64

9.29

Submitted: Mohit Singh Choudhary, Mahesh Kumawat, Pramod Kumar Bharti and Dr. S. K. Vishvakarna, Power Optimized High Speed Synchronous
CML SerDes Transceiver Design with Process Corner Variation IET Electronics Letter
IIT-Indore | EE 799 | M.Tech. Project Stage 1

Application
Application

Telecom wireless communication

In video transmission (FlatLink)
Transceiver Devices
Telecom Switching Applications
8b/10b SerDes are used in Ethernet, Fiber optics, InfiniBand

Dave Lewis, SerDes Architectures and Application, National Semiconductor Corporation

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Future work
Dynamic CML
Reduced swing logic style that reduces both gate and interconnect power dissipation.
DyCML circuits combines the advantages of CML with those of dynamic logic families to
achieve high performance at a low-voltage with low-power dissipation.

Asynchronous Circuits
Asynchronous circuits since does not require clock thus saves lot of power consumed in
oscillators and CDR.

Encoding
Serial data can be encoded to 3-level, 8b/10b etc so that speed can be increased.

1 . Allam, M.W.; Elmasry, M.I., "Dynamic current mode logic (DyCML): a new low-power high-performance logic style," in Solid-State Circuits,IEEE
Journal of , vol.36, no.3, pp.550-558, Mar 2001.
2. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes," in System-on-Chip
Conference (SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014.
3. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-timed SerDes transceiver for multi-core communication,"
in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012.
21

IIT-Indore | EE 799 | M.Tech. Project Stage 1

References
References
[1]. David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition.
Springer
[2]. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip
asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference (SOCC), 2014
27th IEEE International , pp.5-10, 2-5 Sept. 2014
[3]. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power
SerDes transceiver for on-chip networking," in Circuits and Systems (ISCAS), 2011 IEEE
International Symposium on , pp.1419-1422, 15-18 May 2011
[4]. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power selftimed SerDes transceiver for multi-core communication," in Circuits and Systems (ISCAS),
2012 IEEE International Symposium on, pp.1660-1663, 20-23 May 2012
[5]. Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer," in MicroNanoelectronics, Technology and Applications, 2009. EAMTA 2009. Argentine School
of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009

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IIT-Indore | EE 799 | M.Tech. Project Stage 1

Thanks