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1. General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
3. Ordering information
Table 1.
Ordering information
Type number
74HC74D
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO14
SOT108-1
40 C to +125 C
SSOP14
SOT337-1
74HCT74D
74HC74DB
74HCT74DB
74HC74; 74HCT74
NXP Semiconductors
Table 1.
Type number
74HC74PW
Package
Temperature range
Name
Description
Version
40 C to +125 C
TSSOP14
SOT402-1
40 C to +125 C
DHVQFN14
74HCT74PW
74HC74BQ
74HCT74BQ
4. Functional diagram
6'
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&3
6'
4
'
6' 6'
6'
'
'
'
&3
&3
&3
4
4
4
))
4
5'
4
4
5' 5'
Fig 1.
Logic symbol
Fig 2.
&
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5'
6'
5
&
'
&3
6'
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4
&3
))
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4
5'
5
Fig 3.
5'
PQD
Functional diagram
&
&
4
5'
PQD
PQD
&3
))
4
&
&
&
&
'
4
&
&
5'
6'
&3
PQD
&
&
Fig 4.
74HC_HCT74
2 of 20
74HC74; 74HCT74
NXP Semiconductors
5. Pinning information
5.1 Pinning
5'
WHUPLQDO
LQGH[DUHD
+&
+&7
&3
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6'
&3
4
6'
4
4
*1'
4
5'
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6'
&3
4
4
*1'
6'
'
&3
'
9&&
5'
4
*1'
5'
9&&
+&
+&7
4
DDD
7UDQVSDUHQWWRSYLHZ
DDD
Fig 5.
Fig 6.
Pin description
Symbol
Pin
Description
1RD
1D
data input
1CP
1SD
1Q
output
1Q
complement output
GND
ground (0 V)
2Q
complement output
2Q
output
2SD
10
2CP
11
2D
12
data input
2RD
13
VCC
14
supply voltage
74HC_HCT74
3 of 20
74HC74; 74HCT74
NXP Semiconductors
6. Functional description
Table 3.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQ
nQ
[1]
Table 4.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQn+1
nQn+1
[1]
H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = dont care.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
0.5
+7
IIK
20
mA
IOK
20
mA
IO
output current
25
mA
ICC
supply current
+100
mA
IGND
ground current
100
mA
Tstg
storage temperature
65
+150
500
mW
Ptot
[1]
Conditions
Min
[1]
Max
Unit
74HC_HCT74
4 of 20
74HC74; 74HCT74
NXP Semiconductors
Conditions
74HC74
Min
Typ
74HCT74
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
VI
input voltage
VCC
VCC
VO
output voltage
VCC
VCC
Tamb
ambient temperature
40
+25
+125
40
+25
+125
t/V
VCC = 2.0 V
625
ns/V
VCC = 4.5 V
1.67
139
1.67
139
ns/V
VCC = 6.0 V
83
ns/V
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VCC = 2.0 V
1.5
1.2
1.5
VCC = 4.5 V
3.15
2.4
3.15
VCC = 6.0 V
4.2
3.2
4.2
VCC = 2.0 V
0.8
0.5
0.5
VCC = 4.5 V
2.1
1.35
1.35
VCC = 6.0 V
2.8
1.8
1.8
3.84
4.32
3.7
5.34
5.81
5.2
0.15
0.33
0.4
0.16
0.33
0.4
74HC74
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
1.0
1.0
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
40
80
CI
input
capacitance
3.5
pF
74HC_HCT74
5 of 20
74HC74; 74HCT74
NXP Semiconductors
Table 7.
Static characteristics continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
Tamb = 40 C to +125 C
Min
Typ[1]
Max
Min
Max
Unit
74HCT74
VIH
HIGH-level
input voltage
2.0
1.6
2.0
VIL
LOW-level
input voltage
1.2
0.8
0.8
VOH
HIGH-level
output voltage
4.32
3.7
LOW-level
output voltage
0.15
0.33
0.4
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
1.0
1.0
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
40
80
ICC
additional
supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; nD, nRD
inputs
70
315
343
80
360
392
3.5
pF
VOL
input
capacitance
CI
[1]
IO = 4 mA
74HC_HCT74
6 of 20
74HC74; 74HCT74
NXP Semiconductors
Tamb = 40 C to +85 C
Conditions
Min
Typ[1]
Max
Min
Max
47
220
265
ns
74HC74
tpd
propagation
delay
[2]
VCC = 2.0 V
VCC = 4.5 V
17
44
53
ns
VCC = 5 V; CL = 15 pF
14
ns
14
37
45
ns
VCC = 2.0 V
50
250
300
ns
VCC = 4.5 V
18
50
60
ns
VCC = 5 V; CL = 15 pF
15
ns
14
43
51
ns
52
250
300
ns
VCC = 6.0 V
nSD to nQ, nQ; see
Figure 8
[2]
VCC = 6.0 V
nRD to nQ, nQ; see
Figure 8
[2]
VCC = 2.0 V
VCC = 4.5 V
19
50
60
ns
VCC = 5 V; CL = 15 pF
16
ns
15
43
51
ns
VCC = 6.0 V
tt
tW
transition
time
pulse width
[3]
VCC = 2.0 V
19
95
110
ns
VCC = 4.5 V
19
22
ns
VCC = 6.0 V
16
19
ns
VCC = 2.0 V
100
19
120
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
VCC = 2.0 V
100
19
120
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
VCC = 2.0 V
40
45
ns
VCC = 4.5 V
ns
VCC = 6.0 V
ns
trec
recovery
time
74HC_HCT74
7 of 20
74HC74; 74HCT74
NXP Semiconductors
Table 8.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter
tsu
th
fmax
set-up time
hold time
maximum
frequency
Tamb = 40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
ns
VCC = 4.5 V
ns
VCC = 6.0 V
ns
VCC = 2.0 V
4.8
23
4.0
MHz
VCC = 4.5 V
24
69
20
MHz
76
MHz
28
82
24
MHz
24
pF
18
44
53
ns
15
ns
23
50
60
ns
18
ns
24
50
60
ns
18
ns
19
22
ns
23
27
ns
20
24
ns
ns
15
18
ns
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
CPD
Typ[1]
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[4]
propagation
delay
[2]
74HCT74
tpd
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
nSD to nQ, nQ; see
Figure 8
[2]
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
nRD to nQ, nQ; see
Figure 8
[2]
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
tt
tW
transition
time
pulse width
VCC = 4.5 V
VCC = 4.5 V
[3]
recovery
time
set-up time
VCC = 4.5 V
VCC = 4.5 V
74HC_HCT74
8 of 20
74HC74; 74HCT74
NXP Semiconductors
Table 8.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
th
hold time
fmax
maximum
frequency
VCC = 4.5 V
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
power
dissipation
capacitance
CPD
[4]
CL = 50 pF; f = 1 MHz;
VI = GND to VCC - 1.5 V
[1]
[2]
Min
Typ[1]
Max
Min
Max
ns
22
54
18
MHz
59
MHz
29
pF
[3]
[4]
74HC_HCT74
9 of 20
74HC74; 74HCT74
NXP Semiconductors
11. Waveforms
9,
Q'LQSXW
90
*1'
WK
WK
WVX
WVX
IPD[
9,
Q&3LQSXW
90
*1'
W:
W3+/
W3/+
92+
90
Q4RXWSXW
92/
W3/+
W3+/
92+
Q4RXWSXW
90
92/
W7/+
W7+/
DDD
Fig 7.
Input to output propagation delay, output transition time, clock input pulse width and maximum
frequency
74HC_HCT74
10 of 20
74HC74; 74HCT74
NXP Semiconductors
9,
90
Q&3LQSXW
*1'
W UHF
9,
90
Q6'LQSXW
*1'
W:
W:
9,
90
Q5'LQSXW
*1'
W 3/+
W 3+/
92+
Q4RXWSXW
90
92/
92+
90
Q4RXWSXW
92/
W 3+/
W 3/+
PQD
Fig 8.
Table 9.
Set and reset propogation delays, pulse widths and recovery time
Measurement points
Type
Input
Output
VM
VM
74HC74
0.5VCC
0.5VCC
74HCT74
1.3 V
1.3 V
74HC_HCT74
11 of 20
74HC74; 74HCT74
NXP Semiconductors
W:
9,
QHJDWLYH
SXOVH
90
90
*1'
WI
9,
WI
SRVLWLYH
SXOVH
*1'
WU
WU
90
90
W:
9&&
*
9,
92
'87
57
&/
DDK
Fig 9.
Table 10.
Type
Input
VI
tr, tf
CL
RL
74HC74
VCC
6 ns
15 pF, 50 pF
1 k
tPLH, tPHL
74HCT74
3V
6 ns
15 pF, 50 pF
1 k
tPLH, tPHL
74HC_HCT74
Load
Test
12 of 20
74HC74; 74HCT74
NXP Semiconductors
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NXP Semiconductors
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NXP Semiconductors
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74HC74; 74HCT74
NXP Semiconductors
13. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
ESD
ElectroStatic Discharge
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
Change notice
Supersedes
74HC_HCT74 v.5
20151203
74HC_HCT74 v.4
Modifications:
74HC_HCT74 v.4
Modifications:
20120827
74HC_HCT74 v.3
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT74 v.3
20030710
74HC_HCT74_CNV v.2
74HC_HCT74_CNV v.2
19980223
Product specification
74HC_HCT74
17 of 20
74HC74; 74HCT74
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT74
18 of 20
74HC74; 74HCT74
NXP Semiconductors
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74HC_HCT74
19 of 20
74HC74; 74HCT74
NXP Semiconductors
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.