LG P970 Optimus Black Service Manual - en

Internal Use Only
Service Manual
LG-P970
Date: April, 2011 / Issue 1.0
Table Of Contents
1. INTRODUCTION 3
1.1 Purpose3
1.2 Regulatory Information3
1.3 Abbreviations5
2. PERFORMANCE 7
2.1 Product Name7
2.2 Supporting Standard7
2.3 Main Parts : GSM Solution7
2.4 HW Features8
2.5 SW Features 10
2.6 HW SPEC. 14
3. TECHNICAL BRIEF 25
3.1 GENERAL DESCRIPTION 25
3.2 GSM MODE 28
3.3 UMTS MODE 31
3.4 GPS RECEIVER 33
3.5 LO GENERATION and DISTRIBUTION CIRCUIT 37
3.6 OFF-CHIP RF COMPONENTS 39
3.7 Digital Baseband(DBB/MSM7227) 44
3.8 Hardware Architecture 46
3.9 Subsystem (MSM7227) 48
3.10 Power Block 59
3.11 External memory interface 65
3.12 H/W Sub System 66
3.13 Audio and sound 82
3.14 Display 89
3.14 Main (5M pixels) & Sub (2M pixels) Camera 93
3.16 Vibrator 96
3.17 Compass Sensor 97
3.18 Motion Sensor 98
3.19 Gyro Sensor 99
3.20 Proximity Sensor100
3.21 Illumination Sensor101
3.22 Touch Module102
3.23 Main Features103
4. TROUBLE SHOOTING 106
4.1 RF Component106
4.2 SIGNAL PATH107
4.3 Checking TCXO Block109
4.4 Checking GSM TX Module(GSM PAM + FEM) Block111
LGE Internal Use Only
4.5 Checking WCDMA Block114

4.6 Checking GSM Block125
4.7 GPS/WIFI/BT RF components133
4.8 GPS/WIFI/BT SIGNAL PATH135
4.9 Power ON troubleshooting137
4.10 Charger Troubleshooting140
4.11 USB Trouble shooting143
4.12 Audio trouble147
4.13 Camera troubleshooting158
4.14 Main LCD trouble161
4.15 SIM detect Trouble shooting164
4.16 Side Key Trouble shooting168
4.17 Vibrator Troubleshooting170
4.18 Motion sensor troubleshooting173
4.19 Gyro/Compass sensor troubleshooting175
4.20 Proximity Sensor on/off trouble178
4.21 Illumination Sensor on/off trouble180
4.22 Touch trouble182
5. DOWNLOAD 184
6. BLOCK DIAGRAM 203
7. CIRCUIT DIAGRAM 206
8. BGA Pin Map 219
9. PCB LAYOUT 224
10. CALIBRATION 234
10.1 General Description234
10.2 Requirement234
10.3 Setup for RF calibration235
10.4 Tachyon Software Installation235
10.5 Tachyon Start236
10.6 Overview of RF Calibration240
11. HIDDEN MENU 245
12. EXPLODED VIEW & REPLACEMENT PART LIST 253
12.1 EXPLODED VIEW253
12.2 Replacement Parts254
12.3 Accessory295
--
Copyright 2011 LG Electronics. Inc. All right reserved.

Only for training and service purposes
1. INTRODUCTION
1.
INTRODUCTION
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the features of
this model.
1.2 Regulatory Information

A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons
other than your companys employees, agents, subcontractors, or person working on your companys behalf)
can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud associated with
your telecommunications system. System users are responsible for programming and configuring the
equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from
the above case but will prevent unauthorized use of common carrier telecommunication service of facilities
accessed through or connected to it. The manufacturer will not be responsible for any charges that result from
such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly causing
harm or interruption in service to the telephone network, it should disconnect telephone service until repair can
be done. A telephone company may temporarily disconnect service as long as repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these changes
could reasonably be expected to affect the use of the phones or compatibility with the net work, the telephone
company is required to give advanced written notice to the user, allowing the user to take appropriate steps to
maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent.
The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note
that unauthorized alternations or repair may affect the regulatory status of the system and may void any
remaining warranty.
--

1. INTRODUCTION
E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory
agencies. In accordance with these agencies, you may be required to provide information such as the following
to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.
G. Interference and Attenuation
A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the
sign.
Following information is ESD handling:

Service personnel should ground themselves by using a wrist strap when exchange system boards. When
repairs are made to a system board, they should spread the floor with anti-static mat which is also grounded.
Use a suitable, grounded soldering iron. Keep sensitive parts in these protective packages until these are used.
When returning system boards or parts like EEPROM to the factory, use the protective package as described.
--

1. INTRODUCTION
1. INTRODUCTION
1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC
Automatic Power Control
BB
Baseband
BER
Bit Error Ratio
CC-CV
Constant Current Constant Voltage
DAC
Digital to Analog Converter
DCS
Digital Communication System
dBm
dB relative to 1 milli watt
DSP
Digital Signal Processing
EEPROM
Electrical Erasable Programmable Read-Only Memory
ESD
Electrostatic Discharge
FPCB
Flexible Printed Circuit Board
GMSK
Gaussian Minimum Shift Keying
GPIB
General Purpose Interface Bus
GSM
Global System for Mobile Communications
IPUI
International Portable User Identity
IF
Intermediate Frequency
LCD
Liquid Crystal Display
LDO
Low Drop Output
LED
Light Emitting Diode
OPLL
Offset Phase Locked Loop
6/140
--

1. INTRODUCTION
1. INTRODUCTION
PAM
Power Amplifier Module
PCB
Printed Circuit Board
PGA
Programmable Gain Amplifier
PLL
Phase Locked Loop
PSTN
Public Switched Telephone Network
RF
Radio Frequency
RLR
Receiving Loudness Rating
RMS
Root Mean Square
RTC
Real Time Clock
SAW
Surface Acoustic Wave
SIM
Subscriber Identity Module
SLR
Sending Loudness Rating
SRAM
Static Random Access Memory
PSRAM
Pseudo SRAM
STMR
Side Tone Masking Rating
TA
Travel Adapter
TDD
Time Division Duplex
TDMA
Time Division Multiple Access
UART
Universal Asynchronous Receiver/Transmitter
VCO
Voltage Controlled Oscillator
VCTCXO
Voltage Control Temperature Compensated Crystal Oscillator
WAP
Wireless Application Protocol
7/140
--

2. PERFORMANCE
2. PERFORMANCE
2. PERFORMANCE
2.1 Product Name

P970 : WCDMA900/1900/2100+EGSM/GSM850/DCS/PCS
(HSUPA 5.7Mbps/HSDPA 7.2Mbps / GPRS Class 12 / EDGE Class 12)
2.2 Supporting Standard

Item
Supporting Standard
Feature
Comment
WCDMA(FDD1,2,8)/EGSM/GSM850/DCS1800/PCS1900
with seamless handover
Phase 2+(include AMR)
SIM Toolkit
Frequency Range
: Class 1, 2, 3, C-E
WCDMA(FDD1) TX : 1920 1980 MHz

WCDMA(FDD1) RX : 2110 2170 MHz
EGSM TX : 880 915 MHz
EGSM RX : 925 960 MHz
GSM850 TX
: 824 849 MHz
GSM850 RX
: 869 894 MHz
DCS1800 TX
: 1710 1785 MHz
DCS1800 RX
: 1805 1880 MHz
PCS1900 TX
: 1850 1910 MHz
PCS1900 RX
: 1930 1990 MHz
Application Standard
2.3 Main Parts : GSM Solution

Item
Part Name
Digital Baseband
PMB9801 : Infineon
Analog Baseband
PMB9801 : Infineon
RF Chip
PMB5703: Infineon
Comment
One chip
--

2. PERFORMANCE
2.4 HW Features
Item
Feature
Form Factor
DOP type
Battery
1) Capacity
Comment
Standard : Li-Ion Polymer, 1500mAh

2) Packing Type : Soft Pack
Size
Standard :122 x 64 x 9.2mm
Weight
109g
Volume
TBD
PCB
Any-layer type, 10 Layers , 0.65t
Stand by time
2G Up to 375 hrs
@ Paging Period 9 (2G)
3G Up to 375 hrs
@ DRX 7 (3G)
Charging time
3 hrs
@ Power Off / 1500mAh
Talk time
2G Up to 360 mins
@ Tx=Max(2G)
3G Up to 360 mins
@ Tx = 12dBm (3G)
RX sensitivity
With Battery
WCDMA(FDD1) : -106.7 dBm

TX
EGSM
: -105 dBm
GSM850
: -105 dBm
DCS 1800
: -105 dBm
PCS 1900
: -105 dBm
WCDMA/
WCDMA : 24dBm/3.84MHz,+1/-3dBm
Class3(WCDMA)
output
GSM/
EGSM
: 33dBm
Class4 (EGSM)
power
GPRS
GSM850
: 33 dBm
Class4 (GSM850)
DCS 1800
: 30 dBm
Class1 (PCS)
PCS 1900
: 30 dBm
Class1 (DCS)
EDGE
GSM 900
: 27 dBm
E2 (GSM900)
DCS 1800
: 26 dBm
E2 (PCS)
PCS 1900
: 26 dBm
E2 (DCS)
GPRS compatibility
GPRS Class 12
EDGE compatibility
EDGE Class 12
SIM card type
Plug-In SIM
2.85V /1.8V
--

2. PERFORMANCE
Display
Main LCD(WVGA)
TFT Main LCD(4.0 480 x 800)
Built-in Camera
5M Primary CMOS Camera,

2M secondary camera
Status Indicator
No
Keypad
Function Key : 4
Function Key: Home,Back,
Side Key
menu,serach
:4
Side Key : Volume up,down,

power key, Gesture
ANT
Main : LDS(Laser Direct Structure) type

Sub : DPA type(Directed Print Antenna)
System connector
5 Pin Micro USB
Ear Phone Jack
3.5Phi, 4 Pole, Stereo
PC synchronization
Yes
Memory(AP)
eMMC : 2GB
SDRAM : 4Gbit(POP)
Speech coding
FR, EFR, HR, AMR
Data & Fax
Built in Data & Fax support
Vibrator
Built in Vibrator
BlueTooth
V3.0
MIDI(for Buzzer Function)
SW Decoded 72Poly
Music Player
MP3/ WMA/AAC/HE-AAC/eAAC+
Video Player
MPEG4, H.263, H.264, WMV9/VC-1, DiVX
Camcorder
MPEG4, H.264, H.263
Voice Recording
Yes
Speaker Phone mode
Yes
Support
Travel Adapter
Yes
CDROM
No
Stereo Headset
Yes
Data Cable
Yes
T-Flash
Yes
Up to 32GB
(External Memory)
--

2. PERFORMANCE
2.5 SW Features
Item
Feature
Comment
RSSI
0 ~ 4 Levels
Battery Charging
0 ~ 6 Levels
Key Volume
0 ~ 7 Level
Audio Volume
1 ~ 15 Level
Time / Date Display
Yes
Multi-Language
Yes
Quick Access Mode
Phone / Contacts / Messaging / Menu
PC Sync
Yes
Speed Dial
Yes
Voice mail center -> 1 key
Profile
Yes
not same with feature phone setting
CLIP / CLIR
Yes
Phone Book
Name / Number / Email / Chat Id /
There is no limitation on the number
Website / Postal addresses /
of items.
Organizations / Groups / BirthdayNotes /
It depends on available memory
Ringtone
amount.
Yes
Last Dial Number
CZECH , DUTCH , FRENCH , GERMAN ,

GREEK , ITALIAN , PORTUGUESE ,
SPANISH , ARABIC , HEBREW , T
CHINESE TW , S CHINESE ,
ROMANIAN , HUNGARIAN , SLOVAK ,
CROATIAN , BULGARIAN ,
MACEDONIAN , ICELANDIC
of items.
amount.
Last Received
Yes
Number
of items.
amount.
Last Missed Number
Yes

of items.
amount.
- 10 -

2. PERFORMANCE
Search by Number
Name / N
/ Name
Group
Yes

of items.
amount.
Fixed Dial Number
Yes
Service Dial Number
No
Own Number
Yes
Read only
(add/edit/delete are not supported)
Voice Memo
Yes
Support voice recorder
Call Reminder
Yes
Missed call popup
Network Selection
Automatic
Mute
Yes
Call Divert
Yes
Call Barring
Yes
Call Charge (AoC)
Yes
Call Duration
Yes
SMS (EMS)
There is no limitation on the number of
EMS does not support.
items.
amount.
SMS Over GPRS
No
EMS Melody / Picture
No
Send / Receive / Save
No
MMS MPEG4
Yes
Send / Receive / Save
Yes
Long Message
MAX 459 characters
Cell Broadcast
Yes
Download
Over the Web
Game
Yes
Calendar
Yes
SMS 3pages
- 11 -

2. PERFORMANCE
Memo
Yes

of items.
amount.
World Clock
Yes
Unit Convert
No
Stop Watch
Yes
Wall Paper
Yes
WAP Browser
No
Support only web browser based on

webkit. WAP stack and wml are not
supported.
Download Melody /
Yes
Over web browser
SIM Lock
Yes
Operator Dependent
SIM Toolkit
Class 1, 2, 3, C, D
MMS
Yes
EONS
Yes
CPHS
Yes
ENS
No
Camera
Yes
Wallpaper
V4.2
5M AF /
Digital Zoom : x3
JAVA
No
Voice Dial
No
IrDa
No
Bluetooth
Yes
Android do not support JAVA
Ver. 3.0
(GAP, A2DP, AVRCP) DUN, FTP, GAVDP,
GOEP, HFP, HSP, OPP, SDAP, SPP)
FM radio
Yes
GPRS
Yes
Class 12
EDGE
Yes
Class 12
Hold / Retrieve
Yes
Conference Call
Yes
DTMF
Yes
Memo pad
No
Max. 6
- 12 -

2. PERFORMANCE
TTY
No
AMR
Yes
SyncML
Yes
IM
Yes
Email
Yes
Gtalk
- 13 -

2. PERFORMANCE
2.6 HW SPEC.
1) GSM transceiver specification
Item
Specification
Rms : 5
Phase Error
Peak : 20
GSM : 0.1 ppm
Frequency Error
EMC(Radiated
DCS/PCS : 0.1 ppm

Spurious
Emission
Disturbance)
GSM/DCS : < -28dBm
Transmitter Output power and Burst
GSM : 5dBm 33dBm 3dB
Timing
DCS/PCS : 0dBm 30dBm 3dB
Burst Timing
<3.69us
Spectrum due to modulation out to
200kHz : -36dBm
less than 1800kHz offset
600kHz : -51dBm/-56dBm
GSM :
1800-3000kHz :< -63dBc(-46dBm)
Spectrum due to modulation out to
3000kHz-6000kHz : <-65dBc(-46dBm)
larger than 1800kHz offset to the
6000kHz < : < -71dBc(-46dBm)
edge of the transmit band
DCS :
1800-3000kHz :< -65dBc(-51dBm)
6000kHz < : < -73dBc(-51dBm)
Spectrum due to switching transient

Reference Sensitivity TCH/FS
Usable receiver input level range
400kHz : -19dBm/-22dBm(5/0), -23dBm

600kHz : -21dBm/-24dBm(5/0), -26dBm
Class II(RBER) : -105dBm(2.439%)
0.012(-15 - -40dBm)
Intermodulation rejection Speech
800kHz, 1600kHz
channels
: -98dBm/-96dBm (2.439%)
AM Suppression
T
GSM : -31dBm
DCS : -29dBm
Timing Advance
-98dBm/-96dBm (2.439%)
0.5T
- 14 -

2. PERFORMANCE
WCDMAtransmitter
transmitter specification
specification
2)2)WCDMA
Item
Transmit Frequency
Specification
BD1: 1920MHz ~ 1980 MHz
BD2: 1850~1910 MHz
BD8: 880 MHz ~ 915 MHz
Maximum Output Power
+24 dBm / 3.84 MHz, +1 / -3 dB
Frequency Error
within 0.1 PPM
Open Loop Power Control
Normal Conditions : within 9 dB,

Extreme Conditions : within 12 dB
Minimum Transmit Power
< -50 dBm /3.84 MHz
Occupied Bandwidth
< 5 MHz at 3.84 Mcps (99% of power)
Adjacent Channel Leakage
> 33 dB @ 5 MHz,
Power Ratio (ACLR)
> 43 dB @ 10 MHz
Spurious Emissions
< -36 dBm / 1 kHz RW
|f-fc| > 12.5 MHz
< -36 dBm / 10 kHz RW @ 150 KHz f < 30 MHz
@ 9 kHz f < 150 kHz
< -36 dBm / 100 kHz RW

< -30 dBm / 1 MHz RW
@ 30 MHz f < 1 GHz

@ 1 GHz f < 12.75 GHz
< -60 dBm / 3.84 MHz RW @ 869 MHz f 894 MHz

< -67 dBm / 100 kHz RW @ 925 MHz f 935 MHz
Transmit Intermodulation
< -79 dBm / 100 kHz RW
@ 935 MHz < f 960 GHz
< -71 dBm / 100 kHz RW
@ 1805 MHz f 1880 MHz
< -41 dBm / 300 kHz RW
@ 1884.5 MHz < f < 1919.6 MHz
< -31 dBc @ 5 MHz & < -41 dBc @ 10 MHz

when Interference CW Signal Level = -40 dBc
Error Vector Magnitude
< 17.5 %, when Pout -20 dBm
Peak Code Domain Error
< -15 dB at Pout t -20 dBm
- 15 -

2. PERFORMANCE
3) WCDMA receiver specification

Item
Receive Frequency
Specification
BD1: 2110 MHz ~2170 MHz
BD2: 1850~1910 MHz
BD8: 925 MHz ~ 960 MHz
Reference Sensitivity Level
Band1 : BER < 0.001 when or = -106.7 dBm / 3.84 MHz

Maximum Input Level
BER < 0.001 when or = -25 dBm / 3.84 MHz
Adjacent Channel Selectivity
ACS > 33 dB where BER < 0.001 when
(ACS)
or = -92.7 dBm / 3.84 MHz

& Ioac = 52 dBm / 3.84 MHz @ 5 MHz
Blocking Characteristic
BER < 0.001 when or = -103.7 dBm / 3.84 MHz

& Iblocking = -56 dBm / 3.84 MHz @ Fuw(offset) = 10 MHz
or Iblocking = -44 dBm / 3.84 MHz @ Fuw(offset) = 15 MHz
Spurious Response
BER < 0.001 when or = -103.7 dBm / 3.84 MHz

& Iblocking = -44 dBm
Intermodulation
BER < 0.001 when or= -103.7 dBm / 3.84 MHz

& Iouw1 = -46 dBm @ Fuw1(offset) = 10 MHz
& Iouw2 = -46 dBm / 3.84 MHz @ Fuw2(offset) = 20 MHz
Spurious Emissions
< -57 dBm / 100 kHz BW @ 9 kHz f < 1 GHz

< -47 dBm / 1 MHz BW @ 1 GHz f 12.75 GHz
Adjust output(TPC command)
cmd
+1
Inner Loop Power Control

In Uplink
0
-1
1dB
2dB
+0.5/1.5
-0.5/+0.5
-0.5/-1.5
3dB
+1/3
+1.5/4
-0.5/+0.5
-0.5/+0.5
-1/-3
-1.5/-4
group(10equal command group)

+1
+8/+12
- 16 -
+16/+24

2. PERFORMANCE
4) HSDPA transmitter specification

Item
Specification
Transmit Frequency
BD1: 1920MHz ~ 1980 MHz

BD2: 1850~1910 MHz
BD8: 880 MHz ~ 915 MHz
Maximum Output
Power
Sub-Test
1=1/15,
3=13/15
5=15/7
Subtest in
table
C.10.1.4
HS-DPCCH
2=12/15
4=15/8
6=15/0
21~25dBm / 3.84 MHz

20~25dBm / 3.84 MHz
19~25dBm / 3.84 MHz
Transmitter
power step
tolerance
[dB]
Power
step
Power step slot boundary
Power
step size,
P [dB]
Start of Ack/Nack
+/- 2.3
Start of CQI
+/- 0.6
Middle of CQI
+/- 0.6
End of CQI
+/- 2.3
Sub-Test : 1=1/15, 2=12/15, 3=13/15, 4=15/8, 5=15/7, 6=15/0
Spectrum Emission
Mask
Frequency offset from

carrier f
Minimum requirement
Measurement
Bandwidth
2.5 ~ 3.5 MHz
-35-15(f-2.5)dBc
30 kHz
3.5 ~ 7.5 MHz
-35-1(f-3.5)dBc
1 MHz
7.5 ~ 8.5 MHz
-35-10(f-7.5)dBc
1 MHz
8.5 ~ 12.5 MHz
-49dBc
1 MHz
Adjacent Channel
Leakage
Power Ratio (ACLR)
Sub-Test : 1=1/15, 2=12/15, 3=13/15, 4=15/8, 5=15/7, 6=15/0

> 33 dB @ 5 MHz
> 43 dB @ 10 MHz
Error
Magnitude
< 17.5 %, when Pout -20 dBm
Vector
- 17 -

2. PERFORMANCE
5) HSDPA receiver specification

Item
Specification
Receive Frequency
BD1: 2110 MHz ~2170 MHz

BD2: 1850~1910 MHz
BD8: 925 MHz ~ 960 MHz
Maximum Input Level
Sub-Test : 1=1/15, 2=12/15, 3=13/15, 4=15/8, 5=15/7, 6=15/0
(BLER or R), 16QAM Only
BLER < 10%
or R >= 700kbps
6) HSUPA Tx, Rx specification

Item
Specification
Maximum Output
Power
Sub-Test
1=11/15
2=6/15
3=15/9
4=2/15
5=15/15
21~24dBm / 3.84 MHz

19~22dBm / 3.84 MHz
20~23dBm / 3.84 MHz
20~25dBm / 3.84 MHz
19~25dBm / 3.84 MHz
Sub-Test : 1=11/15, 2=6/15, 3=15/9, 4=2/15, 5=15/15
Spectrum Emission
Mask
Adjacent Channel
Leakage
Power Ratio (ACLR)
Frequency offset from

carrier f
Minimum requirement
Measurement
Bandwidth
2.5 ~ 3.5 MHz
-35-15(f-2.5)dBc
30 kHz
3.5 ~ 7.5 MHz
-35-1(f-3.5)dBc
1 MHz
7.5 ~ 8.5 MHz
-35-10(f-7.5)dBc
1 MHz
8.5 ~ 12.5 MHz
-49dBc
1 MHz
Sub-Test : 1=11/15, 2=6/15, 3=15/9, 4=2/15, 5=15/15

> 33 dB @ 5 MHz
> 43 dB @ 10 MHz
- 18 -

2. PERFORMANCE
6) WLAN 802.11b transceiver specification

Item
Specification
Transmit Frequency
2400 MHz ~ 2483.5 MHz ( CH1~CH13 )
Tx Power Level
20dBm under (Europe), 30dBm under (USA)
Frequency Tolerance
within 25 PPM
Chip clock Frequency
within 25 PPM
Tolerance
Spectrum Mask
-30 @ fc-22MHz< f <fc-11MHz and fc+11MHz< f <fc+22MHz

-50 @ f < fc-22MHz and f > fc+22MHz
Power ramp on/off time
2us
Carrier Suppression
-15dB
Modulation Accuracy
35%
(Peak EVM)
Spurious Emissions
< -36 dBm @ 30MHz ~ 1GHz

< -30 dBm above @ 1GHz ~ 12.75GHz
< -47 dBm @ 1.8GHz ~ 1.9GHz
< -47 dBm @ 5.15GHz ~ 5.3GHz
Rx Min input Sensitivity
-76dBm(1Mbps,2Mbps,5.5Mbps,11Mbps) @ FER 8%
Rx Max input Sensitivity
-10dBm(1Mbps,2Mbps,5.5Mbps,11Mbps) @ FER 8%
Rx Adjacent Channel
35dB @FER 8%,
Rejection
interference input signal -70dBm@fc25MHz(11Mbps)
- 19 -

2. PERFORMANCE
7) WLAN 802.11g transceiver specification

Item
Specification
Transmit Frequency
2400 MHz ~ 2483.5 MHz ( CH1~CH13 )
Tx Power Level
Frequency Tolerance
within 25 PPM
within 25 PPM
Tolerance
Spectrum Mask
-20 @ 11MHz offset (9Mhz ~ 11MHz)

-28 @ 20MHz offset (11MHz ~ 20Mhz)
Transmitter constellation error
-5dB@6Mbps, -8dB@9Mbps, -10dB@12Mbps,
(rms EVM)

-22dB@48Mbps, -25dB@54Mbps
Spurious Emissions
< -36 dBm @ 30MHz ~ 1GHz

< -47 dBm @ 1.8GHz ~ 1.9GHz
< -47 dBm @ 5.15GHz ~ 5.3GHz
PER 10%
-82dBm@6Mbps, -81dBm@9Mbps, -79dBm@12Mbps
-66dBm@48Mbps, -65dBm@54Mbps
-20dBm(6,9,12,18,24,36,48,54Mbps) @ PER 10%
Rx Adjacent Channel
PER 10%,
Rejection
ACR 16dB@6Mbps, ACR 15dB@9Mbps,

ACR 13dB@12Mbps, ACR 11dB@18Mbps,
ACR 8dB@24Mbps, ACR 4dB@36Mbps
ACR 0dB@48Mbps, ACR -1dB@54Mbps
ACR shall be measured by setting the desired signal's strength 3 dB
above the rate-dependent
sensitivity specified in min input sensitivity
- 20 -

2. PERFORMANCE
8) WLAN 802.11n transceiver specification

Item
Specification
Transmit Frequency
2400 MHz ~ 2483.5 MHz ( CH1~CH13 )
Tx Power Level
Frequency Tolerance
within 25 PPM
within 25 PPM
Tolerance
Spectrum Mask
-20 @ 11MHz offset (9Mhz ~ 11MHz)

Transmitter constellation error
-5dB@6.5Mbps, -10dB@13Mbps, -13dB@19.5Mbps,
(rms EVM)

-25dB@58.5Mbps, -28dB@65Mbps
Spurious Emissions
< -36 dBm @ 30MHz ~ 1GHz

< -47 dBm @ 1.8GHz ~ 1.9GHz
< -47 dBm @ 5.15GHz ~ 5.3GHz
PER 10%
-82dBm@6.5Mbps, -79dBm@13Mbps, -77dBm@19.5Mbps
-65dBm@58.5Mbps, -64dBm@65Mbps
-20dBm(6.5,13,19.5,26,39,52,58.5,65Mbps) @ PER 10%
Rx Adjacent Channel
PER 10%,
Rejection
ACR 16dB@6.5Mbps, ACR 13dB@13Mbps,

ACR 11dB@19.5Mbps, ACR 8dB@26Mbps,
ACR 4dB@39Mbps, ACR 0dB@52Mbps
ACR -1dB@58.5Mbps, ACR -2dB@65Mbps
ACR shall be measured by setting the desired signal's strength 3 dB
above the rate-dependent
sensitivity specified in min input sensitivity
- 21 -

2. PERFORMANCE
9) GPS receiver specification

Item
Specification
Receive Frequency
1574.42 MHz ~ 1576.42 MHz
Minimum Sensitivity
1 satellite -142dBm, 7 satellites -147dBm at coarse time aiding
10) Current consumption

Stand by
Bluetooth Off
Bluetooth Connected Voice Call
VT
WCDMA
4.0 mA under
7 mA under
350 mA under
NA
Only
(DRX=1.28)
(DRX=1.28)
(Tx=12dBm)
GSM
4.0 mA under
7 mA under
350 mA under
Only
(Paging=5 period)
(Paging=5 period)
(Tx=Max)
11) Battery life time

Stand by
WCDMA
GSM
350 hours over

(DRX = 1.28)
Voice Call
VT
250 min over

(TX = 12dBm,
NA
Low Pwr mode)
350 hours over
250 min over
(Paging Period = 9)
(TX Level = Max)
- 22 -

2. PERFORMANCE
12) Charging hour

3.5hour under ( 1500mAh battery, 1A TA)
- 23 -

2. PERFORMANCE
13) RSSI indicator (Based on Cell power)

BAR
WCDMA
GSM/DCS/PCS
Over -902dBm
Over -90 2dBm
43
-90 2dBm
-90 2dBm
32
-96 2dBm
-97 2dBm
21
-102 2dBm
-103 2dBm
10
-110 2dBm
-107 2dBm
14) Battery indicator

Battery Bar
Specification
BAR 6 (Full)
90% over
BAR 6 --> 5
90% 89%
BAR 5 --> 4
70% 69%
BAR 4 --> 3
50% 49%
BAR 3 --> 2
30% 29%
BAR 2 --> 1
15% 14%
BAR 1 --> 0
5% 4%
Low Battery Pop-up
4% ~ 15% : One Time popup (No call)
Critical Low Battery Pop-up
0% ~ 3% : Every Level change popup (No call)
POWER OFF
0%
remain%
- 24 -

3. Technical Brief
3. TECHNICAL
BRIEF BRIEF
3.
TECHNICAL
3.1 GENERAL DESCRIPTION

The LG-P970 supports UMTS-900, UMTS-1900, UMTS-2100, GSM-850, GSM-850, GSM-900, GSM-1800, and GSM1900 based GSM/GPRS/EDGE/UMTS. All receivers and the UMTS transmitter use the radioOne1Zero-IF
architecture to eliminate intermediate frequencies, directly converting signals between RF and baseband. The
quad-band GSM transmitters use a baseband-to-IF upconversion followed by an offset phase-locked loop that
translates the GMSK-modulated or 8-PSK-modulated signal to RF.
rF Block Diagram
FEM
with
GSM
FSY2_CLK
PAM
VCTCXO
26MHz
SKY77529
XO
VCONT
G850/G900
TX_LB
TX_HB
AFC_DAC
DCS/PCS
DET
W900
Duplexer
RXTX_L2
WCDMA
Dual PAM
ACPM-5281
W2100
Duplexer
RXTX_H
CPL
W1900
Duplexer
RXTX_M1
F26M
SYS_CLK
TX2G_L
TX2G_M
W-PAM
ACPM-5202
CPL
WCDMA
TX SAW
TX_3G_L
WCDMA
TX SAW
TX_3G_H
WCDMA
TX SAW
TX_3G_M
DI3_TX_DAT
DI3_TX_DATX
Di3_TX_DAT
Di3_TX_DATX
DI3_RX_DAT
DI3_RX_DATX
Di3_RX_DAT
Di3_RX_DATX
MP-eHM
transceiver
PMB9801
PMB5703
PWR DET
PA_POW_DET
RFIN1
1900
RX SAW
LNA
RFIN4BGA749
RX_M2 ~MnGX`WWG nGX`WW

RX_M2X
2100
RX SAW
RX_H
RX
H
~GYXWW
RX_HX
RFIN5
900
RX SAW
RX_L1
~MnG`WW
RX_L1X
RX SAW
RX_L2
nG_\W
RX_L2X
RFIN2
RX_M2
RX_L1
RX_M3
850
1800
RX SAW
VDD_MAIN
VDD_FSYS
RX_M1 nGX_WW
RX_M1X
VDD_IO
2.85V_RF1
2.85V RF2
2.85V_RF2
1.8V_SD
VRF1
VRF2
VSD2
[Figure 3-1] Block diagram of RF part
- 25 -

3. Technical Brief
General
SMARTi UE is a highly integrated UMTS/GSM-transceiver, with all necessary features to enable multi
mode,multi band telephone applications. It incorporates a fully integrated dual mode receiver, multi band TX
outputs,TCVCXO control, a measurement interface, DigRF V3.09 compliant high speed data and control interface,
a multi mode timer unit and all necessary front end signals for the complete RF Engine control. Overall the IC
directly supports RF engines with up to 4 GSM bands and typ. 3 UMTS (can be less or more depending on engine
setup) bands without additional discrete RF path switches.
Receiver Section
For the RX section the IC features 5 RX inputs, 4 of those might be used for multi mode receive, this means they
can be used for GSM and UMTS (the IC can be reconfigured to achieve in spec performance) operation. The band
I input is for UMTS operation only. The multi mode inputs may alternatively be configured to be first LNA (for
GSM) or LNA2 (UMTS) when an additional external LNA and interstage filter is used. The receiver structure is
optimized for compressed mode operation, thus only a single base band chain is used, saving area and
optimizes power consumption.The receiver AGC can be aligned to the UMTS frame structure with the TAS macro
SYNC3G.
Transmitter Section
The TX features 6 RF outputs, which are directly matched to 50 impedance for easy connection to external
power amplifiers, which reduces significantly external component count. 2 outputs are high power, small signal
polar modulated outputs for the GSM system, with low sensitivity to PA harmonics. They are capable to perform
GMSK or 8-PSK modulation signals with excellent noise performance, thus no interstage filter in between
transceiver and PA is required. The low band output covers the 850 and the 900 MHz GSM bands, the mid band
output covers the 1800 and 1900 MHz bands.
The UMTS outputs are vector modulated single ended high output power driver amplifiers, with excellent EVM
and adjacent channel leakage performance. Together with external UMTS power amplifier modules all bands
except band VII can be addressed. There is one driver for all low bands (850 and 900 MHz bands), two drivers for
the mid bands (1700 - 1900 MHz bands) and one driver for the high band (2100 MHz band). Thus many band
combinations can be supported by the transceiver.
The IC features additionally closed loop power control for GSM and for UMTS, thus supporting TRP requirements
in cooperation with the power amplifier and the antenna design. There is one input pin for the power detector
voltage coming from the PA, the complete loop circuits are implemented in the digital domain, which enables a
high reliability of the loop performance for both standards.
- 26 -

3. Technical Brief
Interfaces
The base band is connected via a DigRF V3.09 high speed data interface with a maximum clock frequency of 312
MHz. The pure digital interface enables the digital baseband to shrink efficiently, as all the analog functionality is
within the RFIC. All data and control traffic is multiplexed via the RX and TX interface lines. The IC features a high
level programming model enabling the complete compressed mode operation of the device in an RF engine
environment.It handles RX and TX power control, also incorporating the calibration data. The complete timing is
optimized for compressed mode operation of the transceiver, it controls the front end components of the
engine (PAs, switches, LNAs). Additionally a SPI control bus for front end component control is available in the
IC, which also enables the readback of data from external components, thus the handling of functions like PA
saturation, mismatch detection, overheating (incorporated in the closed loop power control) can be adopted.
AFC Control
The AFC control is maintained by providing a voltage generated by a 12-Bit DAC to the external TCVCXO module,
which means the reference clock is synchronized to the system frequency.
- 27 -

3. Technical Brief
3.2 GSM MODE

3.2.1 GSM RECEIVER
The GSM-850/GSM-1800, receiver inputs of PMB5703 are connected directly to the transceiver front-end Module.
The GSM-900/GSM-1900 receiver inputs are using the Rx path with WCDMA1900 and WCDMA900 bands. The
GSM-850, GSM-900, GSM-1800, and GSM-1900 receiver inputs use differential configurations to improve
common-mode rejection and second-order non-linearity performance.
Figure 3-2 shows the line-up for the 2G receiver chain for bands serving only GSM. The RX digital front-end (DFE)
contains all digital signal processing. Blue arrows show gain switching inputs of the signal processing stages.
The signal path splits at the mixer input into an in-phase and an identical quadrature path. For simplicity the 2nd
path is not shown in the figure. The quadrature downconverter translates the useful signal directly to baseband
(zero-IF).
switch
RF filter
20 dB
gain step
17 dB
gain step
6 dB
gain step
35 dB
gain range
(1 dB step)
LNA
mixer
analog
baseband filter
buffer
[Figure 3-2] 2G Receiver Line Up-GSM Single Mode Setup
- 28 -

3. Technical Brief
Figure3-3 shows the 2G receiver line-up in a multimode band. Note the gain step given for the external LNA may
vary from the given value. The chain is basically identical to the 3G line-up but many stages in analog and digital
domain are switched into a different operation mode.
16/-7dB
switch
duplexer
LNA1
interstage
filter
LNA2
17 dB
gain step
6 dB
gain step
35 dB
gain range
(1 dB steps)
mixer
analog
baseband filter
buffer
[Figure 3-3] 2G Receiver Line Up-GSM Multi Mode Setup
Since GSM-850, GSM-900, GSM-1800, and GSM-1900 signals are time-division duplex (the handset can only
receive or transmit at one time), switches are used to separate Rx and Tx signals in place of frequency duplexers
this is accomplished in the switch module. The GSM-850, GSM-900, GSM-1800, and GSM-1900 receive signals
are routed to the PMB5703 through band selection filters and matching networks that transform single-ended
50- sources to differential impedances optimized for gain and noise figure. The PMB5703 input uses a
differential configuration to improve second-order intermodulation and common mode rejection performance.
The downconverted baseband outputs are multiplexed and routed to lowpass filters (one I and one Q) having
passband and stopband characteristics suitable for GMSK or 8-PSK processing. These filter circuits include DC
offset corrections.
- 29 -

3. Technical Brief
3.2.2 GSM TRANSMITTER

The transmitter takes the modulating symbols sent from baseband via DigRF Interface and converts them into a
RF signal. It is based on a polar modulator architecture where amplitude and phase (or alternatively frequency)
are first handled separately and afterwards are merged in the RF domain.
The signal flow can be understood when you look at Figure 3-4. The digital symbol stream enters either a 8PSK
or a GMSK modulator, depending on the desired mode. The GMSK signal is thereby differentially encoded as
postulated by GSM specification 45.004. If a generator runs out of symbols, it behaves as if an input series of
repeating dummy symbols has been applied. To simplify mode switching between 8PSK and GMSK, the two
generators are synchronized. In 8PSK mode, the output of the internal 8PSK signal generator is given in
Cartesian (I/Q) coordinates. The desired conversion into polar coordinates (amplitude and phase) is executed by
a CORDIC algorithm. For GMSK mode the CORDIC algorithm is not involved - the incoming GMSK symbols
directly determine the modulation frequency of the sigma-delta modulation loop.
In the phase path the phase signal is differentiated to obtain a frequency signal, which is fed into a preemphasis
filter to compensate for narrow PLL bandwidth. Afterwards it is applied to the Sigma-Delta modulation loop. In
this way the Sigma-Delta PLL shifts the phase information into RF domain.
The digital amplitude signal is multiplied with the ramping waveform, converted into an analog voltage and
filtered. After that it is mixed with the purely phase modulated RF carrier to gain an amplitude and phase
modulated output signal. The output power can be influenced directly by a PGA (programmable gain amplifier),
if no power control loop is needed, or by specifying a target output level, if a closed power loop for enhanced
output power accuracyis desired.
[Figure 3-4] 2G Transmitter Line Up
- 30 -

3. Technical Brief
3.3 UMTS MODE

3.3.1 UMTS RECEIVER
Figure 3-5 shows the line-up for the 3G receiver chain. Note that the high gain / low gain figures for external
LNA1 are given as an example. The blue arrows indicate the gain control inputs for the AGC subsystem. The
quadrature path is a simple copy of the chain from mixer to DigRF and is not shown in the diagram.
For band l:
SMARTIUE
other bands:
extemal LNA1
switch
duplexer
LNA1
35 dB
gain range
(1 dB steps)
12 dB
gain step
16 / -7 dB
inter stage
filter
LNA2
mixer
analog
baseband filter
buffer
[Figure 3-5] 3G Receiver Line Up

After quadrature downconversion to baseband(Zero-IF) the signal is fed to the analog baseband filter.
The range and gain step of the following buffer amplifier is actually determined by the needs of the AGC in 3G
mode.
- 31 -

3. Technical Brief
3.3.2 UMTS TRANSMITTER

Figure 3-6 shows a functional overview of the 3G transmitter chain implemented for RF signal processing. The
IQ-chips, which are transferred via the digital interface, are stored in a FIFO. Then it depends on the setting of
three signals how samples are consumed from the FIFO Buffer.
Then the samples are fed into a CORDIC, which is used to shift the phase of the complex signal. The rootraisedcosine (RRC) filter performs the pulse shaping according to 3GPP. As the system clock is no integer
multiple of the UMTS chip rate a fractional sample rate conversion (FSRC) is necessary. In the amplitude
correction / offset correction (AC/OC) block the amplitude and the offset of the IQ-signal are modified.
The final sample rate at the output of the digital front end is achieved in the interpolation / noise shaping block,
where also the word length is reduced in order to fit to the D/A-converter resolution. After the DAC a post-filter
reduces the level of the repetition spectrum and the analog noise in order to supply a clean signal to the IQmodulator. The frequency conversion to the wanted TX-channel is done in a direct-up conversion IQ-modulator
which is followed by a gain stage with a single ended high power output.
Interface
Digital Front End (DFE)
DAC
Postfilter
RF
AD / RET
FIFO
DIG RF 3G
CORDIC
ICMP
12 bh
sign
FSRC
time adj.
RRC
AC / OC
interp
NZsh
LO
QCMP
12 bh
sign
CORDIC
Word
REQ
DC offset comp
EN
[Figure 3-6] 3G Transmitter Line Up
- 32 -

3. Technical Brief
3.4 GPS RECEIVER

The Global Positioning System (GPS) is a space-based global navigation satellite system (GNSS) that provides
reliable location and time information in all weather and at all times and anywhere on or near the Earth when
and where there is an unobstructed line of sight to four or more GPS satellites. The GPS Receiver of P970 built-in
BCM4751 is A-GPS chipset is made by BROADCOM that uses a host based integration architecture that splits
processing functions between the GPS core and the CPU on the Host system. The Broadcom BCM4751 is a
single-chip GPS receiver used for tracking and navigation, primarily in mobile devices. Its massively parallel,
hardware correlator architecture provides signal searches, accurate real-time navigation, improved tracking
sensitivity and low average power consumption.
Fig3.7. Block diagram of BCM4751
The BCM4751 supports additional satellite constellations including the Satellite Based Augmentation System
(SBAS) and the Quasi-Zenith Satellite System (QZSS) for Japanese applications, making as many as twelve
additional satellites available for use in navigation.
The BCM4751 GPS receiver offers 65nm CMOS design featuring a highly-integrated RF and baseband processor
with extremely low power consumption. It also claims smallest complete PCB footprint at 30mm2 including
band-pass filter, TCXO and passives.
BCM4751 GPS receiver includes software that meets international standards bodies such as 3GPP, GERAN and
OMA, which promote the delivery of GPS assistance data over cellular networks. Figure shows block diagram of
BCM4751.
The GPS signal is received by the antenna and amplified by an internal LNA. The differential signal coming out of
the LNA is sent to an I/Q mixer, which uses a local Oscillator to directly down-convert the signal to an IF Near
6MHz.
- 33 -

3. Technical Brief
Fig3.7. Block diagram of BCM4751
The BCM4751 supports additional satellite constellations including the Satellite Based Augmentation System
(SBAS) and the Quasi-Zenith Satellite System (QZSS) for Japanese applications, making as many as twelve
additional satellites available for use in navigation.
The BCM4751 GPS receiver offers 65nm CMOS design featuring a highly-integrated RF and baseband processor
with extremely low power consumption. It also claims smallest complete PCB footprint at 30mm2 including
band-pass filter, TCXO and passives.
BCM4751 GPS receiver includes software that meets international standards bodies such as 3GPP, GERAN and
OMA, which promote the delivery of GPS assistance data over cellular networks. Figure shows block diagram of
BCM4751.
The GPS signal is received by the antenna and amplified by an internal LNA. The differential signal coming out of
the LNA is sent to an I/Q mixer, which uses a local Oscillator to directly down-convert the signal to an IF Near
6MHz.
GPS_2.8V
R801
GPS_2.8V
10
R802
4.7K
0.1u
C804
L801
5
L803
9.1n
C808
CN801
330p
1.8n
CN802
1
C803
47p
S_D
C802
VDD
FIL_OUT
RF_IN
GND
L802
FL801
1575.42 MHz
6.8n
OUT
IN
G3G2G1
L804
100n
U802
C807
5 3 2
L812
2.2n
C816
C806
DNI
DNI
0.5p
1.8p
Fig3.8. The Schematic of GPS RF path circuit of P970
- 34 -

3. Technical Brief
Fig3.8. The Schematic of GPS RF path circuit of P970
Figure shows the schematic of GPS RF path circuit of P970, The CN801has connected GPS antenna, GPS signal is
routed from connector (CN801) and antenna, through a dielectric band pass filter (FL801) and then is amplified
by The GPS LNA module(U802).
The GPS LNA module combines low noise amplifier with filter. The LNA module has RF character, that is 18.2dB
gain and 0.95dB noise figure and rejected spurious signal.
FB801
?
C801
2.2u
B5
B3
E4
D4
D3
F2
VDDLNA
E2
VDDIF
VDDPL
SYNC/PPS_OUT
IFVALID
RST_N
REGPU
TM2
AVSS
VSSC1
VSSC2
VSSC3
A6
C3
SCL2/UART_TX
SDA2/UART_RX
UART_nRTS
UART_nCTS
VDD_BAT
C4
REF_CAP
1.8V_VIO
SDA1
SCL1
L803
G1
9.1n
F1
G2
C808
A5
26MHz_GPS_REF
GPS_26MHz
CLK32K_TWL
D1
D5
D2
1.8p
C1
E1
A3
A2
GPS_GSM_CTL
GPS_RESET_N
GPS_PWR_ON
B6
G6
E6
A4
C5
G5
C6
U801
VDD_PRE
G4
GPS_CAL
TCXO/TSXO
LPO_IN
ADCP
VDDADC
ADCN
F6
GPS_UART_RXD
GPS_UART_TXD
GPS_UART_CTS_N
GPS_UART_RTS_N
10n
C810
2.2u
VDD1P2_GRF
F4
B2
C809
D6
B1
RFIP
VSSIF
VSSLNA
VDDC2
VDDC1
E5
VDD_AUX_O
VDD_AUX_IN
HOST_REQ
LNA_EN
VDD1P2_CORE
E3
CAL_REQ/ANT_SEL
VSSADC
B4
C2
AUXOP
F5
A1
VDDIO
G3
F3
GPS_TCXO_1.8V
GPS_2.8V
1.8V_VIO
C811
2.2u
C812
2.2u
C813
2.2u
Fig3.9. The Schematic of GPS main circuit of P970
- 35 -

3. Technical Brief
The amplified GPS signal due to GPS LNA module, go into RFIP pin of U801 GPS chipset. Figure. shows the
schematic of GPS main circuit of P970. The internal LNA/mixer in U801 down-converts the 1575.42MHz GPS
signal to an intermediate frequency of approximately 6.2 MHz. Setting the IF at around 6MHz reduces the
sensitivity of the GPS RF to flicker noise and DC offset.
The TCXO (X801) makes 26MHz reference clock that drives the frequency synthesizer into U801 that generates
about 1.5GHz LO signal. The frequency synthesizer conations a fraction-N PLL consisting of on-chip
VCO and supports a wide rage of reference frequencies, including all frequencies commonly specified in mobile
phone standards.
The GPS receiver input employs a single-ended connection realized by this pin. The GPS input is routed from the
GPS antenna switch, through a band pass filter and then an impedance transformer circuit that optimally
matches the impedance looking into the GPS LNA. The impedance transformer circuit topology is shown in
Figure 3.10.
[Figure 3.10] GPS Input Network Topology
- 36 -

3. Technical Brief
3.5 LO GENERATION and DISTRIBUTION CIRCUIT

The PMB 5703 contains two synthesizer blocks (see Figure3-6). Depending on UMTS or GMSK/8-PSK mode
different VCOs, LF and CPs settings are used. In GMSK/8-PSK mode only the TRX PLL loop with the 2G TRX VCO is
working, which is available in the TX synthesizer block (left). In UMTS TX/RX mode, two separate synthesizer
blocks are available. The TX synthesizer is in the UMTS TX block (left), where the loop is working with the 3G TX
VCO. The RX synthesizer is in UMTS RX block working with the 3G RX VCO.
[Figure 3-6] RF Synthesizer (GMSK/8-PSK and UMTS)
- 37 -

3. Technical Brief
In the PMB 5703 the receiver and the transmitter contain each a complete fractional-N sigma-delta synthesizer
with fast locking. For GMSK/8-PSK RX operation mode a fractional-N sigma-delta synthesizer for the frequency
synthesis is used. For GMSK/8-PSK TX operation mode the fractional-N sigma-delta synthesizer is used as a
Sigma-Delta modulation loop to process the phase/frequency signal.
A 26 MHz reference signal (provided by an internal clock generation block) serves as comparison frequency of
the phase detector. In GMSK/8-PSK mode the divider in the feedback path of the synthesizer is carried out as a
multi-modulus divider (MMD). The GMSK/8-PSK loop filter is fully integrated and the loop bandwidth is about
100 kHz to allow the transfer of the phase modulation during GMSK/8-PSK operation. The open loop gain is
automatically adjusted prior to each GMSK/8-PSK slot . To overcome the statistical spread of the loopfilter
element values an automatic loopfilter adjustment is performed before each GMSK/8-PSK synthesizer startup.
The fully integrated GMSK/8-PSK quad-band VCO is designed for the four GMSK/8-PSK bands (850, 900,
1800,1900 MHz) and operates at double (for GSM1800 and GSM1900 band) or four times (for GSM850 and
GSM900 band) of the transmit or receive frequency. To cover the wide frequency range the VCO is automatically
aligned by a binary automatic band selection before the settling process of the synthesizer starts. In UMTS TX
and RX mode a fractional-N sigma-delta synthesizer for the frequency synthesis is used.
The implemented divider in the feedback path of the synthesizer is carried out as a multi-modulus divider
(MMD). Also the 26 MHz reference signal serves as comparison frequency of the phase detector. The UMTS loop
filter is fully integrated and the loop bandwidth is about 180 kHz. The open loop gain is automatically adjusted
prior each UMTS channel programming.
The two fully integrated UMTS VCOs are designed for the UMTS bands (I, II, III, IV, V, VI, VIII, IX and X) and operates
at double (for bands I, II, III, IV, IX and X) or four times (for bands V, VI and VIII) of the transmit or receive
frequency. To cover the wide frequency range the VCOs are automatically aligned by a binary automatic band
selection before the settling process of the synthesizer starts.
- 38 -

3. Technical Brief
3.6 OFF-CHIP RF COMPONENTS

3.6.1 UMTS PAM
3.6.1.1 W2100,W900 (U105, ACPM-5281), W1900(U103, ACPM-5202)
The ACPM-5281 is a dual-band PAM (Power Amplifier Module) designed for UMTS Band1 and Band8. The ACPM5281 meets stringent UMTS linearity requirements. The 4mmx5mm form factor 14-pin surface mount package is
self contained, incorporating 50ohm input and output matching networks.
The ACPM-5202 is a fully matched 10-pin surface mount module developed for UMTS Band2. This power
amplifier module operates in the 1850-1910MHz bandwidth. The ACPM-5202 meets stringent UMTS linearity
requirements up to 28dBm output power (Rel99). The 3mmx3mm form factor package is self contained,
incorporating 50ohm input and output matching networks
The ACPM-5281 and ACPM-5202 feature 5th generation of CoolPAM circuit technology which supports 3
modes bypass, mid and high power modes. The CoolPAM is stage bypass technology which enables power
amplifier to lower power consumption. Active bypass feature is added to 5th generation to enhance power
added efficiency at low output range and this technology extends talk time of mobiles more by further saving
power amplifiers current consumption. The power amplifier is manufactured on an advanced InGaP HBT
(hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering stateof-the-art reliability, temperature stability and ruggedness.
[Figure 3-7] ACPM5281 (W2100,W900)
[Figure 3-8] ACPM-5202(W1900)
- 39 -

amplifier module operates in the 1850-1910MHz bandwidth. The ACPM-5202 meets stringent UMTS linearity
requirements up to 28dBm output power (Rel99). The 3mmx3mm form factor package is self contained,
incorporating 50ohm input and output matching networks
The ACPM-5281 and ACPM-5202 feature 5th generation of CoolPAM circuit technology which supports 3
modes bypass, mid and high power modes. The CoolPAM is stage bypass technology which enables power
3. to
Technical
amplifier to lower power consumption. Active bypass feature is added to 5th generation
enhance powerBrief
added efficiency at low output range and this technology extends talk time of mobiles more by further saving
power amplifiers current consumption. The power amplifier is manufactured on an advanced InGaP HBT
(hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering stateof-the-art reliability, temperature stability and ruggedness.
[Figure 3-7] ACPM5281 (W2100,W900)
[Figure 3-8] ACPM-5202(W1900)
- 40 -

3. Technical Brief
3.6.2 26MHz VCTCXO (X101, DSA221SCL)

The Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO) provides the reference
frequency for all RFIC synthesizers as well as clock generation functions within the PMB5703 IC. The oscillator
frequency is controlled by the PMB5703 ICs.
TRK_LO_ADJ pulse density modulated signal in the same manner as the transmit gain control TX_AGC_ADJ. A
two-pole RC lowpass filter is recommended on this control line.
The PM7540 IC controls the handset power-up sequence, including a special VCTCXO warm-up interval before
other circuits are turned on. This warm-up interval (as well as other TCXO controller functions) is enabled by the
MSM TCXO_EN line . The PM7540 IC VREG_TCXO regulated output voltage is used to power the VCTCXO and is
enabled before most other regulated outputs. Any GSM mode power control circuits within the MSM7227 IC
require a reference voltage for proper operation and sufficient accuracy.
Connecting the PM7540 IC REF_OUT directly to the MSM7227 IC GSM_PA_PWR_CTL_REF provides this reference.
This sensitive analog signal needs a 0.1 F low frequency filter near to MSM side, and isolate from digital logic
and clock traces with ground on both sides, plus ground above and below if routed on internal layers.
- 41 -

3. Technical Brief
3.6.3 FEM + GSM PAM (U104, SKY77529)

The SKY77529 Tx Front End Module (FEM) is designed in a compact form factor for quad-band cellular handsets
comprising GSM850/900, DCS1800, PCS1900, supporting GMSK and linear EDGE modulation. Class 12 General
Packet Radio Service (GPRS) multi-slot operation is also supported.
The module consists of a GSM850/900 PA block and a DCS1800/PCS1900 PA block, a printed directional coupler
for each block impedance-matching circuitry for 50 input and output impedances, a multifunction power
amplifier control (MFC) block, low pass harmonic rejection filters, and an SP8T Antenna T/R switch. Two separate
Hetero junction Bipolar Transistor (HBT) PA blocks are fabricated onto an InGaP die; one supports the
GSM850/900 bands, the other supports the DCS1800 and PCS1900 bands. The InGaP PA die, the silicon MFC die,
PHEMT switch die, and the passive components are mounted on a multi-layer laminate substrate. The assembly
is encapsulated with plastic overmold.
The FEM incorporates full support for a Serial Peripheral Interface (SPI) bus function. The SPI controller shall
accept SPI telegrams with data fields that support PA and switchplexer-related functions. All FEM operating
modes and switch states shall be determined by the SPI telegram. The Multi-function Control (MFC) provides pin
out for interoperation with a specified transceiver that will establish a closed loop power control mechanism.
The external circuit uses the Linear Detector output to set a fixed bias point for 8PSK (EDGE) mode and a variable
bias point for GMSK (GSM) mode.
The power control loop together with the MFC will reduce sensitivity to antenna load, input drive, temperature,
power supply, and process variation. The combined circuit configures the PA for fixed gain in 8PSK mode while
providing the ability to optimize the PA bias at different power levels to maximize efficiency.
V-Q3_HB
VCMOS
Tx_HB
RxTx-H
Match
VSPI
SERIAL
CLK
PERIPHERAL
DRW
INTERFACE
SS
CONTROL
VDET
LINEAR RF
DETECTOR
VRAMP
POWER
AMP
CONTROL
Rx-M3
BICMOS
MFC
Rx-M2
ANTENNA
RxTx-M1
Rx-L1
Tx_LB
Match
RxTx-L2
V-Q3_LB
Batt
[Figure 3-10] SKY77529 Block Diagram
- 42 -

3. Technical Brief
[Figure 3-11] SPI Write Programming Truth Table
3.6.4 GPS LNA (U802, ALM1612)

The ALM1612 is a GPS Low Noise Amplifier with an integrated SAW filter at the output. Low noise figure, along
with high gain, achieved by the ALM1612 makes it ideal for GPS recievers requiring high sensitivity. This module
builds upon AVAGO leading edge pHEMT process and integrates input matching and low loss high rejection
SAW filter at the output. This results in high performance and a reduced solution size. The ease of
implementation simplifies the reciever design.
The ALM1612 is packaged in a compact 3.3 mm x 2.1 mm x 1.2 mm package with low external component count
required to achieve the best-in-class performance.
- 43 -

3. Technical Brief
3.7 Digital Baseband ( OMAP3630 / X-GOLD 616 )

3.7.1 General Description
A. Features (OMAP3630)
The OMAP3630 high-performance, multimedia application device is based on the enhanced OMAP 3
architecture and ins integrated on TI advanced 45-nm process technology
The architecture is designed to provide bes-in-class video, image, and graphics processing sufficient to support
the following
-Streaming video
-2-dimension / 3-dimensionmobile gaming
-High-resolution still image
-Support OS such as Windows CE / Symbian OS / Linux / Android OS
-Microprocessor unit subsystem based on the ARM cortex A8
-Imaging video and audio subsystem with TMS320C64x DSP core
-L3/L4 interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and
external memory controllers and to on-chip peripherals
-120-KB ROM / 64-KB single-access SRAM on-chip memory
-Peripherals
-Universal asynchronous receiver/transmitter , Three general interface & UART + IrDA SIR
-Multichannel buffered serial port, Three general purpose and two audio loopback capable
-Three master/slave inter-integrated circuit(I2C) high speed standard interfaces
-High speed multiport USB host and High speed USB ON-The-Go
-High-speed controller that offers high-speed data transactions on a USB port with embedded DAM
-High speed MMC/SD/SDIO 1/2/3
-General purpose times ( eleven GP timers )
-Two Watchdog timers / 32 kHz clock timer
- Six 32-bit GPIO controllers
- 44 -

3. Technical Brief
B. Features (X-GOLD 616)

The X-GOLD 616 is GSM/UMTS/GPRS/EDGE/HSDPA/HSUPA baseband controller with integrated mixed signal
audio and measurement subsystem and modem power management unit.
The processing of the upper 2G.3G cellular protocol stack layer are handled by and ARM 1176 embedded
microcontroller
The Key features are following
-Audio : Loudspeaker (stereo) / external chip support / microphone and other audio input / ringtones
-Modem : 3GPP release 6 / HSDPA category 8 / HSUPA category 6 /E-GPRS class 33 etc.
-ARM 11 : operating frequency 416MHz
-Sensors with analog measurement interface
-Memory types : SDRAM / LPDDR1-DRAM / NOR / DDR-NOR / eSD / eMMC / SD / MMC
-High speed interface to SIM & USB 2.0 HS
-Package size : 8 8 0.8 mm, 0.4 mm pitch
- 45 -

3. Technical Brief
3.8 Hardware Architecture

<System HW Block>
B
project Block Diagram
VT Cam
Camera
2M
5M MIPI
EDGE
26M
PCM UART SDIO
m
nzt
l
wht
t
Bluetooth
transceiver
PMB5703
Wi-Fi FM
Di3 RF I/F
MCP(CP)
Dg x
PCM
X32
SDRC
X16
GPMC
4Gb DDR
SDRAM
I2C2
Address
USIM
I2C
USB DP/DM tWL

|ziGpm
|hy{Gvthw
MUIC
|hy{Gy{
|hy{Gz~
LCD BL Charge Pump
LCD Backlight
Proximity sensor
Motion
eMMC
(2GB)
Driver
GPIO for PWM
HS USB data
GPIO
HS USB data
INT1
DP/DN
PCM
Touch Screen
Hall IC
MMC1
TWL5034
I2C3
Gyro
Compass
Key LED
Driver
I2C1 I2C4
KPD
I2S
I2C2
Touch Driver
AMBIENT
OMAP3630
UART3_TX_IRRX/TX
UART4 (GPMC_WAIT)
16
Touch module
Mounted
M
t d on
OMAP3630
I2C2
LCD 4.0
WVGA (800X480)
I2C2
GPIO
I2C
SPI2
I2C1
I2C2
I2C3
A-GPS
DSS_DAtA
MMC2
1Gb NAND
Battery
(1500mAh)
MCP(AP)
16
512Gb DDR
SDRAM
Charger
IC
GPIO
I2C
USIF3
USIF
USB
PCM
MEM_AD
WCDMA
CC_000
MEM_A
I2C_MODEM 2
wti`_WX
UMTS
PAM
Duplex
UART2 CSI2 I2C3 CAM IF I2C3

UART1
SDIO
NCS
Key
Audio
Subsystem
EAR_MIC
MAX17040
Fuel gauge
Figure. Block Diagram
- 46 -

3. Technical Brief
<Detail 1 : RF Block>
rF Block Diagram
FEM
with
GSM
FSY2_CLK
PAM
VCTCXO
26MHz
SKY77529
XO
VCONT
G850/G900
TX_LB
TX_HB
AFC_DAC
DCS/PCS
DET
W900
Duplexer
RXTX_L2
WCDMA
Dual PAM
ACPM-5281
W2100
Duplexer
RXTX_H
CPL
W1900
Duplexer
RXTX_M1
F26M
SYS_CLK
TX2G_L
TX2G_M
W-PAM
ACPM-5202
CPL
WCDMA
TX SAW
TX_3G_L
WCDMA
TX SAW
TX_3G_H
WCDMA
TX SAW
TX_3G_M
DI3_TX_DAT
DI3_TX_DATX
Di3_TX_DAT
Di3_TX_DATX
DI3_RX_DAT
DI3_RX_DATX
Di3_RX_DAT
Di3_RX_DATX
MP-eHM
transceiver
PMB9801
PMB5703
PWR DET
PA_POW_DET
RFIN1
1900
RX SAW
LNA
RFIN4BGA749

RX_M2X
2100
RX SAW
RX_H
RX
H
~GYXWW
RX_HX
RFIN5
900
RX SAW
RX_L1
~MnG`WW
RX_L1X
RX SAW
RX_L2
nG_\W
RX_L2X
RFIN2
RX_M2
RX_L1
RX_M3
850
1800
RX SAW
RX_M1 nGX_WW
RX_M1X
- 47 -
VDD_MAIN
VDD_FSYS
VDD_IO
2.85V_RF1
2.85V RF2
2.85V_RF2
1.8V_SD
VRF1
VRF2
VSD2

3. Technical Brief
3.9 Subsystem(PMB9801_X-GOLDTM616)
3.9.1 ARM Microprocessor Subsystem
The ARM1176JZ-S incorporates an integer unit that implements the ARM11 ARM architecture v6. The core
supports the 32-bit ARM and 16-bit Thumb instruction sets, Jazelle technology to enable direct execution of Java
byte codes and a range of SIMD DSP instructions that operate on 16-bit or 8bit values in 32-bit registers.
3.9.2 WCDMA Subsystem

The 3.5G cellular modem is implemented as an independent Layer1 subsystem including a separate
microcontroller. The X-GOLDTM616 Modem core acts as a master controlling the 3.5G cellular Modem slave via
the Layer1 host controller interface.
The 3.5G cellular modem consists of a number of superblocks.All higher rate physical layer data connections are
realized by a dedicated bus system using dedicated soft bit RAM (SBRAM) blocks serving as data buffers in
between the inner receiver (IRX) and outer receiver (ORX) peripherals for UMTS and HSDPA demodulation and
channel decoding. The AHB buses are mainly used for configuring the HW peripherals and collection of
measurement results and reportings of the peripherals by the 3G modem controller:
The individual superblocks are:
SB_COM: including
The communication RAM (COMRAM) for HCI command exchange and physical layer data exchange in both
3.5G transmit and receive direction
Buffering of communication flags, implementing the notification mechanism between host and 3G modem
controller based on interrupts in both directions
RLC (radio link control)/MAC (medium access control) accelerators (MACPHY-UL and MACPHY-DL) supporting
the data processing of the Layer 2 protocol stack entities RLC and MAC in both uplink and downlink direction
Access to the crossbar via the 3G_Master interface and the multi master AHB_3G_MASTER bus. The MACPHY
units have master access to the crossbar via the 3G_MASTER master interface. The 3G_Master
interface can also be accessed from the ARM7 via an AHB2AHB bus bridge connected to the AHB_3G_SYS
bus.Simple round robin arbitration of AHB_3G_Master between the three masters is implemented.
Access from the crossbar via the 3G_MACOM slave interface
Access from the 3G modem controller subsystem via the 3G_MEMIF bus
- 48 -

3. Technical Brief
SB_uC: including
The 3G modem controller subsystem including the AHB_3G_SYS bus, and master interfaces to three
peripheral buses 3G_MEMIF, AHB1_3G_L1 and AHB2_3G_L1
The USIF trace interface
The Mtrace trace interface to the MIPI port
The interrupt control unit ICU
An AHB2AHB bridge connecting the 3G modem controller to the 3G_Master interface via AHB_3G_SYS
SB_TXSR: including
The UMTS cell searcher (SRCH) HW peripheral
The UMTS delay profile estimator (DPE) HW peripheral
The measurement RAM (MRAM) buffering the results of both SRCH and DPE
Access from the 3G modem controller subsystem to MRAM via the 3G_MEMIF bus
Transmit modulator (TxMod) and transmit bit processor (E-TxBitProc) HW peripherals performing transport
channel multiplexing, channel coding and modulation for all uplink data streams. These blocks exchange
data via a dedicated RAM SBRAM-TX
Access to the transport blocks stored in the COMRAM by the E-TxBitProc via the dedicated bus system
Configuration access from the 3G modem controller subsystem via the AHB_3G_L1 AHB bus
SB_RAKE: including
The DSP subsystem performing sub-slot signal processing and control for the Rake and HSDPA-IRX peripherals.
The DSP subsystem is connected to the 3G modem controller via shared memory and interprocess
communication via comunication flags, and to the Rake and HSDPA-IRX peripherals via a dedicated bus
The Rake inner receiver HW peripheral performing demodulation of all UMTS and HSUPA physical channels
Configuration Access from the 3G modem controller subsystem via the AHB_3G_L1 AHB bus
Access to the SBRAM1 performing framewise storage of the demodulated coded composite transport channels
via the dedicated bus system
- 49 -

3. Technical Brief
SB_ORX: including
The SBRAM1 performing framewise storage of the demodulated coded composite transport channels via the
dedicated bus system
The SBRAM2 performing TTI wise storage of the demodulated transport channels via the dedicated bus system
The R99-ORX (Outer Receiver) HW peripheral performing transport channel demultiplexing, de-rate
matching and channel decoding of all UMTS downlink physical channels
Configuration access from the 3G modem controller subsystem via the AHB_3G_L1 AHB bus
Access to write decoded transport
SB_HSDPA: including
The HSDPA-IRX inner receiver HW peripheral performing demodulation of HS-PDSCH and demodulation and
decoding of HS-SCCH HSDPA physical channels
The SBRAM3 performing framewise storage of the demodulated coded composite transport channels via the
dedicated bus system
The SBRAM4 performing TTI wise storage and HARQ (hybrid ARQ) buffering via the dedicated bus system the
HSDPA-ORX (Outer Receiver) HW peripheral performing transport channel demultiplexing, de-rate matching,
HARQ processing and channel decoding of all UMTS downlink physical channels
Configuration Access from the 3G modem controller subsystem via the AHB_3G_L1 AHB bus
Access to write decoded transport blocks into the COMRAM via the dedicated bus system
SB_DIGRF: including
The DigRF interface (compliant with DigRF Interface V3.09), which is used to transfer the complete 3.5G and
2.5G GSMEDGE data and control information for both receive and transmit direction using the DigRF V3.09
packet structures from X-GOLD618 to suitable RF transceiver ICs
Access from AHB_3G_Shared which is a multi master AHB bus shared between host controller and 3G modem
controller. The access must be shared since both controllers need configuration access e.g. for writing control
sequences, and reading status information from the 2G and 3G RF transceivers. Master access from the 3G
modem controller subsystem is provided via an AHB2AHB bridge. Master access from the ARM11 side is
provided via the 3G_MACOM crossbar interface and an AHB2AHB bridge. Simple round robin arbitration of
AHB_3G_Shared is implemented
Access from the 2G side for 2G data read and write access to and from the RF side
- 50 -

3. Technical Brief
Several individual blocks on top level: including

The UMTS System Interface (USI), consisting of the the UMTS Timer used for highly accurate interrupt and
trigger generation for the L1 FW, UMTS HW peripherals, AGC, and the Control Sequencer, used to process
more complex trigger and switching sequences (e.g. typical RF control sequences) which are programmed by
firmware into a sequence RAM. A sequence is started manually or via a trigger signal from the UMTS Timer
The 3G Control Unit (3GCU) consisting of System Control Unit (3G-SCU), System Power Control Unit (3GSPCU)
and Clock Generation Unit (3G-CGU) for the 3.5G subsystem.The 3GCU is responsible for the control of the 3G
subsystem. It is tightly coupled to the Master Chip Control Functions of the 2G subsystem in the X-GOLD618.
- 51 -

3. Technical Brief
WCDMA
3GPP WCDMA FDD Multimode Type II UE Protocol Stack
Configurable for data classes up to 384 Kbit/s
Inter-RAT Handover and Cell Reselection.
Supports two types of Compressed Mode.
Network Assisted Cell Change from UTRAN to GERAN and GERAN to UTRAN.
Conforms with ETSI UICC Specifications.
SIM/USIM support.
A-GPS support.
CS Data (transparent/non transparent up to 64kBit/s; Support for Video Telephony)
Release 5 - HSDPA
High Speed Downlink Packet Access (HSDPA)
Compliant with 3GPP Release 5.
Supporting HSDPA Category 8, up to 7.2Mbps.
IPv6 support.
Release 6 - HSUPA
High Speed Uplink Packet Access (HSUPA)
Compliant with 3GPP Release 6.
Supporting HSUPA category 6, up to 5.8Mps.
Robust Header Compression (RoHC).
Fractional DPCH.
WB-AMR Support.
- 52 -

3. Technical Brief
3.9.3 GSM Subsystem

The X-GOLDTM616 is suited for mobile stateons operating in the GSM850/900/1800/1900 band. In the receiver
path the antenna input signal is converted to the base band, filtered, and amplified to target level by the RF
transceiver chip set. Tne modem processor performs for both, GMSK and 8-PSK, the complex baseband signal
equalization with soft-output recovery and the channel decoding supported by a Viterbi hardware accelerator.
RMS calculation for field strength measurements (monitoring)
Detection and evaluation of frequency correction bursts (FCB)
Equalization of GMSK and 8PSK normal bursts as well as synchronization bursts with bit-by-bit soft output.
Single Antenna Interference Cancellation (SAIC) for GMSK and 8PSK channels.
Channel encoding and soft-decision channel decoding for all supported GSM/GPRS/EDGE speech,
data and control channels
Synchonization channel (SCH) and control channels including RACH and PRACH
FR, HR, EFR speech channels (TCH/FS, TCH/HS, TCH/EFS)
NAMR/WAMR speech channels over GMSK and 8PSK
Mandatory sub-functions for speech channels:
Discontinous transmission (DTX)
Voice activity detection (VAD)
Background noise calculation
Fullrate and halfrate data channels (F14.4, F9.6, F4.8, F2.4, H4.8, H2.4)
GPRS class 33 support for coding schemes CS1..CS4
Fast USF detection algorithm for MAC layer
EGPRS class 33 support for modulation and coding schemes MSC1..MSC9
Incremental redundancy (ARQ2) for EGPRS
Dual transfer mode (DTM) class 33
- 53 -

3. Technical Brief
GSM/GPRS/EDGE
Supports GSM, GPRS and EDGE up to Class 33.
EDGE Coding Schemes MCS1 to 9.
CSD
R4 GERAN Feature Package 1
SAIC / DARP
Repeated FACCH and repeated SACCH
A-GPS Support
Support for WB-AMR
GPRS ROHC
- 54 -

3. Technical Brief
The Equalizer Accelerator is used to speed up the viterbi trellis search in the equalizer
The Channel Decoder Accelerator is used to speed up the viterbi trellis search in the channel decoder
The DigRF RX block is the interface for receiving samples from the RF
The DifRF TX block is the interface for transmitting samples to the RF
The GSM Cipher is used for encrypting and decrypting data in circuit switched calls
The IR memory is needed for storing incremental redundancy data in a EGPRS call
The shared memory is used to exchange data and control information between DSP and ARM
The AFC is used for controlling the (external) VCXO in the frequency control loop
The GSM system interface is used to program the timing of all GSM related signals
The GPRS GEA Kasumi is used for encrypting and decrypting data in packet switched calls
The USIM is the SIM card interface
3.9.4 RF Interface
The RF interface communicates with the mobile stations external RF and analog baseband circuits. Signals to
these circuits control signal gain in the Rx and Tx signal path and maintain The systems frequency reference.
3.9.5 SPI based IPC

The XMM6160 platform supports the serial connection via SPI. The command flow of the IPC is independent
from the HW solution and the IPC protocol. It is implemented using a logical channel multiplexer and AT
commands.
The IPC hardware interface consists of a serial SPI interface and two control signals, and one additional optional
control signal. The SPI is implemented using the USIF2 of the X-GOLD616, with the GPIOs implementing sleep
mode and readiness handling
- 55 -

3. Technical Brief
3.9.6 Audio function

Audio Processing on ARM Core
The ARM1176 core is mainly in charge of audio application tasks, including audio playback, audio streaming
and audio recording if required. This implies the usage of codec algorithms such as MP3, WMA, AAC etc., which
must be implemented as decoder and/or encoder software on the ARM core. Decoded audio streams are
transmitted as PCM samples to the DSP core via a shared memory. Audio streams to be encoded are transmitted
by the DSP to the ARM core via a shared memory. The ARM can also generate ring tones and service tones to
notify an incoming call, an incoming message or any audio notification of a phones event (warning, error,
confirmation, battery low, etc.). Another activity on the audio side for the ARM is the streaming of compressed
audio data over the UART interface to the Bluetooth chip for A2DP usage (Advanced Audio Distribution Profile:
audio playback over Bluetooth). Via the same interface it communicates with the Bluetooth chip (this is not
restricted to audio activities). The ARM core is managing the configuration of the AFE by sending commands to
the DSP over shared memory to activate various configurations of the AFE. Note that the activities of the ARM
remain purely digital audio processing.
Audio Processing on DSP Core

The DSP core is in charge of speech audio and mixing tasks and its activities remain - as the ARM - purely
digital audio. The DSP can also execute some audio application tasks. It ensures the simultaneous encoding
and decoding of speech audio frames during telephone conversation. It uses different sets of vocoders as
specified by the applicable standards for the ongoing telephone conversation. On the audio out path (i.e.
towards the speaker) it mixes audio application received over shared memory with decoded speech audio. On
this path it can also mix some audio samples coming from the microphone to enable the feedback loop to the
speaker (Sidetone generation, as specified in 3GPP/ TS 43.050, chapter 3.10). On the audio in path (i.e. from the
microphone to the transmission of the encoded audio samples over the air) the DSP can also mix speech audio
samples with any other digital audio source and analogue FM radio as well. The mixing capabilities are
extremely broad as the cases mentioned above are only examples. These mixing capabilities also include the
ability to execute a sample rate conversion to bring all samples to the same rate before
mixing. The DSP also can execute some audio application tasks such as PCM, ADPCM, SB-ADPCM audio playback
and recording. Simple Tone (sine tones, DTMF, key click) can be generated as well.
The next activity of the DSP is transferring data to and from the hardware peripherals (AFE, I2S0 and I2S1).
Asmentioned in Figure 1 a fifo buffer is used to exchange stereo audio samples between the DSP and the AFE
on the microphone path and speaker path. When receiving a command from the ARM the DSP directly
configures the different modes of the AFE. The DSP also manages the I2S interfaces I2S0 and I2S1. I2S0 interface,
configured as master interface, is used to exchange speech audio samples at a rate of 8 or 16 kHz mono on both
directions with the Bluetooth chip in the case of a speech call using a Bluetooth headset. The I2S1 interface can
be used as slave or master interface, enabling the exchange of audio stereo samples at any common rate
between 8 and 48 kHz, potentially asymmetrically between RX and TX. This is to act as an audio bridge with an
external audio chip (application processor, audio processor,etc.). Note that the activities of the DSP - like the
ARM - remain purely digital audio processing. Refer to the document system requirements specification for
more details on the different audio application features supported by the chip.
- 56 -

3. Technical Brief
Audio Processing on Audio Front End

The AFE is used as a playback and capture device, i.e. exchanging digital audio stereo samples on both
directions (from microphone to DSP and from ARM/DSP to speaker). On audio-in path analog to digital
conversion and amplification is executed. On the audio-out path digital to analog conversion and power
amplification is performed. Additionally, the AFE physically selects the correct audio analog paths and is directly
managing the analog inputs and outputs.
3.9.7. Vocoder Subsystem

FR, HR, EFR speech channels (TCH/FS, TCH/HS, TCH/EFS)
NAMR/WAMR speech channels over GMSK and 8PSK
Mandatory sub-functions for speech channels:
Discontinous transmission (DTX)
Voice activity detection (VAD)
Background noise calculation
Fullrate and halfrate data channels (F14.4, F9.6, F4.8, F2.4, H4.8, H2.4)
3.9.8 Memory Subsystem

The X-GOLD616 can use the general term SDRAM as a shortcut for Mobile DDR SDRAM. A total of up to four
external memories is supported, chip selects can be dynamically allocated to one of the two external memory
controllers of X-GOLD616. Only two memory devices can be connected to the SDRAM controller if DDR support
is required.
3.9.9 Battery Management Hardware Configurations

The X-GOLD616 chip has an internal PMU that will provide power supply for the chip itself, memory and the
attached RF. The X-GOLD also holds a measurement unit that can perform all necessary battery measurements
through external HW. This is sufficient for a modem only design where charging is controlled by another chip
3.9.10 General-Purpose Input/Output Interface

The X-GOLD616 chip has an internal PMU that will provide power supply for the chip itself, memory and the
attached RF. The X-GOLD also holds a measurement unit that can perform all necessary battery measurements
through external HW. This is sufficient for a modem only design where charging is controlled by another chip
- 57 -

3. Technical Brief
3.9.11 Clocking
The clocking system is based on 2 different clocks, a 26 MHz reference clock generated within the RF Engine and
a 32 kHz real-time clock (RTC) generated in the baseband.The 26 MHz clock provided by the RF engine is the
main reference clock for the RF circuit and the X-GOLD616. Also other system components may be supplied
with 26 MHz reference clocks. A 32 kHz oscillator located at the X-GOLD616 supplies the RTC with the reference
clock for the real time clock application, as well as provides a low power standby clock for system sleep mode
operation. This clock is available
also for other system components like GPS.
3.9.12 USB
The XMM6160 platform provides two USB interfaces compliant to the USB2.0 standard:
High speed interface (480 Mbps) for communication with external devices acting both as host or device
Full speed interface (12 Mbps) for communication with the UICC using the IC-USB standard acting as host
The USB solution is based on USB controller hardware IP, which is integrated in the X-GOLD616 baseband chip including
both USB transceivers for high and full speed and the USB Stack software that implements the different USB device classes
and features.
The HS OTG USB component supports the following features:
Modem connection for DialUp Networking and AT command interface (CDC-ACM)
Tracing over USB (CDC-ACM)
Suspend/Resume and Remote Wakeup (for power saving)
Software download
Optional features (not included in the XMM6160 platform):
Support for isochronous transfers
The IC-USB component supports the following features:
UICC-Terminal USB interface according to ETSI TS 102 600 (ICCD only)
Suspend/Resume and Remote Wakeup (for power saving)
- 58 -

3. Technical Brief
3.10 Power Block

3.10.1 General
Since P970 uses two individual chips, XMM6160 (IFX Modem) uses integrated PMIC and OMAP3630 uses
TWL5034 as a main PMIC.
3.10.2 XMM6160 (IFX Modem)

X-GOLD616 is a single integrated circuit UMTS/GPRS/EDGE Baseband Controller with integrated mixed signal
and measurement subsystem and modem power management unit. This system on chip designed in
Poweraudio
Block
Diagram (CP)
Infineons low power 65nm CMOS process technology provides the performance to meet the ever increasing
demands of the cellular subscriber market for feature rich terminals at lowest power consumption and a very
competitive cost position.
PMB9801
vSD1
vSD1 1.3v_Core(450mA)
vDD Core
vDD_Core
(450mA)
1.8v_SD(450mA)
vSD2
vSD2
(4450mA
1.35v_PLL(30mA)
vDD_vPLL)
vANA2
vMiPi
vDD_vrtC
vDD_vUSB
vDD_DiG / MeM
vDD_LvDS
2.5v_ANA2(70mA)
vDD_MiPi_BGC
1.2v_MiPi(60mA)
vDD_MiPi
2.3v_rtC(7mA)
vDD_rtC
3.1v_USB(40mA)
vDD_USB
PMB9801
vrF1
vrF2
2.85v_rF1(180mA)
vDD_MAiN
2.85v_rF2(60mA)
vDD_FSYS
vDD_vAr
PMB5703
vDD_vPMU
vANA1
vDD vSiM
vDD_vSiM
MEMORY
vBAt
(for Infineon)
1G / 512Mb
2 85v SiM
2.85v_SiM
USIM For Infineon
(7mA)
Figure. LGP970 Modem Power Block Diagram
- 59 -

3. Technical Brief
3.10.3 TWL5034
The TWL5034 is an integrated power management for mobile devices that use the OMAPs application
processors (AP), or other similar application processors. The TWL5034 includes three high efficiency step-down
regulators and 17 LDOs to power the application processor, internal Logic, I/O, memory, and system accessories.
An additional the device provides LED driver circuitry to power two LED circuits(LED A,LEDB)
that can illuminate a panel or provide user indicators. The LED A can provide up to 160 mA and the
LED B, 50 mA. Each LED circuit is independently controllable for basic power (on/off) control and
illumination level (using PWM).
OJS<:3#V|vwhp#Eorfn#Gldjudp#+whw,
vDD1_Core [1.4A] 1.2v
vDD1_SW_01~03, vDD1_FB
Backup
BATT
vDDS_CSi2
oMAP3630
1.8v_MMC_eN [100mA]
vMMC2_oUt
26MHz
HF_CLKiN
PMB9801
vDDS_DPLL_Per/DLL
1.8v_CSi2 [100mA]
vAUX4_oUt
[5mA Max]
vDDS_MMC1
1.8v_PLL1 [40mA]
vPLL1_oUt
1.8v_vio
vDD_Core (Max 1.6v)
1.8v_vio [600mA]
vio
BKBAt
vDD_MPU_ivA (Max1.6v)
vDD2_Core [600mA] 1.0v
vDD2_SW_01,02, vDD2_FB
1"$5
LDo
vBAt
(NLSv2t244)
ProXiMitY
2.8v_ProXi [200mA]
vAUX1_oUt
(GP2AP002S00F)
vt_CAM_Drv_2.8v [220mA]
vMMC1_oUt
vt CAM
vt_CAM_io_1.8v [200mA]
vAUX3_oUt
vAUX2_oUt
vDAC_oUt
vBUS
eMMC
(SDiN5D2-2G)
LeveL SHiFter
tWL5034
CSC3M260000BFvrS00
2.3v_rtC
vSiM_oUt
(vPLL2)vSDi_CSi_oUt
3.0v_MotioN [100mA]
LDoA
LDoB
LDoC
LDoD
SUB PMIC
CAM POWER
(LP8720)
SW
LDo3
LDo4
Micro USB
LDo5
SUB
1.8v_WLAN [50mA]
GYro (MPU3050A)
1.8v_AUDioAMP[100mA]
CoMPASS
LeD1~8
vt
Motion (KXtF9)
1.8v_MotioN_vio [65mA]
vBAt
LCD BL
CHG PUMP
(AAT2870)
vt
LCD_BL_oUt[1:8]
SUB
(AK8975C)
SUB
WLAN+Bt+FM CoB
1.8v_LCD_iovCC (300mA)
(BCM43291SKUBG)
4.0 LCD
3.0v_LCD_vCC_vCi (150mA)
WM9093
1.8v_toUCH(150mA)
3.0v_toUCH (150mA)
TOUCH
FLASH LeD Driver
1.2v_5M_vDiG (400mA)
(rt8515)
2.7v_5M_vANA(300mA)
5M CAM
1.8v_5M_vio(300mA)
SUB
DP3t S/W (FSUSB63)
2.8v_5M_vCM (300mA)
LDo1
3.0v_MMC (300mA)
LDo2
3.0v_Motor (300mA)
MiCro SD
SUB
CArD_DeteCt : 1.8v_vio
iNt : 1.8v_vio
Motor Driver
FUeL GAUGe
vBAt
(MAX17043)
(iSA1000)
vCHG
Charging IC
RT9524
USB_vBUS[4.9v, 60mA]
vBAt
MUiC
Battery
iNt : 1.8v_vio
(MAX14526DeeWP)
1500mA/h
CHGSB : 1.8v_vio
Figure. TWL5034 functional block diagram
- 60 -

3. Technical Brief
3.10.3 Charging control

P970 uses individual Charger IC which is RT9524.
Features
28V Maximum Rating for DC Adapter
Internal Integrated Power MOSFETs
Support 4.2V/2.3A Factory Mode
50mA Low Dropout Voltage Regulator
Status Pin Indicator
Programmed Charging Current
Under Voltage Lockout
Over Voltage Protection
Thermal Feedback Optimized Charge Rate
RoHS Compliant and Halogen Free
- 61 -

3. Technical Brief
3.10.3.2 Constant Current Charging

Battery Pre-Charge Current
During a charge cycle, if the battery voltage is below the pre-charge threshold, the RT9524 enters the Pre-charge
mode. This feature revives deeply discharged cells and protects battery. Under USB100 Mode, the pre-charge
current is internally set to 95mA. When the RT9524 is under USB500 and ISET Mode, the pre-charge current is
20% of fast-charge current set by external resistor RISET.
Battery Fast-Charge Current
ISET Mode
The RT9524 offers ISET pin to program the charge current. The resistor RISET is connected to ISET and GND. The
parameter KISET is specified in the specification table.
- 62 -

3. Technical Brief
Battery Voltage Regulation (CV Mode)

The battery voltage regulation feedback is through the BATT pin. The RT9524 monitors the battery voltage
between BATT and GND pins. When the battery voltage closes in on the battery regulation voltage threshold,
the voltage regulation phase begins and the charging current begins to taper down. When the charging current
falls below the programmed end-of-charge current threshold, the CHGSB pin goes high to indicate the
termination of charge cycle. The end-of-charge current threshold is set by the IEOC pin. The resistor REOC is
connected to IEOC and GND. The parameters KEOC and IEOC are specified in the specification table.
The current threshold of IEOC (%) is defined as the percentage of fast-charge current set by RISET. After the
CHGSB pin is pulled high, the RT9524 still monitors the battery voltage. Charge current is resumed when the
battery voltage goes to lower than the battery regulation voltage threshold.
3.10.3.3 Constant Voltage Charging

Constant voltage charging begins when the battery voltage reaches a target voltage, 4.2V. The end of constant
voltage charging is commonly detected around 240mA from Travel adaptor.
3.10.3.4 LGP970 Charging Specification

-Charging Method : CC & CV (Constant Current & Constant Voltage)
-Maximum Charging Voltage : 4.2V
-Maximum Charging Current : 946mA
-Nominal Battery Capacity : 1500mAh
-Charging time : Max. 3h 30m
- Full charge indication current (icon stop current) : 156mA
- 63 -

3. Technical Brief
3.10.3.5 LGP970 battery bar icon display

Battery Bar Number
Specification
BAR 6 (Full)
90% over
BAR 6 --> 5
90% 89%
BAR 5 --> 4
70% 69%
BAR 4 --> 3
50% 49%
BAR 3 --> 2
30% 29%
BAR 2 --> 1
15% 14%
BAR 1 --> 0
5% 4%
Low Battery Pop-up
4% ~ 15% : One Time popup
Critical Low Battery Pop-up
0% ~ 3% : Popup at every level change
POWER OFF
0%
Remain %
Table. LGP970 battery bar specification
- 64 -

3. Technical Brief
3.11 External memory interface

3.11.1 Introduction
Since LGP970 contains communication and application processor, memory is dedicated only for each processor.
XMM6160 (IFX modem) uses MCP (Multi Chip Package) 1Gb nand / 512Mb LPDDR1 and AP20 uses POP (Package
on Package) 512MB LPDDR1 and 2GB eMMC nand memory.
3.11.2 LGP970 XMM6160 (IFX Modem) memory Interface

-Multi Chip Package : DDR SDRAM and NAND Flash merged 1 package
-512Mbit Mobile DDR SDRAM / 1Gbit NAND Flash
Interface Spec
Part Name
H8BCS0QG0MMR46M
Product Gr
Maker
Operation Voltage
Speed
NAND
Hynix
1.8V
45ns
1.8V
166MHz
SDRAM
3.11.3 LGP970 OMAP3630 memory Interface

- Package on Package on OMAP3630: LPDDR1 512MB SDRAM
- 8GB eMMC 4.4 version
LPDDR1 SDRAM
Interface Spec
Part Name
H8MBX00U0MER-0EM
Product Gr
Maker
Operation Voltage
Speed
SDRAM
Hynix
1.8V/1.2/1.2/1.2
DDR1 400
(200MHz)
8GB NAND
Interface Spec
Part Name
Product Gr
Maker
Operation Voltage
Speed
SDIN5D2-2G
NAND
Sandisk
3.3V
15MB/s for read

9MB/s for write
3.11.4. External SD card memory Interface

TI OMAP3630 supports external SD card which supports up to 32GB (SDHC compatible)
- 65 -

3. Technical Brief
3.12 H/W Sub System

3.12.1 RF Interface
The base band is connected via a DigRF high speed data interface with a maximum clock frequency of 312 MHz.
The pure digital interface enables the digital baseband to shrink efficiently, as all the analog functionality is
within the RFIC. All data and control traffic is multiplexed via the RX and TX interface lines. The IC features a high
level programming model enabling the complete compressed mode operation of the device in an RF engine
environment. It handles RX and TX power control, also incorporating the calibration data.
The complete timing is optimized for compressed mode operation of the transceiver, it controls the front end
components of the engine (PAs, switches, LNAs). Additionally a SPI control bus for front end component
control is available in the IC, which also enables the readback of data from external components, thus the
handling of functions like PA saturation, mismatch detection, overheating (incorporated in the closed loop
power control) can be adopted.
3.12.1.1 DigiRF Interface

- RESET_N : RESET Input Signal for master reset
- ALERT_N : 3G PLL Lock Status Output Signal
- SYS_CLK : 3G DigRF System Clock Output
- DI3_TX_DAT, DI3_TX_DATX : 3G DigRF TX Input Data (Positive / Negative)
- DI3_RX_DAT, DI3_RX_DATX : 3G DigRF RX Input Data (Positive / Negative)
3.12.1.2 About Clock

- REF_CLK_EN, SYS_CLK_EN, FSYS2_EN, FSYS3_EN
- AFC_DAC : AFC DAC Output; analog output: 12 bits
- XO_SUP : Supply Voltage Output for TCVCXO
- SYS_CLK : 3G DigRF System Clock Output
- FSYS2, FSYS3, FSYS4 : 26 MHz Reference Clock Output
3.12.1.3 General Control Logic Signals

- PA Control Outputs
PA_EN1, PA_EN2, PA_EN3, PA_EN4 : PA Control Output
PA_BSEL : PA Band Select Control Output
PA_MODE : PA Mode Select Control Output
PA_RAMP : PA Ramping Voltage for GMSK and 8-PSK; analog output: 11 bits
PA_BIAS: PA Bias Voltage PA_POW_DET
- Frontend Control
FE_CTRL1~6 : Front-end Control Output
SPI(SPI_CLK, SPI_SS, SPI_DRW) : FEM Control Interface
- LNA Control
LNA_CTRL1, LNA_CTRL2, LNA_CTRL3, LNA_CTRL4 : LNA Control Output
- 66 -

3. Technical Brief
rF Block Diagram
FEM
with
GSM
FSY2_CLK
PAM
VCTCXO
26MHz
SKY77529
XO
VCONT
G850/G900
TX_LB
TX_HB
AFC_DAC
DCS/PCS
DET
W900
Duplexer
RXTX_L2
WCDMA
Dual PAM
ACPM-5281
W2100
Duplexer
RXTX_H
CPL
W1900
Duplexer
RXTX_M1
F26M
SYS_CLK
TX2G_L
TX2G_M
W-PAM
ACPM-5202
CPL
WCDMA
TX SAW
TX_3G_L
WCDMA
TX SAW
TX_3G_H
WCDMA
TX SAW
TX_3G_M
DI3_TX_DAT
DI3_TX_DATX
Di3_TX_DAT
Di3_TX_DATX
DI3_RX_DAT
DI3_RX_DATX
Di3_RX_DAT
Di3_RX_DATX
MP-eHM
transceiver
PMB9801
PMB5703
PWR DET
PA_POW_DET
RFIN1
1900
RX SAW
LNA
RFIN4BGA749

RX_M2X
2100
RX SAW
RX_H
RX
H
~GYXWW
RX_HX
RFIN5
900
RX SAW
RX_L1
~MnG`WW
RX_L1X
RX SAW
RX_L2
nG_\W
RX_L2X
RFIN2
RX_M2
RX_L1
RX_M3
850
1800
RX SAW
VDD_MAIN
VDD_FSYS
RX_M1 nGX_WW
RX_M1X
VDD_IO
2.85V_RF1
2.85V RF2
2.85V_RF2
1.8V_SD
VRF1
VRF2
VSD2
Figure. RF Interface Block Diagram
- 67 -

3. Technical Brief
3.12.1.4 BCM43291SKUBG (BT / WiFi / FM module )

3.12.1.4.1 WiFi
* WLAN_CMD : WLAN SDIO Command Line.
* WLAN_CLK : WLAN SDIO Clock Input.
* WLAN_SDIO[3:0] : WLAN SDIO Data Line.
* WLAN_RESET_N : Low asserting reset for WLAN core.
* WLAN_HOST_WAKEUP : WL_HOST_WAKEUP signal output.
3.12.1.4.2 BT
* BT_UART_RXD : Bluetooth UART Serial Input.
* BT_UART_RTS : Bluetooth UART Request to Send. Active-low request.
* BT_UART_CTS : Bluetooth UART Clear to Send. Active-low clear.
* BT_UART_TXD : Bluetooth UART Serial Output.
* BT_PCM_CLK : BT PCM clock, can be PCM-master (output) or PCM-slave (input).
* BT_PCM_DIN : BT PCM data input.
* BT_PCM_SYNC : BT PCM sync signal, can be PCM-master (output) or PCM-slave (input).
* BT_PCM_OUT : BT PCM data output.
* BT_WAKEUP : BT Wakeup Input.
* BT_HOST_WAKEUP : BT Host Wakeup Output
* BT_RESET_N : Low asserting reset for BT core.
3.12.1.4.3 FM Radio
* FM_ANT : FM RF input.
* SLEEP CLK : External reference oscillator input. (32.768KHz)
* FM_R : Right audio line output digital input data.
* FM_L : Left audio line output digital frame synchronization.
* BT_PCMS : Also Using Control of FM Radio
3.12.1.4.4 Common
* WLAN_REG_ON : If low the internal regulators will be disabled.
* SLEEP_CLK : LPO clock (32.768kHz) input. Used for low-power mode timing.
* CLK_IN : Crystal amplifier input or frequency reference input.
* CLK_REQ : Crystal Circuit / Reference Clock Enable (active-high)
- 68 -

3. Technical Brief
Figure. Wifi/BT/FM Interface Block Diagram
- 69 -

3. Technical Brief
3.12.1.5 BCM4751 (GPS module )

- GPS_UART_RXD : Host UART transport data receive
- GPS_UART_TXD : Host UART transport data transmit. (100K pull-up is needed)
- GPS_UART_CTS_N : UART clear to send
- GPS_UART_RTS_N : UART request to send
- 26MHz_GPS_REF : Calibration clock
_ GPS_26MHz : 26MHz TCXO input
_ CLK32K_TWL : Sleep clock
- GPS_GSM_CTL : Transmit blanking signal
_ GPS_RESET_N : Reset
- GPS PWR_ON : Used as a control signal for enabling Deep Sleep mode.
Figure. GPS Interface Block Diagram
- 70 -

3. Technical Brief
TI Confidential NDA Restrictions
3.12.2 OMAP Sub System
onment
www.ti
3.12.2.1 OMAP environment

Figure 1-1. oMAP3630 High-tier environment
CONNECTOR
JTAG
POP device
SDRC
CDC3S04
NAND SLC/MLC
25ns R/W, 16-bit
Quad Sine-Wave
Clock Buffer
GPMC
NC
AR
Y
DDR
200MHz, 2CS
32bit
Mobile TV
LR 5Mpx
SMIA CCP2
HR 8Mpx
MIPI CSI2
I2C3
LENS
IRIS
MOTOR
CAM ISP
FLASH
CSI2
McSPI2
UART1
CCPV2
or CSI1/2
Camera subsystem
USB3
DV
SDMMC1
OMAP3630
Mass storage media

(eMMC, CE-ATA, JC64)
USB1
EL
IM
IN
LS
3D accelerometer
FingerPrint
TI WL128x
WLAN-BT/FM-GPS
FM 76-108 MHz
SDMMC2
SDMMC3
UART3
Electronic compass
UART2
Cellular
subsystem
HDQ or
UART4
McBSP3
McSPI1
DSS
DSI
I2C2
HSUSB0
CVIDEO
I2C4/SR
McBSP2
I2C1
Main display
WVGA
TWL50xx
S-VIDEO Y/C
TI TSC200x
Touchscreen controller
*
7
4
1
Subdisplay
VGA
0
8
5
2
#
9
6
3
Introduction
PR
Display subsystem
intro_177-001
SWPU176A October
- 71 -

3. Technical Brief
3.12.2.2 Memory
Micro processor unit has a 32 bit address portTI, allowing
it to
a 4 GB space divided into several regions.
Confidential
handle
NDA Restrictions
The Memory map is composed of a memory space and dedicated space Interconnect of the devices and the main
modules and subsystems in the platform.
Introduction
www.ti.com
Figure 2-1. interconnect overview
MPU
subsystem
SGX
IVA2.2
subsystem
Display
subsystem
sDMA
L4
Camera
ISP
L4
L3 interconnect
OCM
ROM
SDRC: SDRAM
memory
controller
Stacked memories
L4 interconnect (peripheral)
USB
HS-OTG
L4
USB
HS-HOST
L4
GPMC: generalpurpose memory

controller
UART3, UART4, McBSP2, McBSP3, McBSP4,

WDT3, GPTIMER2, GPTIMER3,
GPTIMER4,GPTIMER5, GPTIMER6,
GPTIMER7, GPTIMER8, GPTIMER9, GPIO2,
GPIO3, GPIO4, GPIO5, GPIO6
DAP
D2D
L4
L4
L4 interconnect (core)
EL
IM
IN
OCM
RAM
SMS: SDRAM
memory
scheduler /
rotation
AR
Y
External peripherals ports
SCM, CM, display SS, sDMA, USB TLL,

HS USB Host, I2C1, I2C2, I2C3, UART1,
UART2, McBSP1, McBSP5, GPTIMER10,
GPTIMER11, Mailbox, McSPI1,
McSPI2, McSPI3, McSPI4,
MMC/SD/SDIO1, MMC/SD/SDIO2,
MMC/SD/SDIO3, HDQ/1-Wire,
ICR, camera ISP, MODEM, HS USB OTG
INTC, SR1, SR2, MPU INTC
L4 interconnect
(emulation)
Emulation, trace, and

debug modules
External and stacked memories
L4 interconnect (wake-up)
GPTIMER1, WDT2,
GPIO1, 32KTIMER
SWPU176A October 2009
PR
External peripherals ports

memmap-001
Memory Mapping
- 72 -

203
3. Technical Brief
3.12.2.3 Power Management

SmarReflex is a power management technique for controlling the operating voltage of a device to reduce its active
power consumption.
Power IC
Device
VDD
SMPS
SR_MPU interrupt
MPU INTC
VP_MPU interrupt
Voltage command
Voltage processor
Acknowledge
Voltage
controller
IC
interface
CLK
DATA
IC
interface
Control
SR_VP interrupt
Error
Interrupt clear
SmartReflex functional clock
SmartReflex
PRM
PRCM
- 73 -

3. Technical Brief
3.12.2.4 Camera ISP

The camera ISP is a key component for imaging and video applications such as video preview, video record , and still
Camera ISP Overview
www.ti.com
image capture with or without digital zooming.

Figure 6-1. Camera iSP overview Diagram
Device
cam_hs
AR
Y
cam_vs
Camera
ISP
cam_fld
cam_wen
cam_xclka
cam_xclkb
CPI
cam_pclk
EL
IM
IN
L4
interconnect
CSI2A
MPU
subsystem
CSIPHY2
L3
interconnect
IVA2.2
subsystem
CAM_IRQ1
INTC
CSI1 / CCP2B
CAM_IRQ0
INTC
PR
STANDBY
hardware
handshake
CSI2C
PRCM
CSIPHY1
CAM_MCLK
CAM_ICLK
CAM_FCLK
CSI2_96M__FCLK
cam_d[11:10]
(2)
cam_d[5:2]
(2)
csi2_dx0 / ccpv2_dx0
(1)(2)
csi2_dy0 / ccpv2_dy0
(1)(2)
csi2_dx1 / ccpv2_dx1
(1)(2)
csi2_dy1 / ccpv2_dy1
(1)(2)
csi2_dx2 / cam_d[1]
(1)(2)
csi2_dy2 / cam_d[0]
(1)(2)
csi2_dx0 / ccpv2_dx0 / cam_d[6]
(1)(2)
csi2_dy0 / ccpv2_dy0 / cam_d[7]
(1)(2)
csi2_dx1 / ccpv2_dx1 / cam_d[8]
(1)(2)
csi2_dy1 / ccpv2_dy1 / cam_d[9]
(1)(2)
cam_strobe
cam_global_reset
cam_shutter
Legend:
CPI input when PHYs configured in GPI mode(cam_d signals)

Serial-to-Parallel converted data stream
camisp-001
(1)
The mode for each PHY can be selected from CSI2, CSI1/CCP2B, and GPI at
SCM.CONTROL_CAMERA_PHY_CTRL register. It can also control the connection between one of the
PHY's and CSI1/CCP2B receiver via multiplexing.
(2)
There is no top-level muxmode (padconf SCM register) control bit for the different camera modes supported
by the interfaces. If one or another of the interfaces is enabled, then the camera input signals will be
automatically routed to the corresponding ISP receiver depending on the PHY operating mode settings
(SCM.CONTROL_CAMERA_PHY_CTRL register)
- 74 -

3. Technical Brief
3.12.2.5 Display
The display subsystem provides the logic to display a video frame from the memory frame buffer on a liquid crystal
Display Subsystem Overview
www.ti.com
display
panel or TV set.
Figure 7-1. Display Subsystem Highlight

Device
Display subsystem
L4 interconnect
Remote
frame buffer
interface
DSI1_PLL_FCLK
DSI2_PLL_FCLK
DSS_LINE_TRIGGER
DSS_DMA_REQ[3:0]
dss_acbias
DSS_DATA[17:6]
dss_data[17:6]
DSS_IRQ
DSS_DATA[23:18]
Display
controller
EL
IM
IN
dss_data[23:18]
TV out
encoder
TVINT
GPIO2
Composite/Luma
Digital data
IVA2.2
subsystem
interrupt
controller
dss_hsync
DSS_ACBIAS
DSS_L3_ICLK
DSS_L4_ICLK
DSS1_ALWON_FCLK
DSS2_ALWON_FCLK
DSS_96M_FCLK
DSS_TV_FCLK
Pin multiplexing
96-MHz clock
54-MHz clock
MPU
subsystem
interrupt
controller
dss_vsync
AR
Y
L3 clock
L4 clock
Functional clock1
Functional clock2
System DMA
controller
(sDMA)
dss_pclk
DSS_HSYNC
L3 interconnect
PRCM
DSS_PCLK
DSS_VSYNC
24
Chroma
TV syncs
Video DAC
stage
System
control
module
cvideo1_out
cvideo2_out
cvideo1_vfb
cvideo2_vfb
cvideo1_rset
TVACEN
vdda_dac
TVOUTBYPASS
vssa_dac
COMP_EN
Syncs
DSI
protocol
engine
Data
PR
Controls
Note:
DSI
PLL
controller
DSI_DX0
DSI_DY0
DSI_DX1
DSI_DY1
DSI_DX2
DSI_DY2
Status
Pin multiplexing
DSS_DATA[5:0]
DSI
complex I/O
dss_data[0]/dsi_dx0
dss_data[1]/dsi_dy0
dss_data[2]/dsi_dx1
dss_data[3]/dsi_dy1
dss_data[4]/dsi_dx2
dss_data[5]/dsi_dy2
vdds_dsi
vdd_dsi
vss_dsi
DSI PLL
PLL control
HS divider
dss-001
For more information about connecting the LOCK, RECAL, and TVINT signals through the
GPIO2 and GPIO3 modules, see Chapter 25, GPIO.
The display subsystem includes the following main features:

Display controller
Display modes
Programmable pixel display modes (1,
24 bits-per-pixel
[BPP]
Copyright
2011 LG Electronics.
Inc.modes)
All right reserved.
- 752,- 4, 8, 12, 16, and
Programmable display size supported:
XGA - 1024 x 768 VESA timings at 60 fps (pixel clock = 63.5 MHz)
3. Technical Brief
HS I2C Functional Description
www.ti.com
17.4 HS i2C Functional Description

17.4.1
HSI2C
I2C Block Diagram
3.12.2.6
AR
Y
17-21 isfour
a functional
block
of the
HS I2Ccircuit
controllers.
TheFigure
device contains
multimaster
highdiagram
speed inter
integrated
controllers.
Figure 17-21. HS i2C Controllers Functional Block Diagram
Device
L4-Core interconnect
I2Ci
I2Ci_IRQ
FIFOs
I2Ci_FCLK
I2Ci_ICLK
PRCM
i2ci_scl
i2ci_sda
i2ci_sccbe
EL
IM
IN
sDMA I2Ci_DMA_TX
controller
I2Ci_DMA_RX
Master/slave
control
Registers
Internal interface
Test
control
I C and SCCB interface
MPU
INTC
Clock/reset
control
I2Ci_RESET
I2Ci_SWAKEUP
Note:
I2C-021
The i2c1_sccbe and i2c4_sccbe signal is not available. The i2c4 does not have SWAKEUP
request. It also gets its RESET signal from the PRCM reset manager.
PR
The three HS I2C controllers can be configured in F/S I2C mode, in HS I2C mode, or in SCCB mode. The
operation mode is selected by configuring the I2Ci.I2C_CON[13:12] OPMODE bit field. Table 17-10 lists
the available operation modes.
table 17-10. HS i2C operation Mode Selection
operation Mode
i2Ci.i2C_CoN[13:12] oPMoDe Bit Field value
F/S I2C
0x0
HS I2C
0x1
SCCB
0x2
Reserved (not used)
0x3
17.4.2 HS I2C Transmit Mode in I2C Mode

This mode is available for master or slave. The master and slave modes are configurable with the
I2Ci.I2C_CON[10] MST bit (0: slave mode; 1: master mode).
In master mode, the transmit mode is configured by setting the I2Ci.I2C_CON[9] TRX bit to 1. The MPU
subsystem puts the data to transmit in the TX FIFO by writing to the I2Ci.I2C_DATA[7:0] DATA bit field.
Use Only
2862LGE Internal
Multimaster
High-Speed I2C Controller
- 76 -
Copyright 2011 LG Electronics.

Inc. All
right
reserved.
SWPU176A
October
2009
UART/IrDA/CIR Overview
www.ti.com
3. Technical Brief
19.1 UArt/irDA/Cir overview
AR
Y
The device contains three universal asynchronous receiver/transmitter (UART) devices controlled by the
microprocessor unit (MPU) (see Figure 19-1):
Three UART-only modules, UART1, UART2 and UART4 are pinned out for use as UART devices only.
UART1 and UART2 must be programmed by setting the UARTi.MDR1_REG[2:0] MODE_SELECT field
to one of the three UART operating modes.
UART3, which adds infrared communication support, is pinned out for use as a UART, infrared data
3.12.2.7 association
UART
(IrDA), or consumer infrared (CIR) device, and can be programmed to any available
operating mode.
The device contains three universal asynchronous receiver/transmitter devices.
Figure 19-1. UArt Module
Device
UART1
(UART)
EL
IM
IN
MPUsubsystem
MPUSSINTC
UART1.IRQ
L4-Core
32
sDMA
UART1.DMA_RX/TX
uart1_tx
uart1_rx
uart1_rts
uart1_cts
32
UART2
(UART)
uart2_tx
UART2.DMA_RX/TX
UART2.IRQ
uart2_rx
uart2_rts
uart2_cts
IVA2.2subsystem
UART3
(UART/IrDa)
IVA2.2SSINTC
UART3.IRQ
eDMA
uart3_rx/uart3_rx_irrx
UART3.DMA_RX/TX
L4-Core
32
PR
uart3_tx/uart3_tx_irtx
32
uart3_rts/uart3_rts_sd
uart3_cts/uart3_cts_rctx
UART4
(UART)
UART4.IRQ
uart4_tx
UART4.DMA_RX/TX
uart4_rx
uart-001
19.1.1 UART Features
The UARTs (UART1, UART2, UART3, UART4 when in UART mode) include the following key features:
16C750 compatibility
64-byte FIFO for receiver and 64-byte FIFO for transmitter
Programmable interrupt trigger levels for FIFOs
Baud generation based on programmable divisors N (N = 1 ... 16,384) operating from a fixed functional
2938
UART/IrDA/CIR
- 77 -

3. Technical Brief

3.12.2.8 McSPI
McSPI Overview
www.ti.com
The multichannel serial port interface is a master/slave synchronous serial bus.

Figure 20-1. Multichannel Modules SPi1, SPi2, SPi3, and SPi4
Device
Multichannel
SPI1 I/F
MPU SS
INT
System
DMA
SPI1_DMA_RX[0,3]
spi1_clk
spi1_simo
spi1_somi
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
SPI1_DMA_TX[0,3]
SPI1_FCLK
SPI1_SWAKEUP
EL
IM
IN
PRCM
SPI1_IRQ
AR
Y
L4 interconnect
L4 interconnect
MPU SS
INT
System DMA
Multichannel
SPIm I/F
m=[2,3]
SPIn_IRQ
spim_clk
spim_simo
spim_somi
spim_cs0
spim_cs1
SPIn_DMA_RX[0,3]
SPIn_DMA_TX[0,3]
PRCM
L4 interconnect
SPIn_FCLK
SPIn_SWAKEUP
Multichannel
SPI4 I/F
MPU SS
PR
INT
System
DMA
PRCM
SPI4_IRQ
spi4_clk
spi4_simo
spi4_somi
spi4_cs0
SPI4_DMA_RX[0]
SPI4_DMA_TX[0]
SPI4_FCLK
SPI4_SWAKEUP
mcspi-001
The McSPI instances include the following main features:

Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths ranging from 4 bits to 32 bits
Up to four master channels or single channel in slave mode
LGEInternal
Use Only
- 78 Master
multichannel mode:
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
3. Technical Brief
Overview
www.ti.com
overview
AR
Y
The device contains two USB modules:

AUSB
High-Speed USB OTG Controller (see Section 22.1, High-Speed USB OTG Controller)
3.12.2.9
A High-Speed USB Host Subsystem (see Section 22.2, High-Speed USB Host Subsystem)
The device contains two USB modules ( HS USB OTG controller / HS USB host subsystem).
Device
High-Speed USB OTG controller
High-Speed USB host subsystem

USBTLL
12 pins ULPI
Port 1
Channel 0
12 pins ULPI
Port 2
Channel 1
12 pins ULPI
Port 3
EL
IM
IN
High-Speed USB
host controller
Port 0
Figure 22-1. USB Modules overview
Channel 2
12 pins ULPI
PR
usb-035
3280
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
- 79 -

3. Technical Brief
3.12.2.10 MMC/SD/SDIO
The Multimedia card high speed/ SD /SDIO(MMC/SD/SDIO) host controller provides an interface between a local host
such as a microprocessor unit or digital signal processor and either MMC, SD memory cards or SDIO cards and handles
MMC/SD/SDIO Overview
www.ti.com
MMC/SD/SDIO
transactions with minimal local host intervention.
Figure 24-1. MMC/SD/SDio1 and 3 overview

vdds_mmc1
Device
PBIAS0cell
SCM
MMC/SD/SDIO1
controller
vdds_sim
PBIAS1cell
AR
Y
L4
interconnect
MMC1_IRQ
MPUINTC
mmc1_clk
mmc1_cmd
MMC1_FCLK
MMC1_32K
MMC1_SWAKEUP
mmc1_dat[3:0]
MMC1_DMA_RX
MMC1_DMA_TX
PRCM
MMC/SD/SDIO3
controller
EL
IM
IN
L4
interconnect
SystemDMA
controller
(sDMA)
mmc3_clk
MMC3_IRQ
mmc3_cmd
MMC3_DMA_RX
MMC3_DMA_TX
mmc3_dat[7:0]
96MHz
32kHz
MMC3_FCLK
MMC3_32K
MMC3_SWAKEUP
Wakeupfrommmc3_dat1pin(SDIOinterrupt)usingGPIO
Wakeupfrommmc1_dat1pin(SDIOinterrupt)usingGPIO
mmchs-001
PR
GPIO
- 80 -

3. Technical Brief
3.12.2.10 General Purpose IO
The general-purpose interface combines six general purpose IO banks Each GPIO module provides 32 dedicated
general purpose pins with input and output capabilities thus, the general purpose interface supports up to 192
General-Purpose Interface Overview
www.ti.com
(6X32) pins.
Figure 25-1. General-Purpose interface overview

Device
General-purpose interface
GPIO1
GPIO1_ICLK
GPIO1_DBCLK
AR
Y
GPIO_[31:0]
L4-Wake-up
interconnect
gpio_[31:0]
GPIO1_MPU_IRQ
GPIO1_IVA2_IRQ
GPIO1_WAKE
L4-Per
interconnect
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO_[191:188]
GPIO_[186:160]
_
GPIO_[159:128]
GPIO_[127]
gpio_[191:188]
gpio_[186:160]
gpio_[159:128]
gpio_[127]
Interface clock
GPIO2_ICLK
BANDGAP
TSHUT
GPIO_[126:96]
EL
IM
IN
PRCM
Debounce clock
Wake-up
requests
GPIO2_DBCLK
GPIO2_WAKE
GPIO_[95:64]
GPIO_[63:34]
gpio_[126:96]
gpio_[95:64]
gpio_[63:34]
IVA2.2 subsystem
interrupt
controller
MPU subsystem
interrupt
controller
Interrupt requests
GPIO2_IVA2_IRQ
GPIO_33
Interrupt requests
DAC1
TV_DETECT
GPIO2_MPU_IRQ
other GPIO modules

(GPIO3 to GPIO6)
gpif-001
PR
Each channel in GPIOs has the following features:

The GPIOi.GPIO_OE register controls the output capability for each pin.
The output line level reflects the value written in the GPIOi.GPIO_DATAOUT register through the level
4 (L4) interconnect.
The input line can be fed to GPIO through an optional and configurable debounce cell. (The
debouncing time value is global for all ports of one GPIO module, so up to five different debouncing
time values are possible.)
The input line value is sampled into the GPIOi.GPIO_DATAIN register and can be read through the L4
interconnect.
In active mode, the input line can be used through level and edge detectors to trigger synchronous
interrupts. The edge (rising, falling, or both) or the level (logical 0, logical 1, or both) used can be
configured.
In idle mode, the input line can be used to activate the asynchronous wake-up request (on edge
detection: Rising edge, falling edge, or both).
The module provides an alternative to the atomic test and set operations for the following registers:
GPIOi.GPIO_DATAOUT
- 81 GPIOi.GPIO_IRQENABLE1
GPIOi.GPIO_IRQENABLE2
GPIOi.GPIO_WAKEUPENABLE
3. Technical Brief
3.13 Audio and sound

3.13.1 Overview of Audio path
1/#2
69.
z~
$%/

9/
mtGpYz
}tpk
hkjpu^
#WFKQ
5WDU[UVGO
ZU\
Figure. Block diagram of Audio & Sound path
- 82 -

3. Technical Brief
3.13.2 Audio signal processing & interface

3.13.2.1 TWL5034 audio interface
The device audio module contains several audio analog inputs, outputs, and digital microphone inputs. It is
connected to a multimedia processor through the TDM/codec interface (audio interface) and to a 3GPP Modem
through a pulse-code modulation (PCM) interface (voice interface) and Bluetooth interface. The audio module is
controlled by internal registers that can be accessed by the high-speed I2C control interface.
- Feature List Overview

Serial data ports:
Two ports: Port 1 is a voice PCM interface; Port 2 is an audio inter-IC sound (I2S)/time-division
multiplexing (TDM) interface.
No support for McBSP dynamic slot
Both ports are master/slave (In TDM mode, Port2 can act only as a master.)
Tri-state capability on I2S/TDM and PCM
Audio and voice channels:
Voice channel with 8- or 16-kHz sampling modes on MCLK=26MHz
Audio channel with 8-, 11.025-, 12-, 16-, 22.05-, 24-, 32-, 44.1-, or 48-kHz sampling modes, 96 kHz
is supported on the RX path
Audio phase-locked loop (PLL) supports 26-MHz, 19.2-MHz, or 38.4-MHz
Carkit, analog loop mode
Secondary microphone for noise cancellation
Three analog microphone biases and two digital microphone biases
Power and analog mixing
Analog/digital mixing capability (path-mixing capability)
8- stereo class D/class AB (16- headset or 32- earpiece) drivers
Class D output power of 700 mW (8 with VBAT = 4.0 V)
Stereo with or without pseudo-ground headset driver
Eight lines for the uplink path (four differential inputs). FM input is mono or stereo.
Predrivers for external class D or piezoelectric speaker drivers (multiplexed on HS pseudo-ground output)
Left/right paths switch on hands-free speaker and predriver for external class D amplifier.
Differential H-bridge driver for Vibrator.
- 83 -

3. Technical Brief
Additional features
Headset detect capability (GPIO)
Digital microphone inputs (four microphone inputs, two clocks, and two supplies for two external
digital microphones). Supplies are the microphone biases referred to in the previous sublist.
Data and clock are multiplexed on the PCM port.
Pop-noise reduction circuitry for all paths
Side-tone function for the voice pathsTI Confidential NDA Restrictions
Data scramble function for I2S data received
www.ti.com
Bass boost functions in one stereo audio RX path
Functional Description
Automatic
gain
control
onconnected
the microphone
The
analog
input
to the paths
analog auxiliary input and the microphones
Independent gains on UL paths
Note:
The modem or the OMAP device Bluetooth, voice, and audio interfaces must use
Programmable gain
onprovider
audio RXasand
the amplifier
same clock
theTX
device.
Wide gain programmable range on the microphone input
Figure 14-4 is an architecture overview of the audio subsystem.
DTMF tone generator
Figure 14-4. Device Audio Subsystem Architectural overview
Device- Audio
BT
voice
serial
port
Voice
DAC
PCM
voice
serial
port
Analog
mixing
VoiceandBluetoothpaths
Digitalmixing
volumecontrol
filters
Analog
drivers
Analog
volume
control
Four
ADCs
Audioandvoicemixeranddrivers
Audio
TDM/I2S
serial
port
interface
Digitalmixing
volumecontrol
filters
Programmable
analogamplifiersfor
themicrophones
Two
ADCs
Digital
microphones
interface
AudioRx/Txandvoice Tx
Inputinterfaces
audio-004
14.4.1 Data Paths
Figure . Device Audio Subsystem Architectural Overview
After the audio submodule is powered up (by the CODECPDZ bit of the CODEC_MODE register, see
Table 14-19), it has two modes of operation:
LGE Internal
Only 1: Four simultaneous multimedia analog
Copyright 2011
LG Electronics. Inc.converters
All right reserved.
Use
Option
(four multimedia
digital-to-analog
- 84channels
Only for training
service purposes
(DACs) and no modem voice path), and two simultaneous analog-to-digital converters
or and
4 channels
coming from digital microphones.
Option 2: A dedicated modem voice path (two multimedia DACs plus the ADC/DAC pair used for the
3. Technical Brief
Functional Description
www.ti.com
Figure 14-7. voice/Audio option2 (oPt_MoDe = 0) Block Diagram

-24 to 12 dB
2-db step + mute
-30 to15 dB
3 dB step
BTDOUT
+
-50 to -10 dB
1 dB step+ mute
BT_PCM_ VDR
BTRXPGA
Coase gain
2nd
M
U
X
BT_ PCM_VDX
HSOL
Voice A
VDL_ GAIN
Analog PGA
BTTXPGA
Coase gain
PCM
interface
8/16 kHz
M
I
X
+
Two output amplifiers
can be driven by an
analog RXPGA amplifier
simultaneously.
M
I
PreDriv_LEFT
or HSOVMID
Ampli_PreD
PreDriv_RIGHT
VDR
M
U
X
PCM _ VDR
VRXPGA
Fine gain
TN
ATT
M
U
X
VSTPGA
voice sidetone
VDXS
TNG3
VRX2 ARX
PGA
DACR1
-42 to 0 dB
6 dB step
Analog PGA
Gain=
1 or 1
I
X
IHF_RIGHT_P
M
U
X
TNG1
Audio AL1
Voice D
ARXL1
M
U
X
ARXR1PGA
finegain
+boost
ARXR1PGA
coarse gain
ARXL1PGA
finegain
+boost
ARXL1PGA
coarse gain
ARXR2PGA
finegain
SDRR2
Audio
Filter R2
Digital mono
SDRM2
Loopbackfunc
I2S
interface
TDM/I2S_ CLK
Audio
DL1
Audio
DR2
DL1
Modulator
2nd
ARXL2PGA
finegain
+
M
U
X
Audio
Filter L2
ARXL2PGA
coarse gain
To USB block
M
I
X
ARXR2
Modulator
2nd
DACR2
Analog PGA
Carkit L
PRECKT_Left
EAR_P
2nd
M
I
-62 to 0 dB 0 dB to 12 dB
1-dB step 6-dB step
+ mute
OCP
interface
DACL2
ARXL2
M
U
X
Ampli_Ear
0 dB, +6 dB, +12 dB
Analog PGA
Audio AL2
EAR_M
Vmid
M
U
X
PWM
generator
ARX2 VTXPGA
VIBRA_P
H-bridge
vibrator
ATX2ARXL_PGA
Digital loop
(test only)
TDM/I2S_ DOUT
Voice stereo path
Digital
AVTXR2PGA
finegain
Mixing
VUL filterR
AVTXL2PGA
fine gain
VUL filterL
Mic
channel 2
Audio filter R1
Mic
channel 1
Audio filter L1
ATXR1PGA
finegain
Voice: 125 Fs
Audio: 80 Fs
ADCL
TX path
VIBRA_M
FM
Radio loop
FMR
FML
.
.
From USB block

DINP
DINM
HSMICP
HSMICM
Ampli_L
MIC_MAIN_P
ALC + AA filter
Audio stereo path
19.2/26/38.4 MHz clock
PRECKT_Right
Carkit preamplifiers
Modulator
Audio
DL2
Register
-24 to 0 dB
6-dB step + mute
Carkit R
Audio AR2
-6 dB, 0 dB, +6 dB
-62 to 0 dB
6-dB step + mute
ATX2ARXR_PGA
M
I
X
M
U
X
RX path
TDM/I2S_ SYNC
TDM/I2S_DIN
SDRL2
ARXR2PGA
coarse gain
IHF_LEFT_M
2nd
Audio
@48 kHz
IHF_LEFT_P
Class-DL
DR1
Digital mixing
24 bits
DACL1
Modulator
M
U
Class-DR
IHF_RIGHT_M
DTMF
Analog PGA
M
U
X
Ampli_HS
HSOR
-15 to 0 dB
1.0 dB step
TNG2
-24 to 0 dB
1 dB step + mute
-50 to -10 dB
1 dB step + mute
ARXR1
filter
-15 to 0 dB
1.0 dB step
Audio AR1
-18 db 0 dB
TNG4
VDL
VDXM
HFCLKIN
Ampli_PreD
X
-42 to 0 dB
6 dB step
-36 to 12 dB
1 dB step + mute
PCM_ VFS
PCM _ VDX
Ampli_HS
-15 to 30 dB
3 dB step
Bluetooth
Sidetone
BTDIN
PCM _ VCK
-6 dB, 0 dB, 6 dB
M
I
X
BTSTPGA
Bluetooth
interface
Cross R / L possible for Predriver D / Driver D outputs
Analog mixing
DAC
voice
Modulator
MIC_MAIN_M
1-dB step(ALC)
ATXL1PGA
finegain
0 to 31 dB
1-dB step
ADCR
PLL audio
+ div voice
..
AUXL/FML
ALC is available only for the Main Mic and the Sub Mic
6-dB step(LINE)
MIC_SUB_P
MIC_SUB_M
Ampli_R
AUXR/FMR
Input amps
DIG_MIC0
Digital micro
interface
DIG_MIC_CLK0
50 Fs
audio-006
Figure. Detailed diagram of TWL5034 audio interface
SWCU051F March 2008 Revised July 2010
Audio
- 85 -
671

Copyright 20082010, Texas Instruments Incorporated
3. Technical Brief
3.13.2.2 WM9093 audio interface

The WM9093 is a high performance low power audio subsystem, including headphone driver and Class AB/D
earpiece/speaker driver. The Class D speaker driver support 650mV output power at 3.6V, 1%THD.
The unique dual mode charge pump architecture provides ground referenced headphone outputs removing the
requirement for external coupling capacitors. Class G technology is integrated to increase the efficiency and
extend playback time by optimizing the headphone driver supply voltages according to the volume control.
The flexible input configuration allows single ended or differential stereo inputs. Mixers allow highly flexible
routing to the outputs, A voice Bypass path is also available for low-power voice applications.
The WM9093 is controlled using a two-wire I2C interface. An integrated oscillator generates all internal clocks.
Removing the need to provide any external clock.
Separate mixer and volume controls are provided for each headphone and speaker driver. Automatic Gain
control limits the speaker output signal in order to prevent clipping. DC offset correction to less than 1mV
Guarantees a pop/click-free headphone start up.
The WM9093 is available in a 2.0mm 2.5mm 20-bump CSP package.
Figure. Detailed diagram of WM9093 audio interface
- 86 -

3. Technical Brief
AUDIO SUBSYSTEM
VBAT
C602
C603
33p
100n
2.2u
B5
B3
B2
CPVDD
A3
CPVSS
A4
CP
A5
CN
SPK_P
SPK_N
C617
2.2u
C618
2.2u
C619
C613
C614
0.1u
0.1u
R601
R602
EAR_L
EAR_R
20
IN3IN3+
SCL
SDA
D3
C3
A2
HPL
A1
HPR
IC601
IN2IN2+
20
R605
D2
D1
R604
47n
HPVDD
47n
C612
FB602
2.2u
B4
470n
IN1IN1+
GND
C609
C611
C2
C1
BIAS
470n
B1
SPK+
SPK-
C608
C4
HSO_R
HSO_L
FB601
C5
OUT+
D5
OUT-
SVDD
D4
C601
I2C2_SCL
I2C2_SDA
2.2u
2.2u
C631
C632
1.8V_AUDIOAMP
R610
EAR_GND
DNI
MIC Switch
VBAT
U610
MIC_P
MIC_SEL
MIC_N
5
6
9
1A
1B0
S1
1B1
2A
2B0
S2
2B1
VCC
GND
10
1
2
3
MIC1P
MIC2P
MIC1N
MIC2N
C690
2.2u
- 87 -

3. Technical Brief
EAR DETECTION
(Close to Connector)
Q601
1.8V_VIO
2
1
R609
R608
200K
1M
EAR_SENSE
EAR_DETECT
HOOK
1.8V_VIO
100K
R606
1.8V_VIO
U602
VIN-
5
1
VCC
VIN+
HOOK_ADC
OUT
GND
HOOK_DIG
100K
2
R607
- 88 -

3. Technical Brief
3.14 Display
LCD module is connected to Main PCB with 30-pin connector.
The LCD is controlled by MDDI Interface in OMAP3630
VBAT
3.0V_LCD_VCC_VCI
1.8V_LCD_IOVCC
FL702
1
P1
2
P2
3
P3
4
P4
CN702
30
29
28
27
26
25
24
23
22
10
21
11
20
12
19
13
18
14
17
15
16
INOUT_A2
INOUT_B3
INOUT_A3
INOUT_B4
INOUT_A4
10
G2
INOUT_B2
LCD_PWM
15pF
LCD_BL_OUT4
LCD_BL_OUT3
LCD_BL_OUT2
LCD_BL_OUT1
C720
C715
C714
4.7u
2.2u
2.2u
P5 5
INOUT_A1
LCD_BL_OUT8
LCD_BL_OUT7
LCD_BL_OUT6
LCD_BL_OUT5
P3
P1
P4
P2
1
2
LCD_MIPI_CLK_P
LCD_MIPI_CLK_N
P6
INOUT_B1
G1
LCD_TE
LCD_CS
LCD_RESET_N
FL701
LCD_MIPI_D0_P
LCD_MIPI_D0_N
LCD_MIPI_D1_P
LCD_MIPI_D1_N
9
G1
10
G2
LCD_MAKER_ID
5
P5
6
P6
7
P7
8
P8
FL703
Figure. Schematic of LCD connector (Main Board)
- 89 -

3. Technical Brief
Pin No.
Signal
I/O
Function
Drivers Signal Name
MAKER_ID(Low)
Maker ID(Low; GND level)
IOVcc
IO Power (1.8V)
IOVCI
PWMO
PWM output pin of Active Back Light control processir
PWMO
TE
Tearing Effect output pin
CSX
Chip Select pin Note(1)
CSX
RESB
Reset Input pin
RESB
Vci
Analog power supply for reference (2.8V)
SVCI
Vcc
Analog power supply for Analog Circuit (2.8V)
AVCI
NC
NC
10
LEDC_4
GND for LED
11
LEDC_3
GND for LED
12
LEDC_2
GND for LED
13
LEDC_1
GND for LED
14
LED_A
Power supply for LED
15
LED_A
Power supply for LED
16
GND
GND
17
LEDC_5
GND for LED
18
LEDC_6
GND for LED
19
LEDC_7
GND for LED
20
LEDC_8
GND for LED
21
GND
GND
22
MCLK_M
Negative MIPI Clock Input
MCLK_M
23
MCLK_P
Positive MIPI Clock Input
MCLK_P
24
GND
GND
25
MDATA1_M
I/O
Negative MIPI Data2 Input / Output
MDATA1_M
26
MDATA1_P
I/O
Positive MIPI Data2 Input / Output
MDATA1_P
27
GND
28
MDATA0_M
I/O
Negative MIPI Data1 Input / Output
MDATA0_M
29
MDATA0_P
I/O
Positive MIPI Data1 Input / Output
MDATA0_P
30
GND
TE
GND
GND
Table. Interface between LCD Module and MAIN Board
- 90 -

3. Technical Brief
Part Name
TX10D10VM0EAA
Module Dimensions
55.54 (W)mm x 95.8 (H)mm x 1.45 (T)mm

(Excluding I/F-FPC and electronic components)
Active Area Dimensions
51.84 (W)mm x 86.4 (H)mm
Pixel pitch
0.108 (W)mm x 0.108(H)mm
Resolution
480 x3 (R,G,B) (W) x 800(H) dots
Color Pixel Arrangement
RGB Vertical Stripe
Display Mode
Transmissive Type, Normally Black Mode, In-Plane Switching Mode
Number of Colors
16,777,216 Colors / 262,144 Colors
Viewing Direction
10
Backlight
Light Emitting Diode (LED), 8 LEDs are parallel connection Backlight

current: 20mA / LED (typ)
11
Weight
12.6g(typ)
12
Power supply Voltage
Vcc=2.8+/-0.1V, Vci=2.8+/-0.1V
13
Interface I/O power supply

Note(1)
IOVcc=1.8+/-0.1V
The same voltage as H level of a customers interface signal must be
supplied to IOVcc.
14
LCD Driver IC
D51E6TA8851A (Source and Power IC: MagnaChip Semiconductor)
15
Interface
MIPI-DSI Command mode (2-Lane)
Note(1): IOVcc is the reference voltage for adjusting the I/O signal level of TA8851A.
IOVcc voltage must be determined according to a customers system.
Table. LCD Module general data
- 91 -

3. Technical Brief
7BLOCK DIAGRAM
RGB
G1
LCD
480 x RGB (H) x 800 (V)
G400
Scan direction
G800
S1440
LED Backlight
S1
TA8851A
(8LEDs in parallel)
CN3
CN1
CN2
Notes (1)
LED (Anode: 2,Cathode: 8)
VCC,VCI
IOVCC
PWM0
10
2
MAKERID
TE
GND
MDATAO_P, MDATAO_M
MDATAI_P,MDATAI_M
MCLK_P,MCLK_M
RESB,CSX
5
4
Notes (1) Please connect the resistor (R=200 ohm) for current control between LED (cathode)
and GND in the customer's system.
ILED = 160 mA
Hitachi Displays, Ltd.
Date
AN
20 mA
20 mA
20 mA
20 mA
20 mA
20 mA
20 mA
20 mA
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
LCD Sh.
Module
block2607
diagram
Nov. Table.
04, 2010
3284PS
- TX10D10VM0EAA-1
No.
- 92 -
Page
7-1/1

3. Technical Brief
3.15
3.14 Main (5M pixels) & Sub (2M pixels) Camera
LG-P970 supports two cameras. One is 5M pixels, main camera, the other is 2M pixels, sub camera used VT & self
camera scene.
1.2V_5M_VDIG
FL601
1.8V_5M_VIO
CN602
FL602
5
P5
6
P6
7
P7
8
P8
G2
10
G1
9
5M_MIPI_DATA0_N
5M_MIPI_DATA0_P
5M_MIPI_DATA1_N
5M_MIPI_DATA1_P
1
P1
2
P2
3
P3
4
P4
24
23
22
21
20
19
18
17
16
10
15
11
14
12
13
2.8V_5M_VCM
I2C3_SDA
I2C3_SCL
C620
C621
C622
4.7u
1u
0.1u
ZD601
C624
C623
0.1u
0.1u
5M_RESET_N
5M_CAM_VCM_EN
0.1u
G2
10
G1
9
5M_MCLK
2.7V_5M_VANA
1
P1
2
P2
3
P3
4
P4
C625
5
P5
6
P6
7
P7
8
P8
5M_MIPI_CLK_N
5M_MIPI_CLK_P
Figure. Main 8M Camera Schematic
VT_CAM_DRV_2.8V VT_CAM_IO_1.8V
VT_DATA[7]
VT_DATA[6]
VT_DATA[5]
VT_DATA[4]
6
7
8
9
CN103
24
23
22
21
20
19
I2C3_SCL
FL102
G1
G2
10
7.5pF
I2C3_SDA
INOUT_B4
INOUT_A4
INOUT_B3
INOUT_A3
INOUT_B2
INOUT_A2
INOUT_B1
INOUT_A1
4
3
2
VT_VSYNC
VT_DATA[3]
VT_DATA[2]
VT_DATA[1]
VT_DATA[0]
6
7
8
9
INOUT_B4
INOUT_A4
INOUT_B3
INOUT_A3
INOUT_B2
INOUT_A2
INOUT_B1
INOUT_A1
18
17
16
10
15
11
14
12
13
VT_MCLK
FL103
G1
G2
10
7.5pF
VT_HSYNC
VT_PCLK
4
3
2
1
VT_RESET_N
VT_CAM_PWDN
1u
1u
C101
C102
Figure. Sub 2M Camera Schematic

- 93 -

3. Technical Brief
VBAT
2.2u
D1
2.2u
10u
FB
LDO1
VIN1
VIN2
VINB
VBATT
E4
D2
E3
D4
B3
C4
C3
D3
E2
CAM_SUBPM_EN
GNDB
IRQ_N
U601
SDA
SCL
LDO3
A3
A1
DVS
EN
LDO4
DEFSEL
IDSEL
LDO5
C1
E1
C626
C627
C628
C629
C630
1u
1u
1u
1u
1u
B1
GND
B2
C2
B4
SW
LDO2
I2C3_SDA
I2C3_SCL
2.7V_5M_VANA
C607
2.2u
A2
C606
2.2u
1.8V_5M_VIO
L601
C605
10u
2.8V_5M_VCM
C610
C604
A4
1.2V_5M_VDIG
3.0V_MOTOR
3.0V_MMC
VBAT line minimum 0.6mm
Figure. 5M Camera PMIC Schematic
VDAC_IN
VAUX12S_IN
VPLLA3R_IN
VINT_IN
VSDI_CSI_OUT
VPLL1_OUT
VDAC_OUT
VSIM_OUT
VMMC2_OUT
VMMC1_OUT
VAUX4_OUT
VAUX3_OUT
VAUX2_OUT
VAUX1_OUT
VINTUSB1P8_OUT
VINTUSB1P5_OUT
VUSB_3P1
VINTDIG_OUT
VRTC_OUT
VINTANA2_OUT_02
VINTANA2_OUT_01
VINTANA1_OUT
K1
L1
H15
K15
J15
1.8V_AUDIOAMP
1.8V_PLL1
1.8V_MOTION_VIO
1.8V_WLAN
1.8V_MMC_EN
VT_CAM_DRV_2.8V
1.8V_CSI2
VT_CAM_IO_1.8V
3.0V_MOTION
2.8V_PROXI
H14
L2
K2
A4
C2
B3
G16
M3
M2
P10
C461
1u
C451 C452 C5019 C454 C5018 C456 C457 C5017 C459
C460
P8
C462
1u
1u
1u
L16
C463
1u
K16
C482
1u
B6
C483
1u
C484
1u
1u
1u
1u
1u
1u
1u
1u
1u
P9
3.1V_VUSB
J2
H3
C485
1u
Figure. 5M Camera PMIC Schematic
- 94 -

3. Technical Brief
5M_CLK
2.7v_5M_vANA
sw_^YW
\t
1.8v_5M_vio
2.8v_5M_vCM
1.2v_5M_vDiG
Osnp{P
MiPi_CLK
MiPi_DAtA
reSet_N
i2C3_SDA
i2C3_SCL
i2C3_SDA
vthwZ]ZW
i2C3_SCL
{~s\WZ[
vt_CAM_Drv_2.8v
vt_CAM_io_1.8v
Yt
j
Osnp{P
vt_MCLK
vt_PCLK
vt_DAtA[0:7]
vt_vSYNC
vt_HSYNC
Figure. Camera Block diagram
- 95 -

3. Technical Brief
3.16 Vibrator
The ERM motor, also distinguished as Q-coin Motor creates a certain kind of vibration controlled and defined
uniquely by LG Electronics. The followings are the certain examples of conditions that the users may feel the
vibration from the phone: Incoming Call (in Silence Mode), Google Keys Pressed, Turn-on / -off, Dialing, and Text
Messaging.
3.0V_MOTOR
Q-Motor
DNI
R510
Moter Driver
U504
VDD
GAIN
VDN
NC1
GND
MODE
NC2
PWM
VIB_P
7
6
5
VIB_N
C517
2.2u
R516
11
VDP
NC3
EN
10
VIBE_EN
VIBE_PWM
VB101
VIB_P
VIB_N
1
2
SJMY0007118
C519
1%
10n
DNI
R517
Figure 1 Vibrator Schematic
- 96 -

3. Technical Brief
3.17 Compass Sensor

If a customer buy the application SW, The Sensor provides user with a Electric Compass function.
1.8V_MOTION_VIO
3.0V_MOTION
COM_INT
U105 (AK8975C, SUB-FPCB) IC is interfaced to OMAP3630(U301) using I2C interface.
C116
C1
VSS
TST2
C2
C3
DRDY
TST6
VDD
B3
B1
RSV
SCL/SK
TST1
B4
3.0V_MOTION
U105
SDA/SI
A1
SO
C117
0.1u
A4
D4
I2C3_SDA
CAD1
A3
D2
CAD0
CSB
D1
A2
R117
VID
C4
10K
0.1u
1.8V_MOTION_VIO
I2C3_SCL
C119
0.1u
Figure. Compass Sensor Schematic

3-axis
Hall sensor
Chopper SW
Integrator & ADC
Per- AMP
MUX
OSC1
HE-Drive
SCL/SK
Interface,
Logic
& Register
Timing Control
CSB
SO
Voltage Reference
Magnetic source
SDA/SI
DRDY
POR
FUSE ROM
CAD0
CAD1
TST1
TST2
RSV
TST6
VSS
VDD
VID
Figure. Compass Sensor Block Diagram

- 97 -

3. Technical Brief
3.18 Motion Sensor

The motion sensor can sense gravity & accelerated motion. Therefore according to the direction of cell phone,
the phone screen is rotated automatically. And the motion sensor is connected with a gyro sensor to
supplement each data.
U104(SUB_FPCB) : KXTF9 IC is interfaced to OMAP3630(U301) using I2C interface.
3.0V_MOTION
C123
1.8V_MOTION_VIO
GND
DNC2
DNC3
INT
DNC1
U104
IO_VDD
DNC4
SCL
MOTION_INT
IME_CL
SDA
VDD
0.1u
10
C118
0.1u
IME_DA
Figure. Motion Sensor Schematic
X
Senser
Y
Senser
A/D
Charge Amp
Z
Senser
Vdd 5
Digital
Filter
I2C
Digital Engine
IO Vdd 1
GND 4
7
10
G
Figure. Motion Sensor Block Diagram
- 98 -

3. Technical Brief
3.19 Gyro Sensor

The gyro sensor(MPU3050) can sense angular velocity not gravity and accelerated motion. The gyro sensor
applied in LG- P970 can detect 3-axis rotation force sensing X,Y and Z angular velocity. And the gyro sensor
data is supplemented by the motion sensor data. It make possible user to development application SW using
gyro sensor data like that motion games.
U103(SUB_FPCB): MPU3050 IC is interfaced to OMAP3630(U301) using I2C interface.
1.8V_MOTION_VIO
CLKIN
NC2
NC3
IME_DA
NC 1
CLKOUT
CPOUT
RESV1
25
24
I2C3_SDA
I2C3_SCL
23
22
21
20
19
C115
2.2n
18
17
GND
RESV2
INT
NC8
FSYNC
13
3.0V_MOTION
REGOUT
VD D
GYRO_INT_N
12
SCL
U103
NC7
11
SDA
AD0
16
10
VLOGIC
15
NC4
6
0.1u
NC6
8
C121
NC9
IME_CL
NC5
IME_CL
14
0.1u
IME_DA
C122
C120
0.1u
Figure. Gyro Sensor Schematic
Figure. Gyro Sensor Block Diagram
- 99 -

3. Technical Brief
3.20 Proximity Sensor

When the call is connected and the object close to the proximity sensor,
LCD backlight and Touch screen are disable operation automatically.
U102(VT_CAM FPCB) : GP2AP002S00F IC used I2C interface to OMAP3630
PROXI_VCC
1.8V_VIO
PROXI_LEDA
U102
1
PROX_OUT
C106
C107
4.7u
0.1u
LEDA
SCL
LEDC
SDA
VCC
VIO
VOUT
GND
I2C3_SCL
I2C3_SDA
C105
1u
Figure. Proximity Sensor Schematic
Figure. Proximity Sensor Block Diagram

G
- 100 -

3. Technical Brief
3.21 Illumination Sensor

Illumination Sensor adjusts LCD backlight current by detecting the surrounding brightness.
If user checks the automatic brightness menu, LCD backlight current adjusting is to be enable automatically.
U101(VT_CAM FPCB) : BH1621 IC interface to AAT2870
U101
5
VCC
GND1
GC2
GC1
LSENSOR_BIAS
2
3
IOUT
GND2
LSENSOR_SENS
Figure. Illumination Sensor Schematic
Figure. Illumination Sensor Block Diagram

G
- 101 -

3. Technical Brief
3.22 Touch Module

Touch module is connected to Main PCB with 10-pin connector.
The Touch module is controlled by I2C Interface in OMAP3630
3.0V_TOUCH
1.8V_TOUCH
R703
10K
1.8V_TOUCH
CN701
10
1
2
5
C705
I2C2_TOUCH_SDA
0.1u
TOUCH_INT_N
C707
ZD703
ZD702
ZD701
0.1u
I2C2_TOUCH_SCL
Figure. Schematic of Touch connector (Main Board)
Pin No.
Signal
Description
1.8V TOUCH
Power Supply for Interface I/O
NC
GND
GND
GND
I2C2_TOUCH_SCL
I2C Clock
GND
I2C2_TOUCH_SDA
I2C Data
3.0V TOUCH
Power Supply for Driver IC
10
TOUCH_INT_N
Interrupt
Table. Interface between Touch Module and MAIN Board
- 102 -

3. Technical Brief
3.23 Main Features

3.23.1 LG-P970 Main Features
- DOP Type design
- UMTS 2100 + UMTS 1900 + UMTS900+ GSM 900 + DCS 1800 + PCS 1900 + GSM850 based
GSM/GPRS/EDGE/UMTS(WCDMA, HSDPA, HSUPA)
- HSDPA 7.2Mbps, HSUPA 5.7Mbps
- Main LCD(WVGA)
TFT Main LCD(4.0, 480X800)
- Capacitive/Electrostatic Touch Window
- 5M AF Camera, 2 M secondary camera
- 3.5Phi Stereo Headset & Speaker phone
- Mobile XMF Mobile DLS / Scaleable Polyphony
- MP3/AMR/AAC/AAC/WAV/WMA decoder and play
- MPEG4 encoder/decoder and play/save
- JPEG en/decoder
- Supports Bluetooth and HS-USB
- Supports WLAN(802.11b, 802.11g, 802.11n)
- Supports FM Radio
- 1500 mAh (Li-Ion)
- 103 -

3. Technical Brief
3.23.2 LG-P970 Main component (BOTTOM)
Maker P/N: BCM43291SKUBG

Function: Wifi_BT_FM CHIP
Maker P/N: KT32251L38400

Function: TCXO 38.4 Mhz
Maker P/N: PMB9801
Function: Call Processor
Maker P/N: TWL5034

Function: OMAP Power chip
Maker P/N: H8BCS0Q0MR-46M

Function: CP MEMORY
Maker P/N: SDIN502-2G

Function: EMMC-MEMORY
Maker P/N: BD2812

Function: RGB LED DRIVER
Maker P/N: OMAP 3630
Function: Application Processor
- 104 -

3. Technical Brief
3.23.2 LG-P970 Main component (TOP)
Maker P/N: MAX14526

Function: MUIC
Maker P/N: BGA749N16

Function: LNA
Maker P/N: ACMD7606
Function: Filter
Maker P/N: LP8720

Function: SUB PMIC CAM POWER
Maker P/N: ACPM5202

Function: Power AMP
Maker P/N: PMB5703

Function: Transceiver
Maker P/N: BCM4751

Function: GPS Chip
Maker P/N: ISA1000

Function: LCD B/L charge pump
Maker P/N: SKY77529

Function: QUAD TX Module
Maker P/N: RT9524
Function: Charging IC
Maker P/N: ACPM5281-TR1G

Function: 3G Dual PAM
Maker P/N: MAX17043

Function: Fuel gauge
- 105 -

4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
4. Trouble Shooting
4.1 RF Component
FL104
X101
FL105
FL103
U101
RF Transceiver
FL102
FL101
FL107
FL109
U106
W LNA
FL110
U103
WB 2
FL106
PAM
U105
WB 1/8
PAM
FL108
U102
U104
FEM+GSM PAM
FL111
RF component (WCDMA / GSM)
Reference
Description
Reference
Description
U101
U104
U105
U103
FL111
FL107
FL109
FL110
FL106
PMB5703(Transceiver)
FEM + GSM/EDGE PAM Module
WCDMA Dual (I,VIII) PAM
WCDMA Single (II) PAM
WCDMA (I) TX SAW Filter
WCDMA (II) TX SAW Filter
WCDMA (VIII) TX SAW Filter
WCDMA (I) Duplexer
WCDMA (II) Duplexer
FL108
FL101
FL102
FL103
FL104
FL105
U106
X101
U102
WCDMA (VIII) Duplexer

DCS RX SAW Filter
W1900/PCS RX SAW Filter
W2100 RX SAW Filter
GSM850 RX SAW Filter
W900/EGSM RX SAW Filter
WCDMA (I,II,VIII) LNA
TC-VCXO(26MHz)
WCDMA Power Detector
- 106 -

4. TROUBLE SHOOTING
4.2 SIGNAL PATH

WCDMA / GSM Tx PATH
WCDMA 2100 TX PATH, WCDMA 1900 TX PATH, WCDMA 900 TX PATH

GSM Low Band Tx PATH, GSM Hign Band Tx PATH
- 107 -

4. TROUBLE SHOOTING
WCDMA / GSM Rx PATH
WCDMA 2100 RX PATH, WCDMA 1900/PCS RX PATH, WCDMA 900/EGSM TX PATH

DCS Band Rx PATH, GSM 850 Band Rx PATH
- 108 -

4. TROUBLE SHOOTING
4.3 Checking TCXO Block

The output frequency (26MHz) of TCXO (X101) is used as the reference one of PMB5703
- 109 -

4. TROUBLE SHOOTING
Check TP1
VCC of TCXO
2.45 VCC 2.6V
No
Check the PMB5703
Yes
Check TP2
26MHz signal
No
Check soldering and components
Yes
TCXO OK
- 110 -

4. TROUBLE SHOOTING
4.4 Checking GSM TX Module(GSM PAM + FEM) Block
VBATT(TP1)
VBAT
tP1
TP1
C151
C152
10n
22p
C170
C171
1.8p
1.8p
23
PA_POW_DET
22
SS
VBAT
21
DRW
20
CLK
19
VSPI
C178
1u
PA_RAMP
C179
0.1u
18
17
C180
16
15p
15
14
15p
ANT
GND_LB
GND1
DET
RX_L1
SS
GND2
DRW
RXTX_L2
U104
CLK
VSPI
GND3
RXTX_H
GND_SPI
GND4
VCMOS
RXTX_M1
VRAMP
GND5
GND_HB
TX_HB
RX_M2
27
DCS_PCS_TX
C185
TX_LB
RX_M3
1
2
3
RX_850
4
5
6
7
8
9
10
11
12
RX_1900
RX_1800
13
24
G_SLUG
25
1.2n
V_Q3_HB
L133
GSM_TX
V_Q3_LB
26
C150
22u
Schematic of the TX Module
- 111 -

4. TROUBLE SHOOTING
D0
Band Select
D10
D9
Sensor Configuration
Low band
Current sensor FB Off
High bond
D1
Mode Select
GMSK
SPSK
D2
Tx Enable
D15
FE Bcost Comenter
PA off
Off
PA On
On
D5
D4
D3
Current Sensor
D14
D13
D12
D11
FE Status
0.6A
Off
1.7A
0.7A
Tx-M GMSK ANT1
1.8A
0.8A
Tx-L GMSK ANT1
1.9A
0.9A
Reserved
2.0A
1.0A
Rx-L1
2.1A
1.1A
Rx-M2
2.2A
1.2A
Rx-M3
2.3A
1.3A
Reserved
D8
D7
D6
Not Assigned to Specifiic Runction
Rx/Tx-L2
Defaut
Rx/Tx-M1
Rx/Tx-H
Reserved
Reserved
Tx-M GMSK ANT2
Tx-L GMSK ANT2
Reserved
Mode-GMSDK
Mode-SPSK
1.6A
- 112 -

4. TROUBLE SHOOTING
Checking Switch Block Power Source
PAM Vbatt of Check TP1
2.9V < VCC < 5V
No
Replace the GSM Module(U104)
Yes
Check the Logic in each mode
- 113 -

4. TROUBLE SHOOTING
4.5 Checking WCDMA Block

START
1. Check TCXO 26MHz
2. Check FEM Block

Refer to 1.4
3. Check RF Tx Level
4. Check PAM Block

Refer to 1.5.4
5. Check RF Level
6. Ro-download SW & Cal.
- 114 -

4. TROUBLE SHOOTING
4.5.1Checking TCXO Block

Refer to 1.3
4.5.2. Checking FEM Block

Refer to 1.4
4.5.3. Checking RF TX Level
TP2
TP3
TP4
TP1
Test Point (TX Level)
- 115 -

4. TROUBLE SHOOTING
ENWY0003901(Hirose)
SW101
SW102
G1
G2
ANT
ANT
COMMON
G3
C142
TP1
33p
G4
L108
L107
DNI
27n
VBAT
C151
C152
10n
22p
C170
C171
1.8p
1.8p
23
PA_POW_DET
22
SS
VBAT
21
DRW
20
CLK
19
VSPI
C178
C179
1u
PA_RAMP
18
0.1u
17
C180
16
15p
15
C185
ANT
GND_LB
GND1
DET
RX_L1
SS
GND2
DRW
RXTX_L2
U104
CLK
GND3
VSPI
RXTX_H
GND_SPI
GND4
VCMOS
RXTX_M1
VRAMP
GND5
GND_HB
TX_HB
RX_M2
27
DCS_PCS_TX
14
15p
TX_LB
V_Q3_HB
24
RX_M3
1
2
3
RX_850
4
5
6
7
8
9
10
11
RX_1900
12
RX_1800
13
25
1.2n
G_SLUG
L133
GSM_TX
V_Q3_LB
26
C150
22u
VBAT
Band2
C148
L117
C146
C147
1n
2.2u
100p
U103
FL106
1.5n
ANT
TP3
RX
33p
TX
L109
8.2n
100p
GND1
GND6
8.2n
GND2
GND5
C157
GND3
GND4
11
10
9
L110
L122
CPL
7
6
DNI
PGND
VCC2
VCC1
RFOUT
RFIN
ISO
VBP
GND
VMODE
CPL
VEN
TP4
FL107 3
1
C154
2
3
33p
PA_MODE
PA_MODE2
PA_EN_1900
4
5
L130
2.7n
G3
1
OUT IN
G2 G1
5 2
L131
2.7n
TX3G_M1_1900
C158
DNI
C107
100p
(0603)
100p
(0603)
100p
(0603)
TP2
C145
DNI
1880MHz
C162
C160
C161
1880,1960MHz
VBAT
ANT
RX
TX
C131
2
4
5
DNI
GND1
GND2
GND3
GND4
GND5
GND6
1
3
TP3
L129
1n
2.2u
14
13
7
8
9
12
C174
L124
0.5p
100p
11
DNI
10
9
CPL
RFIN_LOW
GND3
VCC2
GND2
VMODE
U105
RFOUT_HI
GND1
CPL
VBP
VCC1
VEN_LOW
VEN_HI
RFIN_HI
15
897.5 MHz,942.5 MHz
RFOUT_LOW
Band1
27p L114
TP2
ANT
RX
TX
L123
10n
33p
4
5
OUT
IN
C173
56p
G3 G2 G1
C177
DNI
PA_EN_900
PA_EN_2100
4
2.7n
PA_MODE2
PA_MODE
2
4
5
GND1
GND2
GND3
GND4
GND5
GND6
1
3
7
8
9
TP3
L125
DNI
897.5 MHz
L115
C187
33p
FL111 3
4
2.7n
1.5n
G3
1
OUT IN
G2 G1
5 2
C188
1p
DNI
C104
10p
TP4
TX3G_H_2100
C192
C193
C194
TX3G_L_900
C176
FL110
2.2n
C181
C169
C172
TP4
FL109
L113
1n
C183
TP2
3.9n
C167
C184
L119
C165
100p
(0603)
100p
(0603)
100p
(0603)
100p
(0603)
33p
C164
C182
C153
FL108
PGND
Band8
1950MHz
DNI
DNI
1950MHz, 2140MHz
For testing, Max power output is needed.
- 116 -

4. TROUBLE SHOOTING
Check Power Level
Check TP1 Over 21dBm?
Yes
RF Tx Level is OK
No
Yes
Check TX Module
No
Yes
Check Duplexer
No
Yes
Check RTR6285
No
Check PAM Block
Refer to 1.5.4
PMB5703 Maximum output Power = 7 dBm
PMB5703 minimum output Power = -73 dBm
- 117 -

4. TROUBLE SHOOTING
4.5.4 Checking PAM Block

PAM control signal
W_PA_EN (W_900_PA_EN(C182),W_1900_PA_EN(C160) W_2100_PA_EN(C181) : PAM Enable
W_PA_MODE1,2 : PAM Gain Control
W_PA_EN must be HIGH (over 2.6V)
PAM IN/OUT Signal
When PAM is under the operation of high power mode
(WCDW_PA_Mode(C162,C183):Low, WCDMA_PA_Mode2(C161,C184):Low),
PAM OUT power must be over 21 dBm
PAM IN power must be under 10 dBm
- 118 -

4. TROUBLE SHOOTING
TP3
TP2
TP1
TP3
C145
C146
C147
1n
2.2u
100p
TP2
TP1
VBAT
U103
11
TP3
10
9
100p
L110
L122
8.2n
CPL
7
6
DNI
VCC2
VCC1
RFOUT
RFIN
ISO
VBP
GND
VMODE
CPL
VEN
TP2 TP2
2
3
4
5
33p
L130
2.7n
3
G3
1
OUT IN
G2 G1
5 2
L131
2.7n
TX3G_M1_1900
C158
DNI
C107
DNI
1880MHz
C162
C160
C161
TP1
FL107
C154
PA_MODE
PA_MODE2
PA_EN_1900
100p
(0603)
100p
(0603)
100p
(0603)
C157
PGND
VBAT
100p
13
12
C174
0.5p
L124
11
DNI
10
9
RFIN_LOW
GND3
VMODE
VCC2
VBP
GND2
U105
RFOUT_HI
GND1
CPL
TP3
L125
VCC1
VEN_LOW
VEN_HI
RFIN_HI
TP2
2
3
TP2
4
5
FL109
L113
C172
33p
4
2.7n
PA_MODE2
PA_MODE
OUT
IN
TX3G_L_900
C176
33p
DNI
FL111
4
2.7n
3
G3
1
OUT IN
G2 G1
5 2
C193
1p
TP1
56p
897.5 MHz
L115
C187
1.5n
C194
C173
G3 G2 G1
C177
DNI
PA_EN_900
PA_EN_2100
C181
15
CPL
RFOUT_LOW
C183
14
C184
1n
C167
C182
2.2u
100p
(0603)
100p
(0603)
100p
(0603)
100p
(0603)
L129
C165
1n
PGND
TP3
C164
DNI
C104
1950MHz
C188
TP1
10p
TX3G_H_2100
C192
DNI
DNI
- 119 -

4. TROUBLE SHOOTING
Set the phone Tx is On and

AGC is 700
Yes
RF Tx Level is OK
No
Check TP2 PA_MODE2 0.5V
Yes
Check PMB5703
No
Check TP1 Over 10 dBm?
Yes
Check PMB5703
No
Change the board
- 120 -

4. TROUBLE SHOOTING
4.5.5 Checking RF Rx Level
TP3
TP4
TP5
Bias
TP2
TP1
Test Point (RF Rx Level)

ENWY0003901(Hirose)
SW101
SW102
G1
G2
ANT
ANT
COMMON
G3
3
TP1
TP1
C142
33p
G4
L108
L107
DNI
27n
VBAT
C151
C152
10n
22p
C170
C171
1.8p
1.8p
23
PA_POW_DET
22
SS
VBAT
21
DRW
20
CLK
19
VSPI
C178
1u
PA_RAMP
C179
0.1u
18
17
C180
16
15p
15
14
15p
- 121 -
ANT
GND_LB
GND1
DET
RX_L1
SS
GND2
DRW
RXTX_L2
U104
CLK
VSPI
GND_SPI
GND4
VCMOS
RXTX_M1
VRAMP
GND5
GND_HB
TX_HB
GND3
RXTX_H
RX_M2
27
DCS_PCS_TX
C185
TX_LB
V_Q3_HB
24
RX_M3
1
2
3
RX_850
4
5
6
7
8
9
10
11
12
RX_1900
RX_1800
13
25
1.2n
G_SLUG
L133
GSM_TX
V_Q3_LB
26
C150
22u

4. TROUBLE SHOOTING
Band2
TP2
C148
FL106
L117
1.5n
ANT
RX
33p
TX
L109
8.2n
GND1
GND6
GND2
GND5
GND3
GND4
1880,1960MHz
C153
33p
Band8
TP2
L119
3.9n
FL108
6
ANT
RX
TX
C131
2
4
5
DNI
1
3
7
GND1
GND2
GND3
GND4
8
GND5
9
GND6
897.5 MHz,942.5 MHz
Band1
TP2
C169
27p
L114
FL110
2.2n
ANT
RX
TX
L123
2
4
5
10n
1
3
7
GND1
GND2
GND3
GND4
8
GND5
9
GND6
1950MHz, 2140MHz
C101
DCS
2p
RX_1800_M1X
2 3
C102
RX_1800
C103
33p
47p
G1 O1
IN
G2 O2
5 4
L126
L101
FL101
5.6n
C105
2p
C106
2p
RX_1800_M1
8.2n
1842.5MHz
Band2 & PCS
TP4
L127
RX_1900
C5027
DNI
RFOUTM
C5029
33p
C108
2.4n
FL102
47p
TP5
O2
3
IN G1G2 O1
2 5
C110
RX_1900_M2
L102
5.6n
C112
2p
RX_1900_M2X
1p
1960MHz
Band1
C115
RFOUTH
47p
TP4
C116
C114
8.2p
TP5
2 3
47p
G1 O1
IN
G2 O2
5 4
C117
RX_2100_HX
L103
FL103
6.8n
C118
8.2p
C119
8.2p
RX_2100_H
DNI
2140MHz
GSM850
C122
RX_850
22p
L128
6.8n
RX_850_L2X
2 3
1
G1 O1
IN
G2 O2
L104
FL104
5 4
C126
12n
C125
8.2p
C130
8.2p
RX_850_L2
1.5p
881.5MHz
Band8/EGSM
RFOUTL
L106
TP4
4.7n
L132
TP5
2 3
3.3n
C132
G1 O1
IN
G2 O2
5 4
RX_900_L1X
L105
15n
FL105
C133
8.2p
RX_900_L1
DNI
942.5MHz
- 122 -

4. TROUBLE SHOOTING
2.85V_RF1
C197
8.2p
2.7p
C196
Bias
TP3
L118
C198
C199
10n
10p
2.7n
LNA_CTRL3
18p
C1002
3.9p
C1001
C5026
DNI
10
11
12
13
RFIN2
RFIN1
VCC
RFOUT1/4
RFGND1/2
RFIN4
RFOUT5
NC
14
L120
2.7n
RREF
RFOUT2
U106
RFIN5
TP3
VON
VGS
9
33p
VEN1
0
C5028
VEN2
R109
15
LNA_CTRL4
RFGND4
DNI
GND
5
4
3
2
1
R106
27K
(1%)
RFOUTM
RFOUTH
RFOUTL
17
16
R110
L121
LNA_CTRL2
18p
C1004
2.7p
C1003
LNA_CTRL1
TP3
8.2n
- 123 -

4. TROUBLE SHOOTING
Set the phone Rx is On
Check BIAS over 2.85V
No
Check bias block soldering
Yes
Check TP1 Signal exist?
No
Check RF Switch (M/S)
Yes
No
Check TX Module Refer 1.4
Yes
No
Check Duplexer
Yes
No
Check LNA
Yes
No
Check PMB5703 and Rx SAW filter
Yes
Change the board
- 124 -

4. TROUBLE SHOOTING
4.6 Checking GSM Block
Start
1. Check TCXO Block
2. Check ANT.SW Module
3. Check RF TRX Level
4. Ro-download SW & Cal.
- 125 -

4. TROUBLE SHOOTING
1
3
2
4.6.1 Checking TCXO Block

Refer to 1.3
4.6.2 Checking FEM Block

Refer to 1.4
4.6.3 Checking RF TX level
TP1
TP3
- 126 -
TP2

3
2 4. TROUBLE SHOOTING
4.6.1 Checking TCXO Block

Refer to 1.3
4.6.2 Checking FEM Block

Refer to 1.4
4.6.3 Checking RF TX level
TP1
TP3
TP2
- 127 -

4. TROUBLE SHOOTING
ENWY0003901(Hirose)
SW101
G2
TP1
SW102
G1
ANT
ANT
COMMON
G3
C142
33p
G4
L108
L107
DNI
27n
VBAT
C151
C152
10n
22p
25
1.2n
24
C170
C171
1.8p
1.8p
23
PA_POW_DET
22
SS
VBAT
21
DRW
20
CLK
19
VSPI
C178
1u
PA_RAMP
C179
0.1u
18
17
C180
16
15p
15
C185
14
15p
TP3
- 128 -
ANT
GND_LB
GND1
DET
RX_L1
SS
GND2
DRW
RXTX_L2
U104
CLK
VSPI
GND3
RXTX_H
GND_SPI
GND4
VCMOS
RXTX_M1
VRAMP
GND5
GND_HB
TX_HB
RX_M2
27
DCS_PCS_TX
TX_LB
V_Q3_HB
L133
RX_M3
1
2
3
RX_850
4
5
6
7
8
9
10
11
12
RX_1900
RX_1800
13
TP2
G_SLUG
GSM_TX
V_Q3_LB
26
C150
22u

4. TROUBLE SHOOTING
Schematic of GSM/DCS/PCS Tx Block
START
Check TCXO Block Refer to 1.3

No
Check TP1
If GSM over 31 dBm?
If DCS/PCS over 28 dBm?
Yes
GSM/DCS/PCS Tx is OK
Check other part
No
Check TP2, 3
If GSM(TP2) under 7 dBm?
If DCS/PCS(TP3) over7 dBm?
Yes
Check ANT SW Block (ASM+EDGR PAM)

Refer to 1.4
No
Check PMB5703 & PAD
No Problem
Check soldering and components
Still exist Problem

Change the board
- 129 -

4. TROUBLE SHOOTING
4.6.4 Checking RF Rx Block
TP2
TP1
ENWY0003901(Hirose)
TP1
SW101
SW102
G1
G2
ANT
ANT
COMMON
G3
3
TP1
C142
33p
G4
L108
L107
DNI
27n
VBAT
C151
C152
10n
22p
C170
C171
1.8p
1.8p
23
PA_POW_DET
22
SS
VBAT
21
DRW
20
CLK
19
VSPI
C178
1u
PA_RAMP
C179
0.1u
18
17
C180
16
15p
15
14
15p
- 130 -
ANT
GND_LB
GND1
DET
RX_L1
SS
GND2
DRW
RXTX_L2
U104
CLK
VSPI
GND3
RXTX_H
GND_SPI
GND4
VCMOS
RXTX_M1
VRAMP
GND5
GND_HB
TX_HB
RX_M2
27
DCS_PCS_TX
C185
TX_LB
V_Q3_HB
24
RX_M3
1
2
3
RX_850
4
5
6
7
8
9
10
11
12
RX_1900
RX_1800
13
25
1.2n
G_SLUG
L133
GSM_TX
V_Q3_LB
26
C150
22u

4. TROUBLE SHOOTING
TP1
C101
DCS
2p
RX_1800_M1X
2 3
C102
RX_1800
C103
33p
47p
G1 O1
IN
G2 O2
L101
FL101
5.6n
5 4
L126
C105
2p
C106
2p
RX_1800_M1
8.2n
1842.5MHz
FL102
Band2 & PCS
L127
RX_1900
C5027
DNI
RFOUTM
C5029
33p
C108
2.4n
47p
2 5
C110
RX_1900_M2
O2
3
IN G1G2 O1
L102
5.6n
C112
2p
RX_1900_M2X
1p
1960MHz
C114
Band1
8.2p
RX_2100_HX
2 3
C115
RFOUTH
47p
C116
47p
G1 O1
IN
G2 O2
5 4
C117
L103
FL103
6.8n
C118
8.2p
C119
8.2p
RX_2100_H
DNI
2140MHz
GSM850
C122
RX_850
22p
L128
6.8n
RX_850_L2X
2 3
1
G1 O1
IN
G2 O2
L104
FL104
5 4
C126
12n
C125
8.2p
C130
8.2p
RX_850_L2
1.5p
881.5MHz
Band8/EGSM
2 3
RFOUTL
L106
4.7n
L132
C132
3.3n
G1 O1
IN
G2 O2
FL105
5 4
RX_900_L1X
L105
15n
C133
8.2p
RX_900_L1
DNI
942.5MHz
- 131 -

4. TROUBLE SHOOTING
Set the phone Rx is On
No
Check RF Switch (M/S)
Yes
No
Check FEM Block Refer 1.4
Yes
Change the board
- 132 -

4. TROUBLE SHOOTING
4.7 GPS/WIFI/BT RF components

4.7.1 GPS RF Components
FL801
U802
U801
U405
X801
Figure. GPS RF Components on top side of the P970 bear board.
Reference
Description
U801
GPS Chip (BCM4751)
U802
LNA Module (LNA + SAW)
FL801
SAW Filter (1575MHz)
X801
TCXO (26MHz)
U405
LDO (150mA)
- 133 -

4. TROUBLE SHOOTING
4.7.2 Wifi/BT/FM RF Components
U803
U804
FL802
X802
U805
Figure. WiFi /BT /FM Components on bottom side of the P970 bear board.
Reference
Description
U803
WiFi/BT/FM Chip (BCM43291)
U805
FEM Module (SP3T + LNA)
FL802
Dielectric Filter (2450MHz)
X802
TCXO (26MHz)
U804
LDO (150mA)
- 134 -

4. TROUBLE SHOOTING
4.8 GPS/WIFI/BT SIGNAL PATH

4.8.1 GPS Signal Path
hu{G
GPS UART to AP
Figure. RF signal path of GPS on top side of the P970 bear board.
- 135 -

4. TROUBLE SHOOTING
4.8.2 Wifi/BT/FM Signal Path

4.8.2 Wifi/BT/FM Signal Path
Via is
connected to
pad of WiFi /
BT ANT.
FM via is connected to
3.5phi Ear-Jack
Figure. RF signal path of WiFi/BT/FM on top side of the P970 bear board.
- 136 -

4. TROUBLE SHOOTING
4.9 Power ON troubleshooting

The main power source of LGP970 is provided by 2 chips which are TWL5034 and XMM6160 (Communication
processor). Since XMM6160 only powers up normally when OMAP3630 is properly powered therefore, TWL5034
are the actual ones to take look at.
Power ON sequence of LGP970 is,
PWR
gogo
to to
lowlow
(R409(TP1),
TWL5034POWER_ON_SW_
POWER_ON_SW_ pin(A11))
pin(A11)) TWL5034
Power
UpUp
PWRkey
keypress
pressPM_ON_SW_N
PM_ON_SW_N
(R409, TWL5034
TWL5034
Power
REGEN
1.8V_MMC_EN(C456_TP2)
1.8V_CSI2(C454_TP4),
3.0V_MOTION
(C452_TP5), 1.8V_
REGEN
1.8V_MMC_EN(C456)
1.8V_VIO(L404_TP3),
1.8V_VIO(L404), 1.8V_CSI2(C454),
3.0V_MOTION
(C452),
AUDIOAMP(C460_TP6)
VDD1_CORE(L402_TP7)
VDD2_CORE(L403_TP8)
1.8V_VPLL1(C459_TP9)
OMAP_PWR_
1.8V_AUDIOAMP(C460) VDD1_CORE(L402) VDD2_CORE(L403) 1.8V_VPLL1(C459) OMAP_PWR_RESET
RESET
goes high!
goes high!
- 137 -

4. TROUBLE SHOOTING
START
Battery voltage higher than

3.70V(OCV)?
No
Change or charging the Battery
Yes
Press PWR Key R409(TP1)
high to low
No
Check the USB FPCB
Yes
Power Key is Damaged?
No
Change USB FPCB
Yes
TP2, TP3, TP4,
TP5, TP6, TP7, TP8, TP9,
Power up?
No
Change the Main board
Yes
is clock OK?
X402: 32.768Khz
No
Change the TCXO and X-tal
Yes
- 138 -

4. TROUBLE SHOOTING
BOTTOM view of LGP970
C456 (TP2)
C454 (TP4)
L402
(TP7)
C459(TP9)
C460 (TP6)
C452 (TP5)
X601
L404
(TP3)
L403
(TP8)
TOP view of LGP970

R409 (TP1)
- 139 -

4. TROUBLE SHOOTING
4.10 Charger Troubleshooting

Since LGP970 micro USB is located at the TOP of the terminal set, charging current flows via USB FPCB.
The charger IC accepts the current and maximum charging current is set around 945mA.
CHARGER IC
uUSB Connector
VCHG
CN101
TP1
USB_VBUS
14
C506
1
2
USB_DM
USB_DP
USB_ID
3
4
11
1u
R505
ISET
GND1
LDO
IEOC
BATT
U502
PGB
CHGSB
GND2
EN_SET
11
10
TP2
9
8
CHG_STATUS_N_OMAP
7
6
CHG_EN_SET_N_OMAP
C511
2.2u
2K
C512
560
15
R504
13
PGND
VIN
100K
1u
R501
12
1.8V_VIO
100K
8
10
VBAT
R506
VCHG
USB
Main
Battery
Close to batt. connector
Check Point
- Connection of TA or USB Cable
- Charging current path(RT9524)
- Battery
Troubleshooting Setup
- Connect TA and battery to the phone
Charging Procedure
- Connect TA or u-USB Cable
- Control the charging current by RT9524 IC
- Charging current flows into the battery
Troubleshooting Procedure
- Check the charger (TA or USB Cable) connector
- 140 -

4. TROUBLE SHOOTING
START
Check the pin and battery

Connect terminals of I/O connector
Connection OK?
No
Change I/O connector
Yes
Is the u- USB Cable
voltage 4.8V (or 5.0V)?
No
Change TA (or u-USB cable)
Yes
Is it charging properly
After turning on?
Yes
END
No
Check PMIC SMT status by X-ray
Exchange PMIC or Change the main
board and Retest
- 141 -

4. TROUBLE SHOOTING
TOP view of LGP970
C506 (TP1)
C511 (TP2)
U502
- 142 -

4. TROUBLE SHOOTING
4.11 USB Trouble shooting

The sequence of LGP970USB is,
USB connected to LGP970 USB_OUT_5V goes to 5V(FPCB) USB_D+ go to 3.3V USB_DATA is triggered
USB work
Block Diagram of USB & UART connection is shown below
{~s
UART_TX_SW
USB_ID
USB_ID
USB_DP_TWL
t|pj
UART_RX_SW
h
z
USB_DM_TWL
OMAP_U
UART_SW
UART3_R
RX_OMAP
UART3_T
TX_OMAP
US
SIF1_SW
UART1_TX_IPC
UART1_
_RX_IPC
h
w
OvthwP
USB_DM
USB_DM
USB_DP
USB_DP
CN1001
U705
UART_RX
CN904
UART_TX
|ziGmwji
kwZ{Gz
OpjZWXP
USB_DP_IFX
X
USB_DM_IFX
X
USIF1_TX_IFX
USIF1_RX_IFX
U2
p
Tn
Owti`_WXP
tGi
- 143 -

4. TROUBLE SHOOTING
START
Cable is inserted?
No
Insert cable
Yes
TP1(C502) is 5V?
Yes
Lower FPCB damaged?
Yes
Change Lower FPCB connector
No
USB_D+ is 3.3V?
No
Check U501
Yes
- 144 -

4. TROUBLE SHOOTING
uUSB Connector
VA903
VA904
ZD904
CN101
6
8
10
USB_DP
USB_DM
12
3
4
P3
P1
P4
P2
13
USB_ID
1
12
11
10
RCV_N
FL902
RCV_P
USB_DM
USB_DP
USB_ID
14
P6
14
CN904
PWR_ON_SW
P5 5
VCHG
3
4
5
FL901
IN
15
MUIC
39p
13
4.7u
ZD902
11
C930
C929
OUT
VCHG
GND1 GND2
VBAT
VCHG
C501
0.1u
C502
90ohm matching !!
D5
1u
TP1
C5
USB_DM
USB_DP
B5
B4
USB_ID
R502
B1
VB
BAT
COMN1
DN1
COMP2
DP2
UID
U501
MAX14526DEEWP
AUD2
SCL
IC
SDA
GND
B2
1u
AUD1
INT
C3
CAP
ISET
A4
USB_DM_TWL
USB_DP_TWL
90ohm matching !!
A5
B3
UART_RX
UART_TX
A3
A1
D4
D3
A2
C2
C513
MIC
C1
C4
U2
RES
2.2K
D1
U1
D2
1.8V_VIO
100K
I2C2_SDA
I2C2_SCL
MUIC_INT_N
R503
90ohm matchingUSB_VBUS
!!
PWR_ON_SW
10K
R409
VBAT
R8
T10
USB_DP_TWL
USB_DM_TWL
3.1V_VUSB
T11
R11
D4
I2C1_SDA
I2C1_SCL
SYS_IRQ_N
D5
F10
F9
A11
PWR_WARM
OMAP_PWR_RESET
B13
A13
C432
1u
N16
C13
VBAT
1.8V_VIO
- 145 -
R407
10K
R408
K11
J11
H8
VBUS
DP
DN
ID
I2C_CNTL_SDA
I2C_CNTL_SCL
INT1
INT2
PWRON
NRESWARM
NRESPWRON
VREF
SYSEN
BOOT0
BOOT1
MSECURE
10K

4. TROUBLE SHOOTING
C520 (USB_VBUS)
TP1 (C502)
- 146 -

4. TROUBLE SHOOTING
4.12 Audio trouble

4.12.1 Speaker troubleshooting
Speaker control signals are generated by TWL5034 (U402), amplified by WM9093 (IC601), and Power is supplied by
Battery (VBAT).
START
Reconnect ANT. FPCB.

and check the speaker sound.
Spker sound is OK?
Yes
END
No
Change the speaker module
Yes
Check the waveform of TP1.

Waveform is OK?
No
Change the ANT. FPCB.
Speaker sounds OK?
Yes
END
No
Waveform is OK?
Yes
Change the Main PCB
Change the Audio codec IC
Speaker sound OK
END
- 147 -

4. TROUBLE SHOOTING
SPK
TP101
SPK_P
TP102
SPK_N
TP1
VA103
VA104
FB601
SPK_P
SPK_N
FB602
C613
C614
0.1u
0.1u
20
R605
20
R604
TP2
R601
R602
- 148 -
EAR_L
EAR_R

4. TROUBLE SHOOTING
4. 12.2 Receiver troubleshooting

Receiver control signals and power are generated by TWL5034 (U402).
START
Reconnect USB FPCB.

and check the speaker sound.
Spker sound is OK?
Yes
END
No
Change the receiver
Yes

Waveform is OK?
No
Waveform is OK?
Yes
Change the USB FPCB
Change the Main PCB
Speaker sound OK
END
- 149 -

4. TROUBLE SHOOTING
RCV
CN104
RCV_P
RCV_N
TP1
VA903
CN904
VA904
ZD904
14
PWR_ON_SW
2
13
12
11
10
USB_ID
TP2
RCV_N
RCV_P
- 150 -

4. TROUBLE SHOOTING
4.12.3 Main MIC troubleshooting

Main MIC control signals and power are generated by TWL5034 (U402).
START
Reconnect the ANT. FPCB.

and check the Main MIC.
Voice recording is OK?
Yes
END
No
Change the ANT. FPCB
Yes
Check the TP1.

Bias range 1.8V~2.2V
OK?
No
Change the Main PCB
Voice recording is OK
END
- 151 -

4. TROUBLE SHOOTING
Main MIC
O
G2
G1
P
MIC1P
MIC1N
4
3
TP1
MICBIAS
MIC101
VA107
VA108
As close as to MIC, Not in the ANT Carrier
- 152 -

4. TROUBLE SHOOTING
4.12.4 SUB MIC troubleshooting

Sub MIC control signals and power are generated by TWL5034 (U402).
START
Reconnect the VCAM FPCB.

and check the Sub MIC.
Speaker phone call is OK?
Yes
END
No
Check the TP1.
OK?
No
Change the VCAM PCB
Speaker phone call is OK

END
- 153 -

4. TROUBLE SHOOTING
L901
47p
R920
FB902
1800
38
37
FB903
1800
36
35
34
33
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
R915
C923
4.7u
R919 DNI
39
PROX_OUT
2.8V_PROXI
1.8V_VIO
ZD905
EAR_GND
FB901
EJ_MIC
FM_ANT
EAR_DETECT
C912
40
R916
KEY_LED_HIGH
VT_DATA[7]
VT_DATA[6]
VT_DATA[5]
VT_DATA[4]
VT_DATA[3]
VT_DATA[2]
VT_DATA[1]
VT_DATA[0]
1800
1
10
MIC2N
MIC2P
C922
- 154 -
C921
LSENSOR_SENS
10u
MICBIAS2
TP1
LSENSOR_BIAS
I2C3_SDA
I2C3_SCL
VT_VSYNC
VT_HSYNC
VT_CAM_DRV_2.8V
C924
C925
DNI
DNI
VT_CAM_IO_1.8V
100
R917
R918
VT_MCLK
VT_PCLK
VT_CAM_PWDN
VT_RESET_N
R913
C918
DNI
VA906
1u
ZD901
47K
C919
33p
ZD903
47p
100K
47p
R914
0.1u
CN903
6
R911
HOOK_ADC
EAR_L
EAR_R
VA905
C911 C913 C914

4
0.1u
R910
C908
2.2K
4.7u
D901
C926
EAR_MICBIAS

4. TROUBLE SHOOTING
4.12.5 Ear-MIC troubleshooting

Ear MIC control signals are generated by TWL5034 (U402), amplified by WM9093 (IC601). The power is generated by
external LDO (U403) which is controlled by OMAP3630 (U301).
START
Reconnect the VCAM FPCB. and check the Headphone Sound & MIC.
Ear sound is OK?
Yes
No
Yes
Hook detect is OK?
No
Check the TP1.

OK?
No
Ear sound is OK?
Yes
Check the
waveform of TP1.
Waveform is OK?
Yes
END
No
Yes
Check the TP3.

Bias range 1.0~1.4V
OK?
No
Yes
Change the VCAM

FPCB
No
Check the Audio LDO or Audio subsystem IC or Main PCB
All sounds OK
END
- 155 -

4. TROUBLE SHOOTING
AUDIO LOD
VBAT
4
3
EAR_MICBIAS_EN
VIN
STBY
VOUT
GND
TP1
1
2
C5031
PGND
U403
1u
EAR_MICBIAS
C5032
C5033
1u
33p
TP2
C912
L901
47p
39
FB902
1800
38
37
FB903
1800
36
35
34
33
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
R915
C923
4.7u
R919 DNI
PROX_OUT
2.8V_PROXI
1.8V_VIO
ZD905
EAR_GND
40
FB901
R916
KEY_LED_HIGH
VT_DATA[7]
VT_DATA[6]
VT_DATA[5]
VT_DATA[4]
VT_DATA[3]
VT_DATA[2]
VT_DATA[1]
VT_DATA[0]
1800
1
10
C919
33p
MIC2N
MIC2P
VA906
C922
10u
MICBIAS2
LSENSOR_SENS
LSENSOR_BIAS
I2C3_SDA
I2C3_SCL
VT_VSYNC
VT_HSYNC
VT_CAM_DRV_2.8V
- 156 -
C924
C925
DNI
DNI
VT_CAM_IO_1.8V
100
R917
R918
VT_MCLK
VT_PCLK
VT_CAM_PWDN
VT_RESET_N
R913
C918
DNI
C921
1u
ZD901
47K
EJ_MIC
FM_ANT
EAR_DETECT
R920
CN903
47p
ZD903
47p
100K
0.1u
R914
TP3
VA905
C911 C913 C914

6
HOOK_ADC
EAR_L
EAR_R
R911
0.1u
R910
C908
2.2K
4.7u
D901
C926
EAR_MICBIAS

4. TROUBLE SHOOTING
TP1_C5032
TP3_C908
TP2_C914
- 157 -

4. TROUBLE SHOOTING
4.13 Camera troubleshooting

5M camera control signals are generated by AP_OMAP3630(U301), and Power is supplied by LP8720(U601)
START
Check the camera conn.

and revonnect thr camera
Camera is OK?
Yes
END
No
No
Check IOVDD(TP1),
DVDD(TP2), AVDD(TP3)
Yes
Change the main board
No
Check the camera signals MCLK(TP4),

MIPI_CLK(TP5), MIPI_DATA(TP6)
Yes
Change the camera
Camera is OK?
- 158 -
Yes
END

4. TROUBLE SHOOTING
1.2V_5M_VDIG
1.8V_5M_VIO
CN602
FL602
TP6
1
P1
2
P2
3
P3
4
P4
G2
10
G1
9
5M_MIPI_DATA0_N
5M_MIPI_DATA0_P
5M_MIPI_DATA1_N
5M_MIPI_DATA1_P
5
P5
6
P6
7
P7
8
P8
24
23
22
21
20
19
18
17
16
10
15
11
14
12
13
I2C3_SDA
I2C3_SCL
0.1u
5M_RESET_N
5M_CAM_VCM_EN
2.8V_5M_VCM
0.1u
TP4
2.7V_5M_VANA
1
P1
2
P2
3
P3
4
P4
P5
6
P6
7
P7
8
P8
0.1u
5M_MCLK
FL601
G2
10
G1
9
5M_MIPI_CLK_N
5M_MIPI_CLK_P
TP5
5
C622
1u
0.1u
C625
C624
C621
4.7u
ZD601
C623
TP2 TP3 TP1
C620
- 159 -

4. TROUBLE SHOOTING
4.13.1 Sub 2M Camera troubleshooting

2M camera control signals are generated by AP_OMAP3630(U301), and Power is supplied by TWL5034(U402)
VT_CAM_DRV_2.8V VT_CAM_IO_1.8V
VT_DATA[7]
VT_DATA[6]
VT_DATA[5]
VT_DATA[4]
6
7
8
9
CN103
24
23
22
21
20
19
18
17
16
10
15
11
14
12
13
I2C3_SCL
FL102
G1
G2
10
7.5pF
I2C3_SDA
INOUT_B4
INOUT_A4
INOUT_B3
INOUT_A3
INOUT_B2
INOUT_A2
INOUT_B1
INOUT_A1
4
3
2
VT_VSYNC
6
7
8
9
10
VT_MCLK
FL103
G1
G2
VT_DATA[3]
VT_DATA[2]
VT_DATA[1]
VT_DATA[0]
VT_HSYNC
7.5pF
VT_PCLK
INOUT_B4
INOUT_A4
INOUT_B3
INOUT_A3
INOUT_B2
INOUT_A2
INOUT_B1
INOUT_A1
4
3
2
1
VT_RESET_N
VT_CAM_PWDN
TP2
TP1
1u
C101
1u
C102
47K
L901
47p
R920
FB902
1800
38
37
FB903
1800
36
35
34
33
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
R915
C923
4.7u
R919 DNI
39
PROX_OUT
2.8V_PROXI
1.8V_VIO
ZD905
EAR_GND
FB901
EJ_MIC
FM_ANT
EAR_DETECT
C912
40
R916
KEY_LED_HIGH
VT_DATA[7]
VT_DATA[6]
VT_DATA[5]
VT_DATA[4]
VT_DATA[3]
VT_DATA[2]
VT_DATA[1]
VT_DATA[0]
1800
1
10
C919
33p
MIC2N
MIC2P
VA906
C922
10u
MICBIAS2
LSENSOR_SENS
LSENSOR_BIAS
I2C3_SDA
I2C3_SCL
VT_VSYNC
VT_HSYNC
VT_CAM_DRV_2.8V
- 160 -
C924
C925
DNI
DNI
R917
VT_CAM_IO_1.8V
R918
VT_CAM_PWDN
VT_RESET_N
R913
C918
DNI
C921
1u
ZD901
CN903
47p
ZD903
47p
100
100K
0.1u
TP3
0
VT_MCLK
VT_PCLK
TP4
R914
HOOK_ADC
EAR_L
EAR_R
VA905
C911 C913 C914

6
R911
0.1u
R910
C908
2.2K
4.7u
D901
C926
EAR_MICBIAS

4. TROUBLE SHOOTING
4.14 Main LCD trouble

Main LCD control signals are generated by OMAP3630. Those signals path are : OMAP3630-> LCD Module
START
Press PWR key turn the power On
Is the circuit powered?
No
Follow the Power ON

trouble shooting
Yes
Disconnect and reconnect
LCD connector
LCD display OK?
Yes
No
Change the LCD module
Yes
Check Power
VCC_LCD_1V8
VCC_LCD_2V8
V_POWERALL
No
Yes
The LCD works
END
- 161 -

4. TROUBLE SHOOTING
VBAT
VBAT line minimum 0.6mm

C701
2.2u
C702
2.2u
1.8V_VIO
1u
B5
C2-
FLTR
BL8
LDOA
B3
SBIAS
LDOB
C1
AMB_IN
LDOC
PGND2
E2
F1
A1
B1
1.8V_LCD_IOVCC
3.0V_LCD_VCC_VCI
B2
1.8V_TOUCH
A2
3.0V_TOUCH
F3
PGND1
AGND2
E1
C5
AGND1
2.2u
R706
LDOD
IN_LDO
A3
68n
C713
100K
C712
A4
F2
2.2u
C2
E3
2.2u
BL7
E4
C711
BL6
F4
2.2u
BL5
LCD_BL_OUT1
LCD_BL_OUT2
LCD_BL_OUT3
LCD_BL_OUT4
LCD_BL_OUT5
LCD_BL_OUT6
LCD_BL_OUT7
LCD_BL_OUT8
E5
C710
BL4
U701
BC_M
F5
2.2u
BL3
C709
BL2
SDA
SCL
D1
LSENSOR_SENS
EN
D5
C708
D3
LSENSOR_BIAS
NEG
BL1
C3
LCD_PWM
C2+
B4
R704
IN
D2
LCD_CP_EN
I2C2_SDA
I2C2_SCL
C1-
C1+
100K
A5
C4
C704
1u
D4
C703
VBAT
3.0V_LCD_VCC_VCI
1.8V_LCD_IOVCC
FL702
1
P1
2
P2
3
P3
4
P4
CN702
30
29
28
27
26
25
24
23
22
10
21
11
20
12
19
13
18
14
17
15
16
INOUT_A3
INOUT_B4
INOUT_A4
LCD_PWM
10
15pF
LCD_BL_OUT4
LCD_BL_OUT3
LCD_BL_OUT2
LCD_BL_OUT1
LCD_BL_OUT8
LCD_BL_OUT7
LCD_BL_OUT6
LCD_BL_OUT5
P3
P1
P4
P2
1
2
LCD_MIPI_CLK_P
LCD_MIPI_CLK_N
FL703
TP2
C720
C715
C714
4.7u
2.2u
2.2u
TP3
P5 5
INOUT_A2
INOUT_B3
G2
INOUT_B2
P6
INOUT_A1
G1
INOUT_B1
LCD_TE
LCD_CS
LCD_RESET_N
FL701
LCD_MIPI_D0_P
LCD_MIPI_D0_N
LCD_MIPI_D1_P
LCD_MIPI_D1_N
9
G1
10
G2
LCD_MAKER_ID
5
P5
6
P6
7
P7
8
P8
TP1
A20
NC45
A10
NC40
A17
SDRC_DQS1
A6
NC38
AG22
AH22
AG23
AH23
AG24
AH24
E26
F28
F27
G26
AD28
AD27
AB28
AB27
AA28
AA27
G25
LCD_MIPI_D0_P
LCD_MIPI_D0_N
LCD_MIPI_D1_P
LCD_MIPI_D1_N
LCD_MIPI_CLK_P
LCD_MIPI_CLK_N
- 162 -
DSS_DATA0
DSS_DATA1
DSS_DATA2
DSS_DATA3
DSS_DATA4
DSS_DATA5
DSS_DATA6
DSS_DATA7
DSS_DATA8
DSS_DATA9
DSS_DATA10
DSS_DATA11
DSS_DATA12
DSS_DATA13
DSS_DATA14
DSS_DATA15
DSS_DATA16

4. TROUBLE SHOOTING
703 702TP2
701 TP3
TP1
signal check
point
- 163 -

4. TROUBLE SHOOTING
4.15 SIM
4.15
SIM detect
detectTrouble
Troubleshooting
shooting
The sequence of detecting LGP970 SIM is,
SIM inserted to LGP970 2.85V_SIM goes to 2.85V(SUB FPCB) Triggers SIM clock, reset and data.
Block Diagram of USB & UART connection is shown below
G
SIM_RSTG
SIM_CLK
CLKG
USIMG
RSTG
SIM_IO
I_OG
CC_CLK
MP-EHMG
CC_RST
CC_IO
XMM6160
zG
START
Re-insert the SIM card

yTGGzptG
~Gf
Work
well?
No
l END
uG
YU_\}zptGf
2.85V_SIM (TP1_C214) runs?

Yes
Yes
Nouv
jGGG
G G
lz
Change
SUB FPCB
jGz|iGmwji
Work
well?
~Gf
No
Yes
l END
uG
jGzptGG
Change SIM card G G G
~Gf
Work well?
No
Yes
END
jGtG
Change Main board
- 164 -

PMUMEAS
VDD_LVDS
VANA1
VANA2
VSS_ANA
VDD_VBAT_LDO
VDD_OSD2
VRF2
VDD_VBAT_RF12_1
VRF1
VDD_VBAT_RF12_2
VSS_RF12
VMIPI
VDD_VRTC
VDD_VPLL
VDD_VSIM
VDD_VUSB
VDD_VPMU
DIF_D0
DIF_D1
DIF_D2
DIF_D3
DIF_D4
DIF_D5
DIF_D6
DIF_D7
DIF_D8
DIF_D9
DIF_CS1
DIF_CS2
DIF_CD
DIF_WR
DIF_RD
DIF_HD
DIF_VD
DIF_RESET1
DSI_DP1
DSI_DN1
DSI_CLKP
DSI_CLKN
NC_9
NC_10
NC_11
NC_12
D12
G16
F18
B16
E16
E14
D15
B15
A16
D14
C15
F16
G17
E13
F19
E15
F17
P5
R1
P2
P1
N7
M6
N5
N4
N2
N1
M8
M7
M5
M4
M2
M1
N8
P4
Y13
Y14
Y11
Y12
A1
Y1
A20
Y20

1.2V_MIPI
2.3V_RTC 1.35V_PLL 2.85V_SIM 3.1V_USB
C203
C204 C205
C206
C207
C208
C211
C212
C213
C214
100n 10u
C209 C210
220n
220n
1u
C215
C216
1u
100n 10u
220n
0.1u
220n
1u
0.1u
0.1u
- 165 -
R205
1.8V_SD 2.85V_RF2 2.85V_RF1
390K
2.5V_ANA2
220K
VBAT
R206
4. TROUBLE SHOOTING
VBAT
IFX_USB_VBUS
TP1
C202
220n
IPC_MRDY
IPC_SRDY
MODEM_AP_WAKE
MODEM_WAKE
MODEM_PWR_CHK
MODEM_CHK

4. TROUBLE SHOOTING
USIM For Infinieon

4.7K
2.85V_SIM
R112
J101
4
5
6
SIM_IO
22p
10
VCC
VPP
RST
IO
CLK
GND5
GND2
GND4
GND3
1
2
SIM_RST
SIM_CLK
3
7
8
D 103
C105
GND1
C106
C107
C108
DNI
0.1u
18p
Main 2 Sub
VBAT
2.85V_SIM
3.0V_MOTION
1.8V_MOTION_VIO
1.8V_VIO
GYRO_INT_N
COM_INT
MOTION_INT
PWR_ON_SW
SIM_RST
SIM_CLK
SIM_IO
I2C3_SCL
I2C3_SDA
40
39
38
37
36
35
34
33
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
FLASH_LED_TORCH
FLASH_LED_EN
GSM_TXON_IND
UART_TX_IFX
UART_RX_IFX
MICROSD_CMD
MICROSD_CLK
MICROSD_DAT0
MICROSD_DAT1
MICROSD_DAT2
MICROSD_DAT3
MICROSD_DET_N
TDO
TDI
TCK
TMS
TRSTN
TRIG_IN
HW_MON1
HW_MON2
DSP_AUDIO_IN1
26MHz_GPS_REF
SIM_CLK
SIM_RST
SIM_IO
H13
L14
L13
M14
M13
G11
E10
F12
E12
E11
L8
L7
R9
L5
U10
T10
H10
H9
G5
E8
E2
E1
F9
M5
M6
M7
M8
M9
M10
CC_CLK
CC_RST
CC_IO
DPLUS
DMINUS
TDO
TDI
TCK
TMS
TRST_n
TRIG_IN
HW_MON1
HW_MON2
DSP_AUDIO_IN1
CLKOUT0
T_OUT0
T_OUT1
KEY_C[0]
KEY_R[0]
KEY_R[1]
KEY_R[2]
3.0V_MMC
CN101
- 166 -

4. TROUBLE SHOOTING
C214 (2.85V_SIM)
TP1(C214)
- 167 -

4. TROUBLE SHOOTING
4.16 Side Key Trouble shooting

The sequence of detecting LGP970 Side key is,
Side key pressed on LGP970 KEY_R[0](Volume up), KEY_R[1](Volume_down), KEY_R[2](Gesture KEY) goes low
Block Diagram of Side key connection is shown below
KEY_R[0]
KPD_R0
KEY_R[1]
KPD_R1
KEY_R[2]
KPD_R2
KEY_C[0]
KPD_C0
TWL5034
START
Press the key
Side Key is worked?
Yes
END
No
TP1_R111
(SUB FPCB) goes low when
the key is pressed?
END
No
LOWER FPCB damaged?
Yes
Change LOWER FPCB
No
- 168 -

4. TROUBLE SHOOTING
KB1
R108
150
R109
150
R110
150
R111
150
KEY_R[0]
Vol. Up
KEY_R[1]
Vol. Down
KEY_R[2]
Gesture
KB2
KB3
KPD_C7
KPD_C5
H6
G4
KPD_C3
KPD_C4
F4
KPD_C2
F7
G7
KPD_C0
KPD_R7
KPD_C1
G6
H7
KEY_C[0]
G8
KPD_R6
L7
KPD_R4
KPD_R5
J10
K10
KPD_R2
KPD_R3
L9
KPD_R1
L8
K7
KPD_R0
K8
K9
KEY_R[0]
KEY_R[1]
KEY_R[2]
KPD_C6
KEY_C[0]
TP1
TP1
- 169 -

4. TROUBLE SHOOTING
4.17 Vibrator Troubleshooting

Check out the setting menu on the phone. If not, check Test points shown on the pictures.
START
Turn on the phone
Is the circuit powered?
No
Follow the Power ON

trouble shooting
Yes
Check Haptic Feedback on the
setting menu
Vibration OK?
Yes
No
Change the vibrator
Yes
Check TP1(C517)
No
Vibrator works
END
- 170 -

4. TROUBLE SHOOTING
- 171 -

4. TROUBLE SHOOTING
DNI
R510
3.0V_MOTOR
U504
GND
MODE
VDD
GAIN
VDN
VIB_P
7
6
5
VIB_N
TP1
C517
2.2u
R516
10
NC3
PWM
11
VDP
NC1
EN
NC2
VIBE_EN
VIBE_PWM
C519
1%
10n
DNI
R517
Q-Motor
VB101
1
VIB_P
VIB_N
SJMY0007118
- 172 -

4. TROUBLE SHOOTING
4.18 Motion sensor troubleshooting

When the motion sensor does not work, the reason is chip problem. If the motion sensor IC is damaged, it will do not
work even thought power is supplied and OMAP3630 controls normally.
Therefore if the motion sensor is damaged, change the motion sensor IC or SUB-FPCB.
START
Motion sensor function check

(Screen rotation function is
Working or not?)
Function is OK?
Yes
END
Change the IC (U104)
Function is OK?
Yes
END
Change the SUB-FPCB
Function is OK?
Yes
END
- 173 -

4. TROUBLE SHOOTING
3.0V_MOTION
C123
1
C118
0.1u
GND
DNC2
DNC1
DNC3
INT
U104
IO_VDD
DNC4
SCL
MOTION_INT
IME_CL
SDA
10
1.8V_MOTION_VIO
VDD
0.1u
IME_DA
U104 (KXTF9)
Motion Sensor
- 174 -

4. TROUBLE SHOOTING
4.19 Gyro/Compass sensor troubleshooting

The compass sensor is calibrated by the gyro sensor data using SW algorithm.
Therefore Gyro sensor error makes the compass sensor malfunction.
START
Gyro & compass sensor function check
Gyro & Compass

Function is OK?
Yes
END
No
Yes
Gyro-NG Compass-OK?
No
Gyro-OK
Compass-NG?
Yes
END
No
Change the Compass
sensor IC (U105)
Change the Gyro sensor IC (U103)
Function is OK?
Yes
END
No
Change the Gyro sensor IC (U103)
No
Function is OK?
Yes
END
No
Change the SUB-FPCB
Function is OK?
Yes
END
END
- 175 -

4. TROUBLE SHOOTING
1.8V_MOTION_VIO
REGOUT
NC 1
CLKIN
NC2
NC3
CLKOUT
RESV2
INT
CPOUT
13
VDD
3.0V_MOTION
GND
FSYNC
NC8
GYRO_INT_N
U103
RESV1
25
24
I2C3_SDA
I2C3_SCL
23
22
21
20
19
C115
2.2n
18
12
SCL
17
11
SDA
AD0
NC7
10
VLOGIC
16
0.1u
NC9
IME_CL
15
C121
NC4
6
8
NC6
IME_CL
14
NC5
0.1u
IME_DA
C122
IME_DA
C120
1.8V_MOTION_VIO
3.0V_MOTION
COM_INT
0.1u
C116
CAD1
C1
VSS
C2
TST2
C3
TST6
RSV
VDD
A4
SCL/SK
A3
A1
SO
B4
3.0V_MOTION
U105
SDA/SI
TST1
I2C3_SDA
D4
CAD0
CS B
D2
A2
D1
DRDY
C4
VID
R117
10K
0.1u
B3
B1
C117
0.1u
1.8V_MOTION_VIO
I2C3_SCL
C119
0.1u
- 176 -

4. TROUBLE SHOOTING
- 177 -

4. TROUBLE SHOOTING
4.20 Proximity Sensor on/off trouble

Proximity Sensor is worked as below:
Send Key click Phone number click Call connected Object moved at the sensor
Control the screens on/off operation automatically
START
Send Key click & call connected
Object moved at the Proximity Sensor
Yes
LCD off?
No
Check PROXI_SDA /
SCL output & Prox_out
No
Change the upper FPCB
Yes
Work well?
No
Yes
END
Measurement
PROXI_VCC
1.8V_VIO
PROXI_LEDA
PROX_OUT (TP3)
I2C3_SCL (TP1)
I2C3_SDA (TP2)
- 178 -

4. TROUBLE SHOOTING
PROXI_VCC
1.8V_VIO
PROXI_LEDA
U102
1
PROX_OUT
C106
TP3
C107
4.7u
0.1u
LEDA
SCL
LEDC
SDA
VCC
VIO
VOUT
GND
- 179 -
TP1
I2C3_SCL
I2C3_SDA
TP2
C105
1u

4. TROUBLE SHOOTING
4.21 Illumination Sensor on/off trouble

Illumination Sensor is worked as below:
Menu Key click Settings click Display click Brightness click Automatic brightness click
START
Automatic brightness click
Hide Illumination sensor by hand
Yes
LCD brightness change?

No
Check TP1,2
(LSENSOR_BIAS/SENS)
No
Change the VT_CAM FPCB
Yes
Work well?
No
Yes
END
Measurement
LSENSOR_BIAS (TP2)
LSENSOR_SENS (TP1)
- 180 -

4. TROUBLE SHOOTING
U101
TP1
VCC
GND1
GC2
GC1
1TP2
LSENSOR_BIAS
IOUT
GND2
LSENSOR_SENS
- 181 -

4. TROUBLE SHOOTING
4.22 Touch trouble

Touch control signals are generated by AP20. Those signals path are : AP20 -> Touch Module
START
Check the touck connector and

reconnect the touck connector
Touch is OK?
Yes
END
No
Check power
3.0V TOUCH (TP1)
1.8V TOUCH (TP2)
No
Yes
Work well?
No
Change the touch module
Yes
END
Measurement
3.0V TOUCH (TP1)
1.8V TOUCH (TP2)
- 182 -

4. TROUBLE SHOOTING
1.8V_TOUCH
1.8V_TOUCH
R703
10K
3.0V_TOUCH
10
CN701
TP2
TOUCH_INT_N
9
5
C705
I2C2_TOUCH_SDA
0.1u
TP1
- 183 -
C707
ZD703
ZD702
ZD701
0.1u
I2C2_TOUCH_SCL

5. DOWNLOAD
5. DOWNLOAD
- 184 -

5. DOWNLOAD
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
- 185 -

5. DOWNLOAD
LG-P970
LG-P970
- 186 -

5. DOWNLOAD
LG-P970
- 187 -

5. DOWNLOAD
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
- 188 -

5. DOWNLOAD
LG-P970
- 189 -

5. DOWNLOAD
- 190 -

5. DOWNLOAD
- 191 -

5. DOWNLOAD
- 192 -

5. DOWNLOAD
- 193 -

5. DOWNLOAD
- 194 -

5. DOWNLOAD
- 195 -

5. DOWNLOAD
- 196 -

5. DOWNLOAD
- 197 -

5. DOWNLOAD
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
- 198 -
LG-P970
LG-P970
LG-P970
LG-P970

5. DOWNLOAD
LG-P970
LG-P970
LG-P970
- 199 -

5. DOWNLOAD
LG-P970
LG-P970
- 200 -

5. DOWNLOAD
LG-P970
LG-P970
LG-P970
LG-P970
LG-P970
- 201 -

5. DOWNLOAD
LG-P970
LG-P970
- 202 -

6. Block Diagram
6.Block diagram
B project Block Diagram

VT Cam
Camera
2M
5M MIPI
EDGE
26M
PCM UART SDIO
m
nzt
l
wht
t
Bluetooth
transceiver
PMB5703
Wi-Fi FM
Di3 RF I/F
WCDMA
MCP(CP)
Dg x
GPIO
I2C
USIF3
USIF
USB
PCM
MEM_AD
MEM_A
CC_000
Duplex
I2C_MODEM 2
wti`_WX
UMTS
PAM
UART2 CSI2 I2C3 CAM IF I2C3

UART1
SDIO
NCS
MCP(AP)
PCM
X32
SDRC
X16
GPMC
4Gb DDR
SDRAM
I2C2
USIM
I2C
USB DP/DM tWL

|ziGpm
|hy{Gvthw
Charger
IC
MUIC
Battery
(1500mAh)
Fuel gauge
|hy{Gy{
HS USB data
GPIO
HS USB data
INT1
|hy{Gz~
DP/DN
PCM
LCD Backlight
Motion
MMC1
eMMC
(2GB)
Driver
TWL5034
I2C3
Gyro
Compass
Key LED
Driver
I2C1 I2C4
I2S
I2C2
LCD BL Charge Pump
Proximity sensor
GPIO for PWM
UART3_TX_IRRX/TX
UART4 (GPMC_WAIT)
16
Touch Screen
Hall IC
OMAP3630
I2C2
Address
Touch Driver
AMBIENT
MMC2
1Gb NAND
Touch module
Mounted
M
t d on
OMAP3630
16
512Gb DDR
SDRAM
LCD 4.0
WVGA (800X480)
DSS_DAtA
I2C2
GPIO
I2C
SPI2
I2C1
I2C2
I2C3
A-GPS
KPD
Key
Audio
Subsystem
EAR_MIC
MAX17040
- 203 -

6. Block Diagram
rF Block Diagram
FEM
with
GSM
FSY2_CLK
PAM
VCTCXO
26MHz
SKY77529
XO
VCONT
G850/G900
TX_LB
TX_HB
AFC_DAC
DCS/PCS
DET
W900
Duplexer
RXTX_L2
WCDMA
Dual PAM
ACPM-5281
W2100
Duplexer
RXTX_H
CPL
W1900
Duplexer
RXTX_M1
F26M
SYS_CLK
TX2G_L
TX2G_M
W-PAM
ACPM-5202
CPL
WCDMA
TX SAW
TX_3G_L
WCDMA
TX SAW
TX_3G_H
WCDMA
TX SAW
TX_3G_M
DI3_TX_DAT
DI3_TX_DATX
Di3_TX_DAT
Di3_TX_DATX
DI3_RX_DAT
DI3_RX_DATX
Di3_RX_DAT
Di3_RX_DATX
MP-eHM
transceiver
PMB9801
PMB5703
PWR DET
PA_POW_DET
RFIN1
1900
RX SAW
LNA
RFIN4BGA749

RX_M2X
2100
RX SAW
RX_H
RX
H
~GYXWW
RX_HX
RFIN5
900
RX SAW
RX_L1
~MnG`WW
RX_L1X
RX SAW
RX_L2
nG_\W
RX_L2X
RFIN2
RX_M2
RX_L1
RX_M3
850
1800
RX SAW
RX_M1 nGX_WW
RX_M1X
- 204 -
VDD_MAIN
VDD_FSYS
VDD_IO
2.85V_RF1
2.85V RF2
2.85V_RF2
1.8V_SD
VRF1
VRF2
VSD2

6. Block Diagram
Power Block Diagram

tA (5PiN)
5.1v,700mA
vCHG
TWL5030
USB_vBUS
vBUS
Charger iC USB
vBUS
(rt9524)
vBAt
CP_iN
(40mA)
vAUX4_oUt
1 500 Ah
1,500mAh
(100mA)
vSDi_CSi_oUt
(100mA)
MUiC
tS5USBA33402
vSiM_oUt
(100mA)
vDAC oUt
vDAC_oUt
(70mA)
Analog
g switch for
USIF1
(200mA)
vSD1_1
vSD1
(450mA)
(450mA)
vSD1_1
vSD2
(450mA)
(4450mA
(30mA)
vANA2
(60mA)
vrF1
(180mA)
vrF2
(60mA)
LNA for IFX
1.8v_MotioN_vi
1
8v MotioN vi
o
1.8v_MMC_eN
2 8v ProXi
vAUX1 oUt 2.8v_ProXi
vAUX1_oUt
vDD_vPLL)
PAM
1.8v_WLAN
(200mA)
PMB980
1
vMiPi
(60mA)
vDD_vrt
C
vDD_vUS
B(40mA)
1.3v_Core
1.8v_SD
1 35v PLL
1.35v_PLL
2.5v_ANA2
2.85v_rF1
2.85v_rF2
1.2v_MiPi
2.3v_rtC
vDDS_MMC1
3.0v MMC
3.0v_MMC
3.0v_MMC
SUB PMIC LDo1

(300mA)
CAM POWER
LDo2 3.0v_Motor
(300mA)
vBAt (LP8720)
vDDS_MeM
vDDS_DPLL_Per
SW
AUDIO SUBSYSTEM
WLAN+BT+FM
MOTION / GYRO
COMPASS
2.85v_SiM
- 205 -
(400mA)
1.2v_5M_vDiG
_ _
LDo3
(300mA)
PROXIMITY
SENSOR
5M CAM
LDo4 1.8v_5M_vio
(300mA)
LDo5 2.8v_5M_vCM
(300mA)
310mA
VT 2M CAM
MOTOR
DRIVE IC
2.7v_5M_vANA
eMMC LDO
GPS LDO
3.0v_USer_MeM
GPS_2.8v
USER
MEMORY
eMMC I/F
GPS
150mA
GPS_tCXo_1.8v
TCXO for
GPS
vDD_Core
vDD_DiG / MeM
AUDIO LDO
vDD_LvDS
eAr_MiCBiAS
_
150mA
vDD_MiPi_BGC
LeD1~8
vDD_MAiN
vDD_FSYS
LCD_BL_oUt[1:8]
LDoA 1.8v_LCD_iovCC 4.0

4.0 LCD
LCD BL
(300mA)
CHG PUMP LDoB 3.0v_LCD_vCC_vCi
(AAT2870) (150mA)
vDD_MiPi
LDoC
vDD_USB PMB9801
(150mA)
MEMORY
(150mA)
(for Infineon)
1G / 512Mb
(7mA)
Core
vDD_rtC
3.1v_USB
vDD_vPM
vDD
vPM
U
vANA1
vDD_vSiM
OMAP3630
MPU
vDDS_CSi2
1.8v_AUDioAMP
vMMC2_oU
t (100mA)
vMMC1_oU vt_CAM_Drv_2.8
v
t (220mA)
vAUX3_oUt vt_CAM_io_1.8v
Key LED DRIVER
SKY77529
1.8v_CSi2
vAUX2_oUt 3.0v_MotioN
38.4MHz for WLAN
PMB5703
1.8v_PLL1
(50mA)
Flash LED Driver
FUEL GAUGE IC
(600mA)
vPLL1_oUt
Battery
DP3T SWITCH
vDD1_Core
vDD1_Cor
e ((1.1A)) vDD2
vDD2_Core
Core
vDD2_Cor
e (600mA) 1.8v_vio
vio
USIM For
Infineon
LEVEL SHIFTER
LDoD
SBiAS
1.8v_toUCH
3.0v_toUCH
LSeNSor_BiAS
TOUCH
AMBIENT
LIGHT
SENSOR

7. CIRCUIT DIAGRAM
7. CIRCUIT DIAGRAM
47p
G1 O1
IN
G2 O2
2p
RX_1800_M1X
L101
FL101
5.6n
5 4
L126
C105
2p
C106
2p
RX_1800_M1
8.2n
GPS_GSM_CTL
GSM_TXON_IND
DRW
SS
CLK
VSPI
1842.5MHz
FL102
Band2 & PCS
L127
RX_1900
C5027
DNI
RFOUTM
C5029
33p
C108
2.4n
RX_1900_M2
O2
1
3
IN G1G2 O1
47p
L102
2 5
C110
C112
2p
RX_1900_M2X
1p
1960MHz
Band1
PA_MODE2
C114
8.2p
C118
8.2p
PA_MODE
C115
RFOUTH
47p
C116
47p
DNI
R103
R104
DNI
6.8n
RX_2100_H
DNI
C119
GSM850
C122
22p
L128
6.8n
8.2p
PAM
VMODE
For 2 mode CTRL
PA_MODE
NC
For 3 mode CTRL
PA_BIAS1
PA_MODE
VBP
G1 O1
IN
G2 O2
12n
C126
C125
8.2p
C130
8.2p
RX_1800_M1
RX_1800_M1X
RX_1900_M2
RX_1900_M2X
RX_2100_H
RX_2100_HX
RX_900_L1
RX_900_L1X
RX_850_L2
RX_850_L2X
RX_850_L2
881.5MHz
VBAT
RFOUTL
3.3n
G1 O1
IN
G2 O2
FL105
5 4
C132
R105
L105
15n
C133
8.2p
1K
ENWY0003901(Hirose)
PWR Detector
SW101
4
SW102
ANT
ANT
COMMON
G3
3
C142
PA_POW_DET
33p
G4
L108
L107
C143
DNI
27n
U101
E8
E9
D8
A11
A1
L11
L1
K4
ALERT_N_UE
J4
100
H11
close to
G10
F10
G11
F11
SYS_CLK
K11
SYS_CLK_EN
J7
REF_CLK_EN
K10
J8
L9
K9
1.8V_SD 2.85V_RF21.8V_SD
J11
L10
J10
K7
L7
L8
H7
C124
0.1u
K8
L4
G8 Close to U1000 L4-pin
E4
C127
C128
C129
F6
10n
10n
10n
D7
(0603) (0603) (0603)
D5
A6
J3
B7
H4
F3
C3
A3
B2
B3
B4
B6
B8
B9
C2
C4
C5
C6
C7
D2
D3
D4
D6
E2
E3
E5
E6
942.5MHz
G1
TESTPIN3
TESTPIN2
TESTPIN1
CB4
CB3
CB2
CB1
RESET_N
ALERT_N
TESTPIN7
DI3_TX_DATX
DI3_TX_DAT
DI3_RX_DATX
DI3_RX_DAT
SYS_CLK
SYS_CLK_EN
REF_CLK_EN
TESTPIN6
FSYS4
FSYS2_EN
FSYS3
FSYS2
FSYS3_EN
AFC_DAC
XO
XO_SUP
VDD_IO
VDD_FSYS
C_EXT
VDD_VAR
VDD0_MAIN
VDD9_MAIN
VDD8_MAIN
VDD7_MAIN
VDD6_MAIN
VDD5_MAIN
VDD4_MAIN
VDD3_MAIN
VDD2_MAIN
VDD1_MAIN
RESET_N_UE
DI3_TX_DATX
PMB5703
DI3_TX_DAT
DI3_RX_DATX
DI3_RX_DAT
Differential 100ohm
4
C120
C121
10n
2.2p
DSA221SCL
VCC
OUT
VCONT
GND
3
2
X101
Close to X1000 4-pin

26MHz
2.85V_RF1
RX_900_L1
DNI
G2
FE_CTRL6
FE_CTRL5
FE_CTRL4
FE_CTRL3
FE_CTRL2
FE_CTRL1
TX3G_M2
TX3G_M1
TX3G_H
TX3G_L
PA_BIAS2
PA_BIAS1
PA_RAMP
PA_BSEL
PA_MODE
PA_EN4
PA_EN3
PA_EN2
PA_EN1
PA_POW_DET
PA_DC_DET
TX2G_L
TX2G_M
LNA_CTRL4
LNA_CTRL3
LNA_CTRL2
LNA_CTRL1
LNA1INT_CTRL
LNA1_IN
LNA1_OUT
RX_M1
RX_M1X
RX_M2
RX_M2X
RX_H
RX_HX
RX_L2
RX_L2X
RX_L1
RX_L1X
MI2
MI1
GND0
GND1
GND2
GND3
GND4
G N D5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
Band8/EGSM
RX_900_L1X
2 3
L132
56p
GSM_TX
DCS_PCS_TX
LNA_CTRL4
LNA_CTRL3
LNA_CTRL2
LNA_CTRL1
1.5p
4.7n
10p
C113
L104
FL104
5 4
L106
C111
PA_POW_DET
RX_850_L2X
2 3
1
12p
PA_EN_1900
PA_EN_2100
PA_EN_900
2140MHz
RX_850
C109
PA_RAMP
L103
FL103
5 4
C117
R102
RX_2100_HX
2 3
G1 O1
IN
G2 O2
TX3G_M1_1900
TX3G_H_2100
TX3G_L_900
CPL_EN
5.6n
K6
L6
L5
K5
J5
J6
A7
A8
A9
A10
E11
E10
B11
D11
D10
C8
C9
C11
B10
C10
D9
B5
A5
G3
H3
K3
K2
L3
A4
A2
B1
C1
D1
E1
F1
G1
H1
J1
K1
L2
H10
G9
R101
C103
33p
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
C102
RX_1800
J9
J2
H9
H8
H6
H5
H2
G7
G6
G5
G4
G2
F9
F8
F7
F5
F4
F2
E7
C101
2 3
DCS
DNI
U102
GND2
VEN
VDET
PIN
GND3
GND1
C134
C135
C136
C137
C138
C139
C140
C141
10n
10n
10n
1u
10n
10n
10n
1u
CPL_EN
2
3
C144
100p
PGND
VBAT
VBAT
Band2
L117
1.5n
20
CLK
19
VSPI
C178
1u
PA_RAMP
C179
0.1u
18
17
C180
16
15p
15
C185
15p
14
RX_L1
SS
GND2
DRW
RXTX_L2
U104
CLK
VSPI
GND3
RXTX_H
GND_SPI
GND4
VCMOS
RXTX_M1
VRAMP
GND5
GND_HB
RX_M2
TX_HB
27
DCS_PCS_TX
DET
RX_M3
GND4
7
6
DNI
C157
VCC2
VCC1
RFOUT
RFIN
ISO
VBP
GND
VMODE
CPL
VEN
FL107 3
1
C154
2
3
L130
33p
PA_MODE
PA_MODE2
PA_EN_1900
4
5
2.7n
G3
1
OUT IN
G2 G1
5 2
L131
2.7n
TX3G_M1_1900
C158
DNI
C107
100p
(0603)
100p
(0603)
100p
(0603)
GND3
CPL
L122
8.2n
PGND
DNI
1880MHz
RX_850
C153
33p
L119
3.9n
FL108
6
ANT
RX
TX
C131
2
4
5
DNI
GND1
GND2
GND3
C164
C165
1n
2.2u
C167
100p
1
L129
14
12
C174
0.5p
L124
11
DNI
10
9
CPL
897.5 MHz,942.5 MHz

10
Band1
RX_1900
12
C169
RX_1800
27p
L114
RFOUT_LOW
RFIN_LOW
GND3
VCC2
GND2
VMODE
U105
RFOUT_HI
GND1
CPL
ANT
RX
TX
L123
2
4
5
10n
VBP
VCC1
VEN_LOW
VEN_HI
RFIN_HI
C172
1
2
33p
4
2.7n
PA_MODE2
PA_MODE
3
4
5
PA_EN_900
PA_EN_2100
6
7
OUT
IN
C173
56p
G3 G2 G1
C177
DNI
TX3G_L_900
C176
DNI
897.5 MHz
FL110
2.2n
FL109
L113
1n
13
GND4
8
GND5
9
GND6
11
C162
VBAT
Band8
C161
C160
1880,1960MHz
GND1
GND2
GND3
1
3
L125
C184
21
GND6
GND5
C183
22
SS
DRW
GND1
GND1
GND2
L110
100p
(0603)
100p
(0603)
100p
(0603)
100p
(0603)
23
PA_POW_DET
VBAT
ANT
GND_LB
9
100p
15
1.8p
V_Q3_LB
26
1.8p
TX_LB
V_Q3_HB
24
C171
G_SLUG
25
1.2n
10
TX
13
L133
C170
11
RX
L109
8.2n
GSM_TX
U103
ANT
33p
C182
22p
100p
C181
C152
10n
C147
2.2u
PGND
C151
C146
1n
FL106
C148
C150
22u
C145
L115
C187
33p
FL111 3
4
2.7n
1.5n
G3
1
OUT IN
G2 G1
5 2
C188
GND4
8
GND5
9
GND6
C194
DNI
C104
1p
10p
TX3G_H_2100
C192
C193
1950MHz
DNI
DNI
2.85V_RF1
8.2p
C 197
2.7p
C 196
1950MHz, 2140MHz
C198
C199
10n
10p
L118
2.7n
CN10
CN11
CN6
CN9
CN7
CN4
CN1
CN20
CN19
CN18
CN13
CN14
CN15
CN17
C5026
33p
DNI
10
11
12
13
RFIN2
RFIN1
L120
2.7n
VCC
VGS
CN8
RREF
RFOUT2
U106
RFOUT1/4
RFGND1/2
RFIN4
RFOUT5
NC
RFIN5
15
CN5
VON
14
18p
CN12
C 1002
3.9p
CN2
C1001
C5028
CN3
LNA_CTRL3
DNI
RFGND4
VEN1
R109
VEN2
R110
LNA_CTRL4
GND
5
4
3
2
1
R106
27K
(1%)
RFOUTM
RFOUTH
RFOUTL
17
16
TOP Shieldcan Pad
18p
C1004
2.7p
C1003
LNA_CTRL1
LNA_CTRL2
L121
8.2n
- 206 -

7. CIRCUIT DIAGRAM
BASE BAND PROCESSOR(PM9801)
BOOT CONFIGURATION
VBAT
1.8V_SD
VBAT
2.3V_RTC 1.35V_PLL 2.85V_SIM 3.1V_USB
4.7K
R212
220n
C220
C221
22u
22u
RESET1_N
IFX_RESET
3.3u
DSP_AUDIO_IN1 HW_MON1
IPC_SRDY
MODEM_AP_WAKE
MODEM_WAKE
MODEM_PWR_CHK
MODEM_CHK
TP111
HW_MON2
0.1u
0.1u
0.1u
0.1u
U202
A8
C1
G1
G10
L1
N8
TRIG_IN
16-bit NAND boot
Flashless boot
NOR boot
4.7u
C223
C224
C225
C226
B9
C10
D9
E10
F9
H10
J9
K9
L10
M9
1.2V_MIPI
2.5V_ANA2
1.8V_SD
3.1V_USB
MEM_BUSY
MEM_WP
R221
C229
0.1u
C230
0.1u
C231 C232
0.1u 0.1u
C233
0.1u
1.8V_SD
1.3V_CORE
C236
0.1u
C237
2.3V_RTC
220n
X201
1
C238
220n
C239
FC-135
32.768KHz
18p
30K
U201
C240
18p
BT_PCM_SYNC
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_CLK
UART_TX_SW
USIF1_TX_IFX
USIF1_SW
UART4_RX_IPC
V+
NO1
COM1
10
NO2
NC2
NC1
GND
USIF1_RX_IFX
1.8V_SD
IN2
IN1
UART_RX_SW
COM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC27
NC20
NC21
NC9
NC19
NC8
NC11
NC12
NC17
NC18
NC7
NC16
NC25
NC6
NC10
NC5
NC13
NC14
NC4
NC2
NC24
NC22
NC23
NC15
NC3
/CK
CK
CKE
/CS
/RAS
/CAS
/WED
UDQM
LDQM
UDQS
LDQS
MEM_AD0
MEM_AD1
MEM_AD2
MEM_AD3
MEM_AD4
MEM_AD5
MEM_AD6
MEM_AD7
MEM_AD8
MEM_AD9
MEM_AD10
MEM_AD11
MEM_AD12
MEM_AD14
MEM_AD15
K4
K5
K6
K7
J8
K8
J7
J5
E6
C5
D8
C6
C8
C7
B8
B7
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
G8
F8
D3
H2
F2
G2
J1
D7
H8
D5
H7
MEM_BFCLKO1
MEM_SDLKO
MEM_CKE
MEM_CS1_N
MEM_RAS_N
MEM_CAS_N
MEM_WR_N
MEM_DQM1
MEM_DQM0
MEM_STROBE1
MEM_STROBE0
R222
C234
C235
A5
M5
0.1u
0.1u
A9
B1
B5
B10
C9
D10
E9
F10
G9
H1
H9
J10
K10
L2
L9
M10
N6
N9
VBAT
IFX_USB_VBUS
USB_VBUS
C228
220n
Q201
1 S1
D1 6
2 G1
G2 5
3 D2
S2 4
VCC1
VCC2
VSS1
VSS4
VSS8
VSSQ5
VSSQ4
VSSQ9
VSSQ8
VSSQ3
VSS2
VSS3
VSSQ10
VSSQ1
VSSQ2
VSS5
VSSQ6
VSSQ7
VSS6
VSS7
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
10K (0603)
/CE
/RE
/WE
CLE
ALE
/WP
R/B
M1
M2
M3
L5
N7
L6
M6
L8
N2
N3
M4
N4
N5
M7
L7
M8
1.8V_SD
MEM_AD0
MEM_AD1
MEM_AD2
MEM_AD3
MEM_AD4
MEM_AD5
MEM_AD6
MEM_AD7
MEM_AD8
MEM_AD9
MEM_AD10
MEM_AD11
MEM_AD12
MEM_AD13
MEM_AD14
MEM_AD15
A6
A3
A7
A4
B4
B3
B6
MEM_CS0_N
MEM_RD_N
MEM_WR_N
MEM_CLE_N
MEM_ALE_N
MEM_WP
MEM_BUSY
1.8V_SD
DUMMY INTERFACE
1.8V_SD
1.8V_VIO
1.8V_VIO
- 207 -
27
26
25
24
23
22
10
21
11
20
12
19
13
18
14
17
15
16
JTAG_OMAP_TRST
JTAG_OMAP_TDI
JTAG_OMAP_TMS
JTAG_OMAP_TCK
JTAG_OMAP_RTCK
JTAG_OMAP_TDO
OMAP_PWR_RESET
UART3_TX_OMAP
UART3_RX_OMAP
C241
C242
DNI
DNI
DNI
28
DNI
29
DNI
DNI
DNI
R235
R234
2.3V_RTC
IFX_USB_VBUS
30
R233
OMAP_SEND
MODEM_SEND
R231
R230
USB_DP_IFX
USB_DM_IFX
IFX_USB_VBUS
USIF1_TX_IFX
UART_TX_IFX
UART_RX_IFX
USIF1_RX_IFX
MCSPI2_IPC_DOUT
MCSPI2_IPC_DIN
MCSPI2_IPC_CLK
need to apply 43.2ohm, 1%
TDO
TDI
TCK
TMS
TRSTN
TRIG_IN
HW_MON1
HW_MON2
DSP_AUDIO_IN1
26MHz_GPS_REF
SIM_CLK
SIM_RST
SIM_IO
10K
R236
TRSTN
TDI
TMS
TCK
TRIG_IN
TDO
RESET1_N
UART_TX_IFX
UART_RX_IFX
22K
R232
R227
CN201
PT201
R228
R229
43
K14
J14
J15
M15
J13
K13
H13
L14
L13
M14
M13
G11
E10
F12
E12
E11
L8
L7
R9
L5
U10
T10
H10
H9
G5
E8
E2
E1
F9
G19
G20
M17
L17
H17
H16
J17
J16
K17
K16
N11
N12
N9
P11
P10
K10
L10
A8
A9
A10
B10
B8
B9
H4
J4
K4
K5
K2
K1
L4
L2
L1
B7
A7
A6
A3
A4
A5
A2
B6
B5
B4
B3
C6
V6
SYS_CLK
VDDQ1
VDDQ6
VDDQ5
VDDQ4
VDDQ10
VDDQ9
VDDQ2
VDDQ8
VDDQ7
VDDQ3
J4
K1
K2
K3
B2
C2
D1
C3
D2
C4
J3
E2
E1
H3
J2
100n
MEM_AD15
MEM_AD14
MEM_AD13
MEM_AD12
MEM_AD11
MEM_AD10
MEM_AD9
MEM_AD8
MEM_AD7
MEM_AD6
MEM_AD5
MEM_AD4
MEM_AD3
MEM_AD2
MEM_AD1
MEM_AD0
MEM_A15
MEM_A14
MEM_A13
MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
UART4_TX_IPC
C227
IFX_USB_VBUS_EN
(Active high)
VDD1
VDD2
VDD3
VDD5
VDD4
VDD6
A1
A10
N1
N10
MEM_CS1_N
MEM_CS0_N
U203
100K
MEM_WR_N
MEM_RD_N
MEM_ALE_N
VBAT
R220
MEM_CLE_N
Analog switch for USIF1
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
CC_CLK
CC_RST
CC_IO
DPLUS
DMINUS
TDO
TDI
TCK
TMS
TRST_n
TRIG_IN
HW_MON1
HW_MON2
DSP_AUDIO_IN1
CLKOUT0
T_OUT0
T_OUT1
CLK32K
EPN1
EPP1
EPPA1
EPPA2
MICP1
MICN1
AUX1P
AUX1N
AUX2P
AUX2N
MMCI1_CMD
MMCI1_CLK
MMCI1_CD
MMCI1_DAT_0
MMCI1_DAT_1
MMCI1_DAT_2
MMCI1_DAT_3
USB_TEST
USB_DPLUS
USB_DMINUS
USB_TUNE
USB_ID
VBUS1
USIF1_TXD_MTSR
USIF1_RTS_n
USIF1_CTS_n
USIF1_RXD_MRST
USIF3_TXD_MTSR
USIF3_RXD_MRST
USIF3_SCLK
USIF3_RTS_n
USIF3_CTS_n
KP_IN0
KP_IN1
KP_IN2
KP_IN5
KP_IN4
KP_IN3
KP_IN6
KP_OUT0
KP_OUT1
KP_OUT2
KP_OUT3
NC_13
NC_14
4.7K
MEM_SDLKO
MEM_STROBE1
MEM_STROBE0
MEM_DQM1
MEM_DQM0
MEM_CAS_N
MEM_RAS_N
PMIC
Y7
Y8
Y5
Y6
Y9
Y10
R2
T1
T2
T4
T5
U1
U2
V1
V2
W1
W2
W3
Y2
Y3
H7
H5
H8
J7
J8
J1
J2
H1
H2
M19
M20
M18
M16
L16
L19
L20
K19
J20
J18
H19
J19
K20
U8
U7
U6
U5
U4
W6
W5
W4
Y4
U16
P13
P14
N13
T17
R16
N14
R17
P16
R18
P17
N16
N17
P19
N19
N20
Y16
Y15
W16
W17
W18
Y18
W19
Y19
W20
V19
V20
T19
T20
R19
R20
P20
A2
D4
D6
E3
E4
E5
E7
E8
F1
F3
F4
F5
F6
F7
G3
G4
G5
G6
G7
H4
H5
H6
J6
L3
L4
4.7K
PCM_IFX_OMAP_DOUT
PCM_IFX_OMAP_CLK
MEM_CKE
MEM_BFCLKO1
R219
4.7K
R218
4.7K
R217
1.8V_SD
SWIF_TXRX
MMCI3_DAT[3]
MMCI3_DAT[2]
MMCI3_DAT[1]
MMCI3_DAT[0]
MMCI3_CD
MMCI3_CLK
MMCI3_CMD
MMCI2_DAT[3]
MMCI2_DAT[2]
MMCI2_DAT[1]
MMCI2_DAT[0]
MMCI2_CD
MMCI2_CLK
MMCI2_CMD
MEM_CKE
MEM_BFCLKO_1
MEM_BFCLKO_0
MEM_SDCLKO
MEM_BC3_n
MEM_BC2_n
MEM_BC1_n
MEM_BC0_n
MEM_CAS_n
MEM_RAS_n
MEM_WAIT_n
MEM_WR_n
MEM_RD_n
MEM_ADV_n
MEM_CSA0_n
MEM_CS2_n
MEM_CS1_n
MEM_CS0_n
FCDP_RBn
FWP
VDD_FUSE_FS
VDD_FUSE_LS
VDD_USB_HS_PHY
VDD_USB_DIG
VDD_USB
VDD_MIPI_SLAVE
VDD_MIPI_MASTER
VDD_MIPI_BGC
VDD_MIPI_PLL
MIPI_R_EXT
VDDP_MMC
VSS_MAIN_19
VSS_MAIN_18
VSS_MAIN_17
VSS_MAIN_16
VSS_MAIN_15
VSS_MAIN_14
VSS_MAIN_13
VSS_MAIN_12
VSS_MAIN_11
VSS_MAIN_10
VSS_MAIN_9
VSS_MAIN_6
VSS_MAIN_5
VSS_MAIN_4
VSS_MAIN_3
VSS_MAIN_2
VSS_MAIN_1
VDDP_DIG_MS
VDDP_DIG_6
VDDP_DIG_5
VDDP_DIG_4
VDDP_DIG_3
VDDP_DIG_2
VDDP_DIG_1
VDD_CORE_6
VDD_CORE_5
VDD_CORE_4
VDD_CORE_3
VDD_CORE_2
VDD_CORE_1
VSS_RTC
VDD_RTC
OSC32K
F32K
F26M
CSI_CLKN
CSI_CLKP
CSI_DN2
CSI_DP2
CSI_DN1
CSI_DP1
CIF_RESET_GPIO
CIF_PD_GPIO
CLKOUT2
CIF_VSYNC
CIF_HSYNC
CIF_PCLK
CIF_D7
CIF_D6
CIF_D5
CIF_D4
CIF_D3
CIF_D2
CIF_D1
CIF_D0
I2S1_WA0
I2S1_TX
I2S1_RX
I2S1_WA1
I2S1_CLK0
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
CP2
CP1
VDD_CPN
VUMIC
VMIC
HP_SPK2N
HP_SPK2P
HP_SPK1N
HP_SPK1P
VSS_HF_SPK_2
VSS_HF_SPK_1
VBAT_HF_SPK_2
VBAT_HF_SPK_1
MIPI1_DATA7
MIPI1_DATA6
MIPI1_DATA5
MIPI1_DATA4
MIPI1_DATA3
MIPI1_DATA2
MIPI1_DATA1
MIPI1_DATA0
MIPI1_CLK
MEM_AD15
MEM_AD14
MEM_AD13
MEM_AD12
MEM_AD11
MEM_AD10
MEM_AD9
MEM_AD8
MEM_AD7
MEM_AD6
MEM_AD5
MEM_AD4
MEM_AD3
MEM_AD2
MEM_AD1
MEM_AD0
MEM_A15
MEM_A14
MEM_A13
MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0
R223
PCM_IFX_OMAP_FSYNC
PCM_IFX_OMAP_DIN
J6
D1
D2
C1
C2
D4
B1
B2
E5
D5
D6
D7
G4
E4
D8
U11
W14
U14
W13
Y17
U20
W15
U19
T14
T13
U15
U13
U12
V15
T11
T12
R12
P12
T9
V9
P8
P9
D9
D10
C9
W7
W11
W8
W12
W10
N10
W9
V12
M3
J3
H20
P7
G7
R4
F4
D16
D11
T16
T7
L11
K7
E7
B11
H14
R3
F3
U17
T6
K8
E6
R5
F5
T15
T8
K11
E9
C12
B12
A11
A12
D13
RESET2_N
RESET_CMP
CHRG_EN
I2C_INT
CMP_EN
REF_CLK_EN
FSYSEN
Di3_RX_DAT
Di3_RX_DATX
Di3_TX_DAT
Di3_TX_DATX
SYSCLKEN
XRESET
ALERT_N
VRE F
VDD_VBAT_SD1_1
VDD_VBAT_SD1_2
VSD1_1
VSD1_2
SD1_FB
VSS_SD1_1
VSS_SD1_2
VDD_VBAT_SD2_1
VDD_VBAT_SD2_2
VSD2_1
VSD2_2
SD2_FB
VSS_SD2_1
VSS_SD2_2
ON_OFF1
ON_OFF2
RESET1_N
RESET_PMU_N
PWR_ON_CMP
PMUMEAS
VDD_LVDS
VANA1
VANA2
VSS_ANA
VDD_VBAT_LDO
VDD_OSD2
VRF2
VDD_VBAT_RF12_1
VRF1
VDD_VBAT_RF12_2
VSS_RF12
VMIPI
VDD_VRTC
VDD_VPLL
VDD_VSIM
VDD_VUSB
VDD_VPMU
DIF_D0
DIF_D1
DIF_D2
DIF_D3
DIF_D4
DIF_D5
DIF_D6
DIF_D7
DIF_D8
DIF_D9
DIF_CS1
DIF_CS2
DIF_CD
DIF_WR
DIF_RD
DIF_HD
DIF_VD
DIF_RESET1
DSI_DP1
DSI_DN1
DSI_CLKP
DSI_CLKN
NC_9
NC_10
NC_11
NC_12
U9
G9
J5
G1
G8
G10
F2
B14
B13
A14
A13
F1
G2
H11
A 15
A18
B17
A19
B18
A17
B19
C19
D 17
E 17
B20
C20
E20
D20
D19
G14
G13
G12
F20
H12
E19
D12
G16
F18
B16
E 16
E14
D15
B15
A16
D14
C15
F16
G 17
E13
F19
E15
F17
P5
R1
P2
P1
N7
M6
N5
N4
N2
N1
M8
M7
M5
M4
M2
M1
N8
P4
Y13
Y14
Y 11
Y12
A1
Y1
A20
Y20
TP110
IPC_MRDY
L201
3.3u
L202
DI3_TX_DAT
DI3_TX_DATX
SYS_CLK_EN
RESET_N_UE
ALERT_N_UE
REF_CLK_EN
100
C222
10K (0603)
220n
C219
10K (0603)
C202
1.8V_SD
10K (0603)
R207
R206
INFINEON MEMORY
DSP_AUDIO_IN1
HW_MON1
HW_MON2
TRIG_IN
R226
0.1u
R225
0.1u
R224
C216
NC1
NC26
NC28
NC29
C215
1u
DNI
C214
220n
DNI
C213
0.1u
4.7K
C212
220n
R204
R201
C211
100n 10u
R202
C209 C210
1u
4.7K
C208
1u
R208
C207
220n
R205
C206
100n 10u
10K
R211
DI3_RX_DAT
C204 C205
220n
390K
10u
C203
10n
220K
10u
C201
IFX_PWRON
C218
DI3_RX_DATX
C217
1.8V_SD
4.7K
IFX_USB_VBUS
1.3V_CORE
R203
1.2V_MIPI
DNI
1.8V_SD 2.85V_RF2 2.85V_RF1
R210
2.5V_ANA2
RD2N0I9
1.35V_PLL
VBAT

7. CIRCUIT DIAGRAM
CLK32K_TWL
26M_REF
TWL_CLK_REQ
MICROSD_DET_N
1.8V_VIO
OMAP_PWR_RESET
PWR_WARM
SYS_IRQ_N
SYS_OFF_MODE
D NI
10 K
R305
R306
EAR_SENSE
AE17
AG25
SYS_XTALIN
AF17
SYS_XTALOUT
AE25
SYS_32K
SYS_CLKOUT1
AE22
SYS_CLKOUT2
AF25
SYS_CLKREQ
AH25
SYS_NRESPWRON
AF24
SYS_NRESWARM
AF26
SYS_NIRQ
AF22
SYS_OFF_MODE
TV_OUT2
TV_OUT1
TV_VFB1
TV_VFB2
TV_VREF
100K
470
W28
Y28
Y27
W27
W26
100K
R307
J 25
1.8V_VIO
100ohm matching!
HDQ_SIO
BT_WAKEUP
LCD_TE
LCD_CS
LCD_MAKER_ID
VIBE_PWM
VIBE_EN
COM_INT
1.8V_VIO
EAR_MICBIAS_EN
VT_RESET_N
LCD_CP_EN
ONENAND_INT
UART4_TX_IPC
UART4_RX_IPC
AB26
AB25
AA25
AD25
R312
4.7K
BT_UART_CTS_N
BT_UART_RTS_N
BT_UART_TXD
BT_UART_RXD
H18
HOOK_DIG
UART3_CTS_RCTX
GPIO
163
H19
UART3_RTS_SD
GPIO 164
H20
Also connected to TWL 'HOOK_ADC'
UART3_RX_OMAP
UART3_TX_OMAP
UART3_TX_IRRX
H21
UART3_TX_IRTX
AA8
GPS_UART_TXD
GPS_UART_RTS_N
GPS_UART_CTS_N
GPS_UART_RXD
UART1_TX
AA9
UART1_RTS
W8
UART1_CTS
Y8
UART1_RX
1.8V_VIO
DNI
4.7K
4.7K
R316
R317
4.7K
R315
BOOT CONFIGURATION
SYS_BOOT0 SYS_BOOT1 SYS_BOOT2 SYS_BOOT3 SYS_BOOT4 SYS_BOOT5 SYS_BOOT6
4.7K
DNI
R323
OneNAND boot
4.7K
TP303
G4
H3
V8
U8
T8
R8
P8
N8
T4
F4
G2
F3
G3
U3
H1
M8
L8
K8
J8
R321
I2C4_SCL
I2C4_SDA
I2C3_SCL
I2C3_SDA
JTAG_OMAP_TDO
JTAG_OMAP_TRST
JTAG_OMAP_TMS
JTAG_OMAP_TDI
JTAG_OMAP_TCK
JTAG_OMAP_RTCK
JTAG_TDO
JTAG_NTRST
JTAG_TMS_
JTAG_TDI
JTAG_TCK
JTAG_RTCK
JTAG_EMU0
JTAG_ENU1
AA19
AA17
AA18
AA20
AA13
AA12
AA11 R308
AA10 R309
AG19
CSI2_DX0
AH19
CSI2_DY0
AG18
CSI2_DX1
AH18
CSI2_DY1
C25
B26
C27
A 23
A 24
C23
B 23
D25
AG17
AH17
B2 4
C24
D24
A25
K28
L28
K27
L27
B 25
C26
AD26
I2C4_SCL
AE26
I2C4_SDA
CAM_XCLKA
CAM_XCLKB
CAM_PCLK
CAM_VS
CAM_HS
CAM_FLD
CAM_WEN
CAM_STROBE
CAM_D0
CAM_D1
CAM_D2
CAM_D3
CAM_D4
CAM_D5
CAM_D6
CAM_D7
CAM_D8
CAM_D9
CAM_D10
CAM_D11
- 208 -
D6
C6
B6
C8
C9
A7
B9
A9
C14
B14
C15
B16
D17
C17
B17
D18
D11
B10
C11
D12
C12
A11
B13
D14
C18
A19
B19
B20
D20
A21
B21
C21
R322
Fiducial1
GAUGE_INT
MODEM_SEND
MODEM_CHK
U305
I2C2_SCL
I2C2_SDA
UART2_CTS
UART2_RTS
UART2_TX
UART2_RX
4G LPDDR
1
AF14
GPMC_WAIT0
GPIO 63GPMC_WAIT1
GPIO 64GPMC_WAIT2
GPIO 65GPMC_WAIT3
4.7K
MMC2_CLK
MMC2_CMD
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
MMC2_DAT4
MMC2_DAT5
MMC2_DAT6
MMC2_DAT7
R314
36
AE2
AG5
AH5
AH4
AG4
AF4
AE4
AH3
AF3
AE3
R318
POP memory
R324
DNI
MMC_CLK
MMC_CMD
MMC_DAT0
MMC_DAT1
MMC_DAT2
MMC_DAT3
MMC_DAT4
MMC_DAT5
MMC_DAT6
MMC_DAT7
DN I
OMAP_SEND
KEY_LED_RESET
MODEM_AP_WAKE
4.7K
CTS
GPMC_CLK
GPMC_NWE
GPMC_NOE
GPMC_NADV_AL
GPIO GPMC_NBE0_CL
60
GPIO 61 GPMC_NBE1
GPIO 62 GPMC_NWP
R320
RTS
MMC1_CLK
MMC1_CMD
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
MMC1_DAT4
MMC1_DAT5
MMC1_DAT6
MMC1_DAT7
R319
DSR
N28
M27
N27
N26
N25
P28
P27
P26
R27
R25
R313
NC4
10
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
NC3
R311
AH26
AG26
AE14
AF18
AF19
AE21
AF21
NC2
MICROSD_CLK
MICROSD_CMD
MICROSD_DAT0
MICROSD_DAT1
MICROSD_DAT2
MICROSD_DAT3
21
22
23
24
25
26
27
28
29
VBAT
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ON_SW
52 GPMC_NCS1
53 GPMC_NCS2
54 GPMC_NCS3
55 GPMC_NCS4
56 GPMC_NCS5
57 GPMC_NCS6
58 GPMC_NCS7
LCD_RESET_N
TOUCH_INT_N
VT_CAM_PWDN
CAM_SUBPM_EN
MODEM_PWR_CHK
MODEM_WAKE
MUIC_INT_N
GYRO_INT_N
MOTION_INT
BT_HOST_WAKEUP
TP302
NC1
TP301
TX
GPIO 14
GPIO 15
GPIO 16
RX
ETK_CLK
ETK_CTL
ETK_D0
ETK_D1
ETK_D2
ETK_D3
ETK_D4
ETK_D5
ETK_D6
ETK_D7
ETK_D8
ETK_D9
ETK_D10
ETK_D11
ETK_D12
ETK_D13
ETK_D14
ETK_D15
GND
OMAP_UART_SW
IFX_UART_SW
PWR_ON_SW
MCBSP1_CLKR
MCBSP1_FSR
MCBSP1_DX
MCBSP1_DR
MCBSP1_CLKS
MCBSP1_FSX GPIO 161
MCBSP1_CLKX GPIO 162
1
2
3
4
5
6
7
8
9
10
11
12
UART_RX_IFX
UART_TX_IFX
3G
GPMC_NCS0
Y21
AA21
V21
U21
T21
K26
W21
2.5G
NC43
NC21
NC24
NC7
NC42
NC44
NC41
NC20
SDRC_D8
SDRC_D9
SDRC_D10
SDRC_D11
SDRC_D12
SDRC_D13
SDRC_D14
SDRC_D15
NC18
NC16
NC14
NC1
NC32
NC4
NC5
NC3
NC2
NC33
NC15
NC17
NC25
NC22
NC37
NC34
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PCM_IFX_OMAP_CLK
PCM_IFX_OMAP_FSYNC
PCM_IFX_OMAP_DOUT
PCM_IFX_OMAP_DIN
UAT301
HSUSB0_DATA0
HSUSB0_DATA1
HSUSB0_DATA2
HSUSB0_DATA3
HSUSB0_DATA4
HSUSB0_DATA5
HSUSB0_DATA6
HSUSB0_DATA7
HSUSB0_CLK
HSUSB0_STP
HSUSB0_DIR
HSUSB0_NXT
VBAT VCHG
N4
M4
L4
K4
T3
R3
N3
M3
L3
K3
34 GPMC_A1
35 GPMC_A2
36 GPMC_A3
37 GPMC_A4
38 GPMC_A5
39 GPMC_A6
40 GPMC_A7
41 GPMC_A8
42 GPMC_A9
43 GPMC_A10
U301
T27
U28
U27
U26
U25
V28
V27
V26
T28
T25
R28
T26
MIC_SEL
DSS_DATA0
DSS_DATA1
DSS_DATA2
DSS_DATA3
DSS_DATA4
DSS_DATA5
DSS_DATA6
DSS_DATA7
DSS_DATA8
DSS_DATA9
DSS_DATA10
DSS_DATA11
DSS_DATA12
DSS_DATA13
DSS_DATA14
DSS_DATA15
DSS_DATA16
DSS_DATA17
DSS_DATA18
DSS_DATA19
DSS_DATA20
DSS_DATA21
DSS_DATA22
DSS_DATA23
DSS_PCLK
DSS_HSYNC
DSS_VSYNC
DSS_ACBIAS
USB_D[0]
USB_D[1]
USB_D[2]
USB_D[3]
USB_D[4]
USB_D[5]
USB_D[6]
USB_D[7]
USB_CLK
USB_STP
USB_DIR
USB_NXT
Array TP
AG22
AH22
AG23
AH23
AG24
AH24
E26
F28
F27
G26
AD28
AD27
AB28
AB27
AA28
AA27
G25
H27
H26
H25
E28
J26
AC27
AC28
D28
D26
D27
E27
LCD_MIPI_D0_P
LCD_MIPI_D0_N
LCD_MIPI_D1_P
LCD_MIPI_D1_N
LCD_MIPI_CLK_P
LCD_MIPI_CLK_N
152
153
154
10n
MCBSP4_FSX GPIO 155
IFX_RESET
C303
MCBSP3_FSX
AE 1
MCBSP4_CLKX GPIO
AD1
MCBSP4_DR GPIO
AD2
MCBSP4_DX GPIO
AC1
IFX_PWRON
GPS_PWR_ON
GPS_RESET_N
FLASH_LED_TORCH
FLASH_LED_EN
GND
MCBST2_DX
_OE
AF 6
MCBSP3_DX
AE 6
MCBSP3_DR
AF 5
MCBSP3_CLKX
AE 5
B2
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_CLK
BT_PCM_SYNC
5 1K
A2
R310
10n
B1
I2S_FSYNC
I2S_CLK
I2S_DIN
I2S_DOUT
VCCB
A1
GPIO 181
GPIO 182
C302
VCCA
MCSPI2_CS1
IFX_RESET_1.8V
100K
R325
IFX_PWRON_1.8V
P21
MCBSP2_FSX
N21
MCBSP2_CLKX
R21
MCBSP2_DR
M21
2.3V_RTC
U302
SDRC_NRAS
SDRC_NCAS
SDRC_NWE
SDRC_CLK
SDRC_NCLK
SDRC_CKE1
SDRC_CKE0
SDRC_NCS1
SDRC_NCS0
NC39
NC27
SDRC_DM1
NC8
NC45
NC40
SDRC_DQS1
NC38
K1
L1
L2
P2
T1
V1
V2
W2
H2
K2
P1
R1
R2
T2
W1
Y1
GPMC_D0
GPMC_D1
GPMC_D2
GPMC_D3
GPMC_D4
GPMC_D5
GPMC_D6
GPMC_D7
GPMC_D8
GPMC_D9
GPMC_D10
GPMC_D11
GPMC_D12
GPMC_D13
GPMC_D14
GPMC_D15
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
TP305
H14
H13
H15
A13
A14
H17
H16
H12
H11
C20
B11
A16
B7
A20
A10
A17
A6
NC35
NC9
NC10
NC11
NC12
NC13
NC19
NC29
NC26
NC28
NC30
NC23
NC31
NC36
NC6
MCSPI1_CLK
MCSPI1_SIMO
MCSPI1_SOMI
MCSPI1_CS0
MCSPI1_CS1
MCSPI1_CS2
MCSPI1_CS3
LEVEL SHIFTER
1.8V_VIO
TP309
SDRC_BA0
SDRC_BA1
AB 3
AB 4
AA 4
AC2
AC3
AB 1
AB 2
E1
E2
D1
D2
D3
D4
C1
C2
C3
D5
C4
C5
B3
B4
A4
I2C3_SCL
AG14
I2C3_SDA
K 21
C301
H9
H10
AF15
Internal pull-up at I2C1 and I2C4
I2C2_SCL
AE15
I2C2_SDA
GND
I2C1_SCL
J21
I2C1_SDA
SEL0
TP308
12
3
GPIO 176
GPIO 177
VCC
TP307
AA 3
MCSPI2_CLK
Y2
MCSPI2_SIMO
Y3
MCSPI2_SOMI
Y4
MCSPI2_CS0
V3
SEL1
TP306
UART_RX
TP304
MCSPI2_IPC_CLK
MCSPI2_IPC_DOUT
MCSPI2_IPC_DIN
WLAN_WAKEUP
USIF1_SW
11
D-
1u
HSD2HSD3-
AF10
AE10
AF11
AG12
AH12
AE13
AE11
AH9
AF13
AH14
AF 9
AG9
AE 7
AF 7
AG7
AH7
AG8
AH8
UART_TX
HSD1-
WLAN_CLK
WLAN_CMD
PROX_OUT
CHG_STATUS_N_OMAP
BT_EN
WLAN_SDIO[3]
WLAN_SDIO[0]
WLAN_SDIO[1]
WLAN_SDIO[2]
IPC_SRDY
IPC_MRDY
WLAN_EN
WLAN_HOST_WAKEUP
CHG_EN_SET_N_OMAP
IFX_RESET_1.8V
IFX_PWRON_1.8V
CRADLE_DETECT_N
CARKIT_DETECT_S
HSD3+
R327
D+
R301
R302
R303
R304
HSD2+
IFX_UART_SW
OMAP_UART_SW
HSD1+
8
10
5M_MCLK
VT_MCLK
VT_PCLK
VT_VSYNC
VT_HSYNC
5M_RESET_N
5M_CAM_VCM_EN
IC301
6
UART3_TX_OMAP
UART_TX_SW
USB_DP_IFX
UART3_RX_OMAP
UART_RX_SW
USB_DM_IFX
DNI
DN I
R326
1.8V_VIO
4.7K
4.7K
4.7K
4.7K
I2C1_SCL
I2C1_SDA
1.8V_VIO
5M_MIPI_CLK_P
5M_MIPI_CLK_N
5M_MIPI_DATA0_P
5M_MIPI_DATA0_N
VBAT
VT_DATA[0]
VT_DATA[1]
VT_DATA[2]
VT_DATA[3]
VT_DATA[4]
VT_DATA[5]
VT_DATA[6]
VT_DATA[7]
DP3T SWITCH
5M_MIPI_DATA1_P
100ohm matching!
5M_MIPI_DATA1_N
IFX_USB_VBUS_EN
OMAP3630
eMMC boot
External boot

7. CIRCUIT DIAGRAM
TWL5034
OMAP3x30 Power
Resistane depending on PCB revision

Revision
68kohm / 6.2kohm
Rev.B
68kohm / 10kohm
Rev.C
68kohm / 15kohm
Rev.D
68kohm / 20kohm
Rev.E
68kohm / 24kohm
Rev.F
68kohm / 30kohm
Rev.G
68kohm / 36kohm
A11
B13
A13
C432
1u
N16
C13
K11
J11
H8
T1
P15
P16
N10
G15
F15
F16
H4
J3
BATT_THM_ADC
G3
J9
B1
D8
PCB_VER_ADC
HOOK_ADC
VDD1_CORE
N11
P11
N8
N9
L10
C476 C478 C479 C480
BOOT0
2.2u 1u
0.1u
0.1u
AUDIO LDO
N14
M4
A2
P1 3
GPIO_7
GPIO_2
GPIO_6
GPIO_15
RFID_EN
L4
P1 2
N1 2
GPIO_1
GPIO_0
C5034
0.1u
0.1u
C414
C413
F1
G1
AUXL
C455
C411
C5035
0.1u
MIC_SUB_M
0.1u
G2
D2
H2
0.1u
F2
MIC_MAIN_P
MIC_SUB_P
ICTLAC2
ICTLUSB2
MSECURE
VPRECH
PCHGAC
PCM_VCK
PCHGUSB
VCCS
PCM
PCM_VDX
VBATS
PCM_VFS
VBAT
BCIAUTO
GPIO_17
GPIO_16
BKBAT
I2S_CLK
IO_1P8
I2S_SYNC
I2S
I2S_DIN
VBAT_RIGHT_02
I2S_DOUT
HF SET
JTAG_TCK
VBAT_RIGHT_01
VBAT_LIFT_02
VBAT_LEFT_01
JTAG_TDI
TEST
VMMC2_IN
TESTV2
VMMC1_IN
NC
TESTV1
TEST_RESET
VAUX4_IN
VBAT_USB
32KXOUT
PWR IN
32KXIN
32KCLKOUT
VDAC_IN
VAUX12S_IN
VPLLA3R_IN
LEDB
VINT_IN
LEDA
LEDSYNC
VSDI_CSI_OUT
LEDGND
VPLL1_OUT
VDAC_OUT
ADCIN0
VSIM_OUT
ADCIN1
VMMC2_OUT
ADC
ADCIN2
LDO PWR
START_ADC
VMMC1_OUT
VAUX4_OUT
VAUX3_OUT
UART1_TXD
VAUX2_OUT
UART
UART1_RXD
VAUX1_OUT
RTSO
VINTUSB1P8_OUT
CTSI
VINTUSB1P5_OUT
ADC
TXAF
VUSB_3P1
RXAF
VINTDIG_OUT
MANU
VRTC_OUT
DGND_01
DGND_04
H13
DGND_03
H11
H10
DGND_02
H9
KPD_C7
KPD_C6
KPD_C5
KPD_C4
F4
H6
G4
G7
KPD_C3
F7
KPD_C1
KPD_C2
G6
KPD_C0
VINTANA2_OUT_02
VINTANA2_OUT_01
VINTANA1_OUT
E13
C421
C420
0.1u
10u
C14
D15
D16
L402
1u
VDD1_CORE
B15
C15
C16
C422
C423
0.1u
22u
C426
C427
0.1u
10u
R13
P14
N13
T13
R14
L403
VDD2_CORE
1u
T14
R15
C424
C425
0.1u
10u
P3
R4
N3
R3
T4
L404
1u
1.8V_VIO
C430
R2
C428
C429
0.1u
10u
C431
0.1u
T3
10u
N5
N7
P2
P6
VBAT
P1
N2
N4
N6
C434
P5
1u
C433
4.7u
P4
R5
N1
BAT401
M14
C8
1.8V_VIO
D11
D12
C435
D9
VBAT
C436
1u
D10
1u
A3
C1
B2
R9

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LG P970 Optimus Black Service Manual - en

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Internal Use Only

Date: April, 2011 / Issue 1.0

4.5 Checking WCDMA Block114

Copyright 2011 LG Electronics. Inc. All right reserved.

1.2 Regulatory Information

LGE Internal Use Only

Copyright 2011 LG Electronics. Inc. All right reserved.

E. Notice of Radiated Emissions

Following information is ESD handling:

LGE Internal Use Only

Copyright 2011 LG Electronics. Inc. All right reserved.

Automatic Power Control

Bit Error Ratio

Constant Current Constant Voltage

Digital to Analog Converter

Digital Communication System

dB relative to 1 milli watt

Digital Signal Processing

Electrical Erasable Programmable Read-Only Memory

Flexible Printed Circuit Board

Gaussian Minimum Shift Keying

General Purpose Interface Bus

Global System for Mobile Communications

International Portable User Identity

Liquid Crystal Display

Low Drop Output

Light Emitting Diode

Offset Phase Locked Loop

LGE Internal Use Only

Copyright 2011 LG Electronics. Inc. All right reserved.

Power Amplifier Module

Printed Circuit Board

Programmable Gain Amplifier

Phase Locked Loop

Public Switched Telephone Network

Receiving Loudness Rating

Root Mean Square

Real Time Clock

Surface Acoustic Wave

Subscriber Identity Module

Sending Loudness Rating

Static Random Access Memory

Side Tone Masking Rating

Time Division Duplex

Time Division Multiple Access

Universal Asynchronous Receiver/Transmitter

Voltage Controlled Oscillator

Voltage Control Temperature Compensated Crystal Oscillator

Wireless Application Protocol

LGE Internal Use Only

Copyright 2011 LG Electronics. Inc. All right reserved.

2.1 Product Name

2.2 Supporting Standard

WCDMA(FDD1) TX : 1920 1980 MHz

: 824 849 MHz

: 869 894 MHz

: 1710 1785 MHz

: 1805 1880 MHz

: 1850 1910 MHz

: 1930 1990 MHz

2.3 Main Parts : GSM Solution

LGE Internal Use Only

4.5 Checking WCDMA Block114