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Next-Generation Wireless
Prototyping
Sponsored by
Sarah Yost
Product Marketing Manager| SDR & Wireless Research
ni.com
eMBB
100 X More
Devices
< 1 mS
Latency
mMTC
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uMTC, UR/LL
Peak
Data Rate
High
User Experience
Data Rate
Med
Low
Area Traffic
Capacity
Spectrum
Efficiency
Mobility
Network
Energy Efficiency
eMBB
uMTC, UR/LL
Latency
Connection
Density
Source ITU-R M.[IMT.VISION]
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mMTC
1982-85
GSM
5G
We are here
The
Pivotal Year
of
Standardization
Pivotal
Moment
Birth
of GSM
1987
1988-91
Implementation by aBillions
large number
of Devices
of suppliers & operators
Source: www.gsmhistory.com/who_created-gsm
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Prototyping is needed.
Phased Array
Phased Array
8 Transceiver Base
Station
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Patch
Dipole
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http://theinstitute.ieee.org/technology-focus/technology-history/first-ieee-milestones-in-india
https://www.cv.nrao.edu/~demerson/bose/bose.html
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Modern point-to-point
mmWave link
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The ITU released a list of globally viable frequencies for 5G mmWave technologies
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Communications Prototyping
New physical layer/new air interface
Adapting existing standards from 20
MHz bandwidth to 2 GHz bandwidth
Over the air testing at new mmWave
frequencies
Channe
l
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Channel Sounding
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mmWave propagation channel models for various frequencies and environment are currently available
from different groups, but lacks consistency and use case.
Enable researchers to do measurements efficiently to create and validate the channel models
Use the same HW to run a data link in the same environment immediately and gather system
performance
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7
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Ryan J. Pirkl* and Gregory D. Durgin, How to Build an Optimal Broadband Channel Sounder, Georgia Institute of
Technology, School of ECE, 777 Atlantic Dr, Atlanta, GA 30332, http://www.propagation.gatech.edu
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Channel parameters
Calibration
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ZC Seq
parameters
block
generation
RRC filter
pulse
shaping
Transmit 'x'
repetitions
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FPGA
Host
PPS trigger
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DAC
Equalizer
LUT
From A/D
IQ
CFO
correction
correction
MF
Average
Rx ZC Seq.
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Equalizer
FPGA
Host
Apply
Power Cal.
Post Processing
(rms delay spread,
Doppler etc.)
Channel
Impulse
Response
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o
o
!=
Current setup:
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17 dB
= 81 + 7 36 17 = 127dBm
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Waveform Design
Zadoff-Chu
Sequence Block
Zadoff-Chu
Sequence Block
Zadoff-Chu
Sequence Block
Waveform
Repetition of ZC Sequences 6 7 = 8
9:;<=
>
,0 7
1,
= 1920
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Correlation of received ZC sequence with a local copy gives the CIR estimate
Periodicity also enables TOA measurement
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2.
3.
Linearity Tests
4.
Power Calibration
5.
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Demo
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Physical layer
Higher layers
Low latency MAC, multiuser support, scheduling algorithms, hand off mechanisms, ..
Semiconductor
Scalable BW, Sub 1ms latency, MIMO support, channel coding LDPC, Polar codes etc., beam
steering/tracking, various control channel design, cell search .
Enabling many new areas such as self driving cars, massive number of connected devices as
part of IoT, many more.
Every new idea will requires building some sort of PoC system fast
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Hardware Requirements:
High performance
o
Flexible
o
o
o
Software Requirements
Hardware abstraction
o
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mmWave
Receiver
Baseband
Receiver
IF Downconverter
Analog
Baseband
Digital
Baseband
Analog
Baseband
Digital
Baseband
MulitMulit-FPGA
Processing
Data
mmWave
Transmitter
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IF
Upconverter
Baseband
Transmitter
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MultiMulti-FPGA
Processing
Data
mmWave IC
mmWave IC
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Baseband
Receiver
IF Downconverter
Analog
Baseband
Digital
Baseband
Analog
Baseband
Digital
Baseband
IF
Upconverter
Baseband
Transmitter
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MulitMulit-FPGA
Processing
MultiMulti-FPGA
Processing
Data
Data
Baseband
Receiver
Analog
Baseband
Digital
Baseband
Analog
Baseband
Digital
Baseband
MulitMulit-FPGA
Processing
Data
mmWave IC
Baseband
Transmitter
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MultiMulti-FPGA
Processing
Data
Modulation:
M. Cudak, T. Kovarik, T. A. Thomas, A. Ghosh, Y. Kishiyama and T. Nakamura, "Experimental mm wave 5G cellular system," 2014 IEEE Globecom Workshops (GC Wkshps), Austin, TX,
2014, pp. 377-381.
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W1
Channel Est
Pilot
Odd
Matched
filter
FFT
MIMO
Equalization
IFFT
Stream 1
Decoder
IFFT
Stream 1
Decoder
Channel Est
Pilot
Even
FFT
Stream 1
Stream 2
W2
Channel Est
Pilot
Odd
Matched
filter
FFT
MIMO
Equalizer
Channel Est
Pilot
Even
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FFT
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PXIe-1085 Chassis #1
3072 MS/s
12-bit
Digitizer
3630
ADC Interface
I/Q Correction
RRC Filter
Frame Sync
Equalization
7902
PXIe-1085 Chassis #2
MIMO Processor
Channel Est
Wmmse
7902
LLR
Turbo Decoders
Data Aggregation
Host Processing
PXIe-8880
Eight-core
Intel Xeon E5-2618L
Channel 0
Analog
Differential
I and Q
I
R EF I N
Q
R EF OUT
PCIe
Switch
3630
Channel 1
Analog
Differential
I and Q
7902
7902
I
R EF I N
Q
R EF OUT
PCIe
Switch
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Trigger4..6: bus1
bus2
bus3
IF0
DAC0
ADC0
MOD1
DEMOD1
MOD0
DEMOD0
DAC1
ADC1
IF1
3620
3610
3630
7902
7902
7902
7902
3610
3630
3620
TX
RX
MAC
TX
LO1
IN
LO1
IN
LO1
IN
LO1
OUT
LO1
OUT
LO1
OUT
LO1
OUT
LO1
LO1
LO1
IF IN
8384
16
17
18
16
17
18
RX
LO1
IN
IF OUT
7976R
LO1
IF OUT
IF IN
8880
DIGITAL I/O
DIGIT AL I/O
Q+
LO2 IN
Q+
Q-
LO2 OUT
Q-
I
REF IN
Q
REF OUT
REF IN
REF I N
Q
REF OUT
REF OUT
MIMO
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>> Constellation >> Pilots >>
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I+
RE F IN
I-
REF OUT
Q+
LO2 IN
Q+
Q-
LO2 OUT
Q-
I+
I-
REF I N
REF OUT
12
13
14
15
Wmmse >>
I-
>>
I+
RE F OUT
Wmmse >>
REF IN
I-
>>
I+
7902
2nd stream
BLANK
PCIe
Switch
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10
11
12
13
14
15
PCIe
Switch
High Throughput DSP IP for Multi Gbps mmWave PoC: Wide Data Path
FFT
x0,x4,x8
Serial
FFT128
x1,x5,x9
Serial
FFT128
x2,x6,x10
Serial
FFT128
x3,x7,x11
Serial
FFT128
X0,X1,X2
Parallel FFT4
X256,X257,X258
X384,X385,X386
Twiddle
factors
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X128,X129,X130
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Conclusions
Will require both theoretical research and building PoC systems to validate system performance
Will require much data collection in different environment in order to characterize signal behavior at
mmWave
Research in mmWave spans all the way from channel models to new RAT and semiconductor
development
mmWave technology will also enable new application space that are beyond our imagination
today
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