Chap 3 Processing Unit

Faculty of Electrical and Electronic Engineering
Semester II, Session 2015/2016
BEC30303
Computer Architecture and Organization
Chapter 3:
Processing Unit
Mohamad Hairol Jabbar
Department of Computer Engineering
http://fkee.uthm.edu.my/mhjabbar
REVIEW CHAPTER 2
Instruction architecture definition ISA, elements in
an instruction, assembly vs RTN, CPU storage
organizations
Stack organization operations, RPN
Instruction formats 3-address, 2-address, 1address, 0-address, RISC address
Condition codes/status flags
Addressing modes definition, types of addressing
mode
Encoding of machine instructions definition,
instruction length: fixed vs variable
Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit
CHAPTER 3
In this chapter, we will discuss about the detailed process

for instructions execution by the processor.
OUTLINE
Instruction execution
Instruction fetch and execution steps
Control signals
INSTRUCTION EXECUTION
HW COMPONENTS IN CPU
RECALL: COMPUTER ORGANIZATION

Bus
Processor
Memory
Devices
Control
Cache
Input
Datapath
Output
Registers
FUNDAMENTAL CONCEPTS
Processor (CPU):
the active part of the computer, which does all the
work (data manipulation and decision-making).
Datapath:
portion of the processor which contains hardware
necessary to perform all operations required by
the computer.
Control:
portion of the processor (also in hardware) which
tells the datapath what needs to be done (the
brain).
INSTRUCTION EXECUTION
Instruction execution
Instruction
Fetch
cycle: fetch, decode,

execute.
Fetch: fetch next
Instruction
Decode
instruction (using PC)

from memory into IR.
Decode: decode the
instruction.
Execute: execute
instruction.
Operand
Fetch
Execute
Result
Store
Next
Instruction
FETCH AND EXECUTE

Fetching an instruction and loading it into the IR is
usually referred to as the instruction fetch phase.
Performing the operation specified in the instruction
constitutes the instruction execution phase.
With few exceptions, the operation specified by an
instruction can be carried out by performing one or
more of the following actions:
Read the contents of a given memory location and load
them into a processor register.
Read data from one or more processor registers.
Perform an arithmetic or logic operation and place the
result into a processor register.
Store data from a processor register into a given memory
location.
10
SINGLE BUS ORGANIZATION

Register Y, Z and TEMP
are use only by the
processor unit for
temporary storage during
the execution of some
instructions.
Programmer cannot
access these registers
Internal
processor bus
PC
Address line
Memory
bus
Data line
Instruction
decoder and
control logic
MAR
MDR
IR
Constant 4
The IR and the

Instruction decoder are
integral parts of the control
circuitry in the processing
unit.
Control signals
...
Y
R0
Select
ALU
control
lines
MUX
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
11

The data registers, ALU
and the interconnecting
bus is referred to as data
path
Register R0 through
R(n-1) are the processor
register
These registers include
General Purpose Register
and Special Purpose
Register (stack pointer,
index register and
pointers)
The Register and ALU
are used for storing and
manipulating data
These are 2 option
provides for A & B input of
the ALU. Select by MUX
Internal
processor bus
Control signals
...
PC
Address line
Memory
bus
Data line
Instruction
decoder and
control logic
MAR
MDR
IR
Constant 4
Y
R0
Select
ALU
control
lines
MUX
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
12

Internal
processor bus
The Multiplexer (MUX)

is used to select one of
the two inputs
If select (1) select
output of Y
If select (0)- select
Constant as input A for
ALU
The constant number is
used to increment the
contents of program
counter
Control signals
...
PC
Address line
Memory
bus
Data line
Instruction
decoder and
control logic
MAR
MDR
IR
Constant 4
Y
R0
Select
ALU
control
lines
MUX
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
13
EXEC. OF VARIOUS INSTRUCTIONS
14
REGISTER TRANSFER
Register to register transfer:
For each register Ri, two
control signals:
Riin used to load the data
on the bus into the

register.
Riout to place the registers
Select
contents on the bus.
Example: To transfer
contents of R1 to R4:
Set R1out to 1. This places
contents of R1 on the bus.

Set R4in to 1. This loads
data from the processor
bus into R4.
Internal processor bus

Riin
Yin
X
Ri
Y
Constant 4
X
Riout
MUX
A
ALU
Zin
Z
X
Zout
15
ARITHMETIC/LOGIC OPERATION
ALU: Performs
arithmetic and logic

operations on its A
and B inputs.
Select
To perform
R3 R1 + R2:
1. R1out, Yin
2. R2out, Select Y, Add,
Zin
3. Zout, R3in
Riin
Yin
X
X
Constant 4
Ri
Y
X
Riout
MUX
A
ALU
Zin
Z
X
Zout
16
EXTERNAL MEMORY BUS

MDR has four control signals: MDRin, MDRout, MDRinE (for
external) and MDRoutE (for external).
Memory-bus data lines
MDRinE
MDRin
MDR
MDRoutE
MDRout
17
EXTERNAL MEMORY BUS DATAPATH

Memory-bus
data lines
Internal
processor bus
MDRin
MDRin
Address line
Control
signals
...
PC
Memory
bus
Data line
Instruction
decoder
and control
logic
MAR
MDR
IR
MDR
X
Constant
4
MDRout
MDRou
t
ALU
control
lines
R0
MU
X
Select
E
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
18
REGISTER TO/FROM MEM. TRANSFER

Memory-bus
data lines
Internal
processor bus
MDRinE
PC
MDRin
Address line
Memory
bus
MAR
IR
MDR
Constant
4
R0
X
MU
X
Select
MDRoutE
Instruction
decoder
and control
logic
MDR
Data line

Control
signals
...
MDRout
ALU
control
lines
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
19
READ A WORD FROM MEMORY

Move (R1) , R2/* R2 [[R1]]
Instruction Sequence of Action
1. MAR [R1]
2. Start a Read operation on the
memory bus
3. Wait for the MFC response
from the memory MFC
Memory-Function-Completed
Signal
4. Load MDR from the memory
bus
5. R2 [MDR]
Sequence of control steps:

1.
2.
3.
4.
5.
R1out, MARin, Read

MDRinE,
WMFC
MDRout,
R2in

Control
signals
PC
...
Address line
Memory
bus
Data line
Instruction
decoder
and control
logic
MAR
MDR
IR
Y
Constant
4
MU
X
Select
ALU
control
lines
R0
Add
Sub
:
:
ALU
Carryin
XOR
WMFC: Wait for arrival of MFC
R(n1)
TEMP
(Memory-Function-Completed) signal.
20
STORE A WORD IN MEMORY

Move R2, (R1) /* [R1] R2
Sequence of control steps:
R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC
1.

Control
signals
...
PC
Address line
Memory
bus
Data line
Instruction
decoder
and control
logic
MAR
MDR
IR
Y
Constant
4
MU
X
Select
ALU
control
lines
R0
Add
Sub
:
:
R(n1)
ALU
Carryin
XOR
TEMP
21
ARITHMETIC INSTRUCTIONS
Add R1, (R2) /* R1 <- R1 + [R2] *
Adds the contents of a memory location
pointed to by R2 to register R1.
Sequence of actions:
Fetch the instruction
Fetch the operand from memory location pointed
by R2
Perform the addition
Store the result in R1
22
INSTRUCTION FETCH AND

EXECUTION STEPS
FETCH AND EXECUTE STEPS (1/5)

Control
signals
PC
...
Sequence of control steps for the single
bus architecture as follows:

R1 <- R1 + R2
Address
Step 1 :
MAR
line
The instruction fetch operation is Memory
initiated by loading the controls of bus
MDR
Data line
PC into the MAR.
PC contents are also loaded into
Y
register Y and added constant
Constant 4
number by activating select C input
of multiplexer and add input of the
MUX
Select
ALU.
By activating Zin signal, result is
Add
A
B
ALU
Sub
stored in the register Z.
control
lines
PCout, MARin, Read, Select4, Add, Zin
XOR
AL
U
Instruction
decoder
and
control
logic
IR
RO
:
:
R(n1)
Carryin
24
TEMP

Step 2 :
The contents of register Z are

transferred to PC register by
activating Zout and PCin signal.
(Memory-Function-Completed)
signal
Control
signals
PC
Address line
Memory
bus
Data line
...
Instruction
decoder
and control
logic
MAR
MDR
IR
Zout, PCin, WMFC
Y
Constant 4
RO
Step 3 :
MUX
Select
The contents of MDR register are

transferred to the instruction register
ALU
(IR) of the processor
control
MDRout, IRin
lines
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
25

Step 4 :
The contents of register R2 are

transferred to register MAR by
activating R2out and MAR in signals.
Memory
R2out, MARin, Read
Instruction
decoder
and control
logic
MAR
bus
Data line
MDR
IR
Step 5 :
Address line

Control
signals
PC
...

transferred to register Y by activating
Select
R1out and Yin signals.
ALU
(Memory-Function-Completed)
control
lines
signals.
R1out, Yin, WMFC
Constant
4
RO
MUX
Add
Sub
:
:R1
R(n1)
R2
ALU
Carry-in
XOR
TEMP
Z
26

Step 4 :

transferred to register MAR by
activating R2out and MAR in signals.
R2out, MARin, Read
Address line
Memory
bus
Step 5 :
Instruction
decoder
and control
logic
MAR
Data line

Control
signals
PC
...
MDR
IR

transferred to register Y by activating
R1out and Yin signals.
Select
(Memory-Function-Completed) ALU
control
signals.
R1out, Yin, WMFC
lines
Y
Constant
4
RO
MUX
Add
Sub
:
:R1
R(n1)
R2
ALU
Carry-in
XOR
TEMP
Z
27

Step 6 :
MDRout , select Y, Add and Zin

signals are activated to perform
addition of contents of register Y and
the contents of MDR.
Memory
The result is stored in the registerbus
Z.
MDRout, SelectY, Add, Zin
Control
signals
PC
...
Address line
Instruction
decoder
and control
logic
MAR
Data line
MDR
IR
Y
4. Store the Result in R1

Step 7 :
The contents of register Z are

transferred to register R1 by
activating Zout and R1in signals.
Zout, R1in, End
Constant
4
RO
MUX
Select
ALU
control
lines
Add
Sub
:
:R1
R(n1)
ALU
Carry-in
XOR
TEMP
Zin
Z
Zout
28
MULTIPLE BUS ORGANIZATION

Bus A Bus B
Bus C
Bus A Bus B
Bus C
Incrementer
Instruction
decoder
PC
IR
Register
file
MUX
Constant 4
MDR
A
ALU
R
MAR
Address
line
Memory bus
data lines
29
FETCH AND EXECUTE STEPS

Summary of key steps:
30
EXAMPLE LOAD INSTRUCTION

Load R5, X(R7)
Memory address <- [PC], read
memory, IR <- memory data, PC
<- [PC] + 4
RA <- [R7]
RZ <- [RA] + immediate value X
Memory address <- [RZ], read
memory, RY <- memory data
R5 <- [RY]
31
EXAMPLE ALU INSTRUCTION

Add R3, R4, R5
memory, IR <- memory data, PC
<- [PC] + 4
RA <- [R4], RB <- [R5]
Compute the sum, RZ <- [R4] +
[R5].
RY <- [RZ]
R3 <- [RY]
32
EXAMPLE STORE INSTRUCTION

Store R6, X(R8)
memory, IR <- memory daya, PC
<- [PC] + 4
Decode, RA <- [R8], RB <- [R6]
RZ <- [RA] + immediate value X,
RM <- [RB].
Memory address <- [RZ],
memory data <- [RM], write
memory
No action.
33
EXAMPLE BRANCH INSTRUCTION

BR R5, R6
memory, IR <- Read memory, PC
<- [PC] + 4
Decode instruction, RA <- [R5],
RB <- [R6]
Compare [RA] to [RB], If [RA] =
[RB], then PC <- [PC] + Branch
offset
No action
No action
34
EXAMPLE SUBROUTINE CALL

Call R9
memory, IR <- Read memory, PC
<- [PC] + 4
Decode instruction, RA <- [R9]
PC-Temp <- [PC], PC <- [RA]
RY <- [PC-Temp]
Register LINK <- [RY]
35
CONTROL SIGNALS
CONTROL SIGNALS (1/2)
The operation of the

processors hardware
components is governed
by control signals.
These signals determine
which multiplexer input is
selected, what operation
is performed by the ALU,
etc.
37
CONTROL SIGNALS (2/2)

Examine how the processor generates the
control signals that cause the fetch and
execute actions to take place in the correct
sequence and at the right time.
There are two basic approaches:
hardwired control and microprogrammed control
38
HARDWIRED CONTROL
An instruction is executed in a sequence of
steps, where each step requires one clock cycle.
A counter as well as logic gates may be used to
keep track of the progress of execution.
Several actions are performed in each step,
depending on the instruction being executed.
In some cases, such as for branch instructions,
the actions taken depend on tests applied to the
result of a computation or a comparison
operation.
External signals, such as interrupt requests, may
also influence the actions to be performed.
39
EXAMPLE OF HARDWIRED CONTROL
Source: kuiraq.com/staff/salamhm
40
HARDWIRED CONTROL: ADV/DISADV.

Advantage:
Very fast control signals: because dedicated
control wires to each component in the CPU
Disadvantages:
Complex to be designed
Cannot be modified for changes
41
MICROPROGRAMMED CONTROL
Microinstructions are control processor within
the main processor i.e fetched and executed
much like machine instructions.
Function:
to direct the actions of the main processors
hardware components, by indicating which
control signals need to be active during each
execution step.
Using software (in terms of small instructions)

to control operations in the CPU
42
MICROPROGRAMMED CONTROL UNIT
43
MICROPROGRAMMED CONTROL UNIT

Advantage:
Control mechanism can be modified by modifying
the control instructions, not change in the
hardware
Disadvantage:
Slow control speed because CPU needs to
process the instructions before executing it
44
FINISH

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Chap 3 Processing Unit

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Faculty of Electrical and Electronic Engineering

Semester II, Session 2015/2016

In this chapter, we will discuss about the detailed process

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

RECALL: COMPUTER ORGANIZATION

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

cycle: fetch, decode,

instruction (using PC)

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

FETCH AND EXECUTE

SINGLE BUS ORGANIZATION

The IR and the

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

SINGLE BUS ORGANIZATION

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

SINGLE BUS ORGANIZATION

The Multiplexer (MUX)

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

EXEC. OF VARIOUS INSTRUCTIONS

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

on the bus into the

contents of R1 on the bus.

Internal processor bus

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

arithmetic and logic

EXTERNAL MEMORY BUS

Internal processor bus

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

EXTERNAL MEMORY BUS DATAPATH

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

REGISTER TO/FROM MEM. TRANSFER

Internal processor bus

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

READ A WORD FROM MEMORY

Sequence of control steps:

R1out, MARin, Read

Internal processor bus

WMFC: Wait for arrival of MFC

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

STORE A WORD IN MEMORY

Internal processor bus

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

INSTRUCTION FETCH AND

FETCH AND EXECUTE STEPS (1/5)

Sequence of control steps for the single

bus architecture as follows:

PCout, MARin, Read, Select4, Add, Zin

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

FETCH AND EXECUTE STEPS (2/5)

The contents of register Z are

Zout, PCin, WMFC

The contents of MDR register are

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

FETCH AND EXECUTE STEPS (3/5)

The contents of register R2 are

R2out, MARin, Read

Internal processor bus

The contents of register R1 are

R1out, Yin, WMFC

Computer Architecture and Organization (BEC30303) | Chapter 3: Processing Unit

FETCH AND EXECUTE STEPS (4/5)