Академический Документы
Профессиональный Документы
Культура Документы
To my family
CONTENTS:
1. Introduction and objectives
1.1. Introduction
1.2. Objectives
2. Multilevel Converter Topologies
2.1. Introduction
2.2. Multilevel Converter Topologies
2.2.1. Diode-Clamped Converter (DCC)
2.2.1.1.
2.2.2.2.
converters
2.2.3.2.
Topology
5.3.1.2.
Topology
5.3.1.3.
Topology
5.3.2. Flying Capacitor Converter Topology
5.4. Controllability limits
6. Contributions and General Conclusions
7. Future works
8. Publications derived from the thesis work
9. References
10. Acknowledgments
Chapter 1
Introduction and Objectives
1.1 Introduction
The Electronic Engineering Department at University of Seville has been
involved in multilevel converter topics during last 10 years. The research has
been focused on the development of new modulation strategies and new control
strategies [1]-[4]. The performance of this thesis has been the pinnacle of this
research and it would be the base for future multilevel converters research in our
department.
1.2 Objectives
The objectives in this thesis have been focused on improvements on multilevel
converter features. The first objective is centered on minimizing the
computational cost of the modulation strategy. In this thesis, the design of simple
and fast Space Vector Modulation (SVPWM) techniques reducing the
computational cost for different multilevel converter topologies is the first aim.
On the other hand, multilevel converters present problems to achieve the balance
of DC capacitors. The second objective of this thesis is the development of
simple and low-cost control strategies to get voltage balance based on the use of
redundant vectors using proposed SVPWM strategies. These control algorithms
should be completely generalized and they could be applied to different
multilevel converter topologies and for any number of levels.
Chapter 2
Multilevel Converter
Topologies
2.1 Introduction
This thesis is focused on the development of different modulation techniques and
several optimisations to improve some specific characteristics of multilevel
converters. But, in order to make the text understandable, it is necessary to make
a brief overview of the most common multilevel converter topologies introducing
the used nomenclature and the operation basis of this type of converters. So, this
chapter is dedicated to introduce the way of switching for multilevel converters
and to show the possible output voltages that can be achieved depending on the
choosing converter topology.
Multilevel converters present great advantages compared with typical and very
well known two-level converters [5][6]. These advantages are fundamentally
10
11
The proposed modification to get the three-level converter added two new
transistors per phase (see Figure 2.2). Using this new topology, each transistor
tolerates at the most a voltage equal to VDC/2. So, if these new transistors have
12
the same characteristics than the transistors in two-level case, the DC-Link
voltage can be doubled achieving a value equal to 2VDC.
But, this converter topology still has a problem. If transistors S1 and S2 are
switched on and transistors S3 and S4 are switched off, VDC voltage should be
equally shared between transistors S3 and S4. But, there is not any mechanism
that assures it. The solution of this problem appears thanks to use the clamping
diodes. In each phase, two diodes clamp each transistor voltage. Finally, in
Figure 2.2, a three-level Diode Clamped Converter (DCC) is shown. In this
converter topology, the DC-Link voltage is equally shared between capacitors C1
and C2.
13
short-circuit in some DC-Link capacitor or they let the output opened. For
instance, if S1, S2 and S3 are switched on, a short-circuit is created in capacitor
C2. Besides, the voltage in transistor S4 is VDC being its maximum admissible
voltage equal to VDC/2. The possible switching configurations are shown in
TABLE 2.I. Only three possible output phase voltages with respect to 0 (middle
point of the DC-Link) appear using this converter and this is the reason to name
this converter as a three-level converter.
S1
S2
S3
S4
Phase-0 voltage
ON
ON
OFF OFF
OFF
ON
ON
OFF
OFF OFF
ON
ON
-VDC/2
VDC/2
S1
S2
S3
S4
S5
S6
S7
S8
Phase-0 voltage
ON
ON
ON
ON
VDC/2
OFF
ON
ON
ON
ON
VDC/4
OFF OFF
ON
ON
ON
ON
OFF OFF
ON
ON
ON
ON
OFF
-VDC/4
ON
ON
ON
ON
-VDC/2
14
In general, for N-level DCC topology all the possible switching configurations
have N-1 adjacent transistors switched on in each phase and the possible output
phase voltages with respect to 0 take N discrete values in equally spaced out in
the voltage range {-VDC/2, VDC/2}.
15
17
18
The switching configurations study can be done defining each transistor couple
state in a basic cell as a binary value specifying if the couple state is low (the
lowest transistor of the basic cell is switched on) or high (the highest transistor of
the basic cell is switched on). So, for a single phase x M-cell FCC, binary factors
Hxi can be defined as follows:
19
0, S xi = OFF
H xi =
1, S xi = ON
with i = 1,..., M
(2.1)
So, in general, for M-cell FCC case, there are 2M-1 possible switching
configurations where Hxi with i=1, , M marks the state of each transistors
couple in the basic cell i in the single phase x [27].
general,
for
multilevel
FCC,
several
flying
capacitor
voltages
Figure 2.8. Four-cell single phase FCC using OFBCS voltage ratio
20
Using this voltages ratio, there are only four possible switching configurations in
each phase for two-cell single phase FCC and they are shown in TABLE 2.III
using basic cells binary values Hxi. Other possibilities are not allowed because
they create short-circuit in some capacitor or they let the output opened. It is
important to say that two different switching configurations achieve the same
output phase voltage with respect to 0. This is very important because this type of
converter has redundant switching configurations. It will be shown later that this
property can be used to improve the floating capacitors voltage control. From
TABLE 2.III it can be concluded that two-cell single phase FCC is a three-level
single phase FCC with one redundant switching configuration. The state of each
phase is denoted by an integer number where 0 means that the output Vxo
voltage is the minimum voltage possible.
Phasex-0
Phasex
voltage
State
VDC/2
Redundant switching
OFF ON
configurations
OFF OFF
-VDC/2
SX1
SX2
HX1 HX2
ON
ON
ON
OFF
The same calculations can be done using the four-cell single phase FCC topology
with OFBCS voltages ratio. In this case, there are more possible switching
configurations and they are shown in TABLE 2.IV. The calculation results show
that this topology achieves five different output voltage levels presenting several
redundant switching configurations. Using OFBCS voltages ratio, the number of
21
output levels (N) is the number of basic cells (M) plus one. In general, there is an
easy way to calculate the output phase voltage with respect to 0 thanks to the
couples binary values using OFBCS voltages ratio.
Phasex _ State = H xi
i =1
Vout
V
V
= DC Phasex _ State - DC
M
2
(2.2)
HX1
HX2
HX3
HX4
Phasex-0 voltage
Phasex_State
-VDC/2
-VDC/4
-VDC/4
-VDC/4
VDC/4
-VDC/4
VDC/4
VDC/4
VDC/4
VDC/2
22
It can be seen from TABLE 2.III and TABLE 2.IV that increasing the number of
cells of the converter, the switching configurations redundancy increases. This
redundancy implies that the same output phase voltage can be achieved thanks to
different switching configurations. This property does not appear in DCC and in
chapter 5 it will be shown that it introduces some control advantages. However, it
should not be forgotten that the control complexity increases with the number of
FCC cells because there will be more redundant switching configurations.
In [27] new flying capacitors voltage ratios were presented in order to achieve
more output voltage levels with the same number of power devices. In [27][28],
the comparison between these voltage ratios was presented using the Full Binary
Combination Schema (FBCS) concept demonstrating that, with the same number
of power devices, the number of levels in the output voltages changes depending
on the voltage ratios used in FCC. Several voltage ratios generate higher number
of levels compared with OFBCS. Therefore, at first sight, they improve the
behaviour of the converter because they achieve better output signals quality with
the same cost. However, all these possible configurations achieve phase to
middle point of the DC-Link output voltage signals in the range {-VDC/2,VDC/2}.
These voltage ratios consider that the flying capacitors voltages have the same
polarity. All the flying capacitors are charged with the desired voltage in the
same sense. A new voltage ratio is presented considering OFBCS voltage ratios
but doing that flying capacitors voltages can be positive or negative. In the
proposed voltage ratio, the sign of flying capacitor voltages (Vxi) is alternatively
positive and negative considering positive the DC-Link voltage. This proposed
voltage ratio is named New FBCS (NFBCS). In Figure 2.9, a FCC performed
with four basic cells using NFBCS is shown.
23
Figure 2.9. Four-cell single phase FCC using NFBCS voltages ratio
Using this voltage configuration, the output phase to middle point of DC-Link
voltage (Vx0) can be calculated. In TABLE 2.V, the results using OFBCS and
NFBCS voltage ratios are shown. It can be seen that with the same number of
devices (only with 4 basic cells), OFBCS achieves five output levels and NFBCS
achieves 15 levels. So, it is clear that using this new voltages ratio, with the same
number of power devices, the number of output voltage levels increases. Other
important result can be concluded from TABLE 2.V. Using OFBCS, output Vx0
voltages are located in the range {-VDC/2, VDC/2} where VDC is the DC-Link
voltage. However, using NFBCS voltages ratio the output voltages are in the
range {-2VDC, 2VDC} with the same DC-Link voltage. Therefore, two clear
advantages appear using NFBCS voltage ratio.
In general, for a M-cell FCC using OFBCS voltages ratio, the number of output
levels is N=M+1. However, using NFBCS the number of levels increases
exponentially. In Figure 2.10, the number of output levels achieved by both
voltage ratios is represented in order to show the increase of levels using NFBCS
voltages ratio.
24
Switching
Configuration
HX1HX2HX3HX4
Output Phasex-middle
point of DC-Link
Voltage/VDC
OFBCS
NFBCS
0000
-1/2
-1/2
0001
-1/4
-3/4
0010
-1/4
1/4
0011
0100
-1/4
-7/4
0101
-2
0110
-1
0111
1/4
-5/4
1000
-1/4
5/4
1001
1010
1011
1/4
7/4
1100
1101
1/4
-1/4
1110
1/4
3/4
1111
1/4
1/2
TABLE 2.V. Output voltages for four-cell FCC using OFBCS and NFBCS
voltages ratios
25
Figure 2.10. Number of levels achieved by OFBCS and NFBCS voltages ratios
depending of the number of FCC basic cells
Output voltages Vx0 range also depends on the chosen voltages ratio. Using
OFBCS, Vx0 is always in the range {-VDC/2, +VDC/2} and this range does not
depend on the number of basic cells in FCC. However, using NFBCS the output
voltage range increases. In Figure 2.11, the output voltage range depending on
the used voltages ratios is represented showing the increase depending on the
number of basic cells in the FCC.
Previously, the advantages using NFBCS in FCC have been shown. However,
some possible drawbacks appear using this new voltages ratio. Changing the sign
of flying capacitor voltages, the power semiconductors of the converter should be
chosen very carefully. Using OFBCS, each power device must support a
maximum voltage equal to VDC/M where M is the number of basic cells in the
FCC. But using NFBCS voltage ratio, each power device must support higher
voltages and due to this fact, the specifications of each power device must be
chosen in order to support this voltage. For an M-cell FCC using NFBCS, the
maximum voltage that each power device must support is (2M-1)VDC/M. This
problem also appears using other previously published voltage ratios [28].
26
Figure 2.11. Maximum output voltage obtained by OFBCS and NFBCS voltage
ratios depending of the number of FCC basic cells
On the other hand, the topology of power devices using NFBCS voltages ratio
must be different because they must be bidirectional. Actually these bidirectional
power devices are used in other converter topologies as matrix converters and
they can be found easily in the market [29]. These bidirectional power devices
use to be diode bridges or back-to-back switches. The diagram of a back-to-back
switch is shown in Figure 2.12 and it is built using a module of two reverse
blocking IGBTs. This module controls the current flow within each switch.
These power devices are actually well extended and for instance, bidirectional
power devices are performed by Dynex Semiconductors, Semelab or EUPEC.
27
From TABLE 2.VI, it can be seen that output voltage levels are equally spaced
out and all the voltage steps are equal to VDC/M. However, NEFBCS ratio makes
smaller the output voltage range. In general, for a M-Cell FCC the output voltage
range is {(-3/2+1/M)VDC,(-3/2+1/M)VDC}. So, it can be seen that increasing the
number of basic cells, the maximum output voltage using NEFBCS is smaller
than the obtained using NFBCS. Besides, the number of output voltage levels
depends on the chosen voltages ratio. Figure 2.14 and Figure 2.15 show a
comparison between OFBCS, NFBCS and NEFBCS voltages ratios.
28
Switching Configuration
Sx1Sx2Sx3Sx4
NEFBCS
0000
-1/2
-1/2
0001
-3/4
-3/4
0010
1/4
0011
-1/4
0100
-7/4
-1
0101
-2
-5/4
0110
-1
-1/2
0111
-5/4
-3/4
1000
5/4
3/4
1001
1/2
1010
5/4
1011
7/4
1100
1/4
1101
-1/4
1110
3/4
3/4
1111
1/2
1/2
TABLE 2.VI. Output voltages VX0 in four-cell FCC using NFBCS and NEFBCS
voltages ratios
29
Figure 2.13. Four-cell single phase FCC using NEFBCS voltages ratio
Figure 2.14. Maximum output voltage depending on the number of basic cells in
FCC using different flying capacitor voltage ratios
30
Figure 2.15. Number of output voltage levels depending on the number of basic
cells in the FCC using different flying capacitor voltage ratios
As conclusions, new flying capacitor voltages ratios using the Full Binary
Combination Schema (FBCS) have been studied in order to improve the output
signals features for multilevel FCC. These voltage ratios use positive and
negative flying capacitor voltages. The results show that an increase in the output
voltages range and an increase in the number of levels of the converter is
achieved with the same number of power devices and with the same DC-Link
capacitors voltage. Therefore, to obtain the same maximum output voltage, the
DC-Link capacitors voltage can be reduced and the power devices can have
lower
voltage
requirements.
Besides,
discussions
about
the
physical
31
32
Considering the three-level basic cell, it is clear that only one transistor of each
leg (S1-S1, S2-S2) can be switched on at the same time. In order to facilitate the
notation of the possible switching configurations, for each basic cell in phase x,
binary factors Hxi can be defined as follows:
(2.3)
So, using this binary notation, the possible switching configurations of the threelevel basic cell are shown in TABLE 2.VII.
33
HX1
HX2
VAB
-VDC
VDC
This three-level converter is the basic cell that is used to build multilevel
cascaded converters. A multilevel cascaded converter is easily built connecting
basic three-level cells in series. For instance, the two basic cells cascaded
converter is shown in Figure 2.17. It is important to notice that each basic cell
needs an independent voltage source and this is one of the most important
drawbacks of this multilevel converter topology.
H xi = H x (i +1)
0,
1, H xi = 1 and H x (i +1) = 0
(2.4)
And finally, the phase state and the output phase-to-neutral voltages can be
determined using the FCxi parameter as follows:
35
(2.5)
i =1
Cell 1
Cell 2
Vxn voltage
Phasex_State
VDC
-VDC
VDC
2VDC
VDC
-VDC
-2VDC
-VDC
VDC
-VDC
HX1
HX2
HX3
HX4
TABLE 2.VIII. Output voltages for a two basic cells cascaded converter using
classic voltage ratio (all DC voltage sources have the same value)
36
Using classic voltage sources ratio, a diagram of the necessary basic cells to
obtain multilevel cascaded converters is shown in Figure 2.18. The number of
three-level basic cells to build a N-level cascaded converter is (N-1)/2 with N
odd.
Figure 2.18. Diagram of the necessary basic three-level cells to obtain different
multilevel single-phase cascaded converters
37
Other DC voltage sources ratios can be taken into account [31]. A generalized
study can be done for the two basic cells single phase cascaded converter. In this
case, the possible output phase-to-neutral voltages can be calculated and they are
shown in TABLE 2.IX.
Cell 1
Cell 2
Vxn voltage
HX1
HX2
HX3
HX4
VDC2
-VDC2
VDC1
VDC1+ VDC2
VDC1- VDC2
VDC1
-VDC1
VDC2- VDC1
-VDC1 -VDC2
-VDC1
VDC2
-VDC2
TABLE 2.IX. Generalized output phase-to-neutral voltages for a two basic cells
single phase cascaded converter
38
So, depending on the DC voltage sources values, different number of levels can
be obtained in the output voltages. For instance, if VDC2 is three times VDC1, nine
different levels appear in the output voltages. It can be seen in TABLE 2.X.
Cell 1
Cell 2
Vxn voltage
Phasex_State
3VDC1
-3VDC1
VDC1
4VDC1
-2VDC1
VDC1
-VDC1
2VDC1
-4VDC1
-VDC1
3VDC1
-3VDC1
HX1
HX2
HX3
HX4
TABLE 2.X. Output phase-to-neutral voltages for a two basic cells single phase
cascaded converter considering VDC2=3VDC1
39
40
41
42
43
Chapter 3
Multilevel Converter Models
3.1 Introduction
It is very important to develop mathematical models for multilevel converters to
carry out simulations to find out the system response to different control
strategies. In fact, the first step of the implementation of a control algorithm is to
simulate it and to see if the simulation results are satisfactory. In this thesis,
several multilevel converters analytical models have been developed. These
models are built thanks to commutation models and the definition of the
switching functions that will be presented in this chapter. The simulation models
were developed using MatLab/Simulink software helping to the performance of
the control algorithms presented in this thesis. All mathematical models are
based on the determination of state equations for dynamical variables introduced
in [1]. These models are conspicuous by their extreme simplicity in front of other
previous analytical models presented in the literature [32]-[36].
44
In this converter, only one of the transistors can be switched on at the same time.
If S1 transistor is switched on, the output phase voltage with respect to the
reference (see figure 3.1) is VDC/2 and if S2 transistor is switched on, the output
phase voltage with respect to the reference is -VDC/2. In order to simplify the
circuit, it is possible to replace the phase using an ideal switch that connects the
output to the possible voltage connection points of the system. The switching
functions are defined as Sij where i is the phase and j is the point where the phase
i output is connected (it is supposed that 0 is the lowest voltage connection
value). The switching function Sij is equal to 1 if the phase i is connected to the
voltage connection point j and 0 if the phase i is connected to other voltage
connection point. The simplification of the two level single phase converter can
be seen in Figure 3.2.
45
Figure 3.2. Phase of the conventional two-level converter using an ideal switch
The implemented analytical models need the state equations for the DC
capacitors voltages and the phase currents. This chapter is focused on the
determination of these state equations depending on the multilevel converter
topology. Using matrix notation, the state equations can be described as follows.
dWJx1
= AJxJ WJx1 + BJx1VDC
dt
46
(3.1)
3L3W Three-level DCC can be easily extended increasing the number of levels.
The commutation model of the 3L3W N-level DCC is shown in Figure 3.4. In
the N-level case, the mathematical model uses switching functions Sij where i
{a,b,c} and j {0,1,, N-1}.
47
48
i1 = C1
iN-1 = CN-1
dVC( N-1)
dt
(3.2)
1
2
3
1
N-4
N-3
N -2
F1 +
F2 +
F3 + ... + FN-1 + ... +
FN-4 +
FN-3 FN-2
N -1
N -1
N -1
N -1
N -1
2 2
N-1
49
where
Fi = ( Sai ia + Sbi ib + Sci ic )
(3.3)
And finally, the state equations of the DC-Link capacitors voltages are presented.
1
dVC 1 1
= - f1 F1 - f2 F2 - f3 F3 - ... - FN -1 - ... - g3 FN -4 - g2 FN -3 - g1 FN -2
2 2
dt
C1
1
1
dVC 2
= g1 F1 - f2 F2 - f3 F3 - ... - FN -1 - ... - g3 FN -4 - g2 FN -3 - g1 FN -2
2 2
dt
C2
dVC 3
1
1
= g1 F1 + g2 F2 - f3 F3 - ... - FN -1 - ... - g3 FN -4 - g2 FN -3 - g1 FN -2
2 2
dt
C3
(3.4)
1
1
dVC 4
= g1 F1 + g2 F2 + g3 F3 - ... - FN -1 - ... - g3 FN -4 - g2 FN -3 - g1 FN -2
2 2
dt
C4
.....
dVC ( N -1)
dt
1
1
g1 F1 + g2 F2 + g3 F3 + ... + FN -1 + ... + f3 FN -4 + f2 FN -3 - f1FN -2
2 2
C N -1
where
N - 1- i
N -1
i
gi =
N -1
fi =
(3.5)
In order to determine the state equations for the phase currents, the output phase
voltages with respect to 0 (lowest point of the DC-Link) are calculated as
follows.
50
dia
dt
dib
dt
(3.6)
dic
dt
3L3W topology fulfils that the voltage of the neutral point of the load with
respect to 0 is determined as follows.
VN 0 =
Va 0 + Vb 0 + Vc 0
3
(3.7)
The phase voltages with respect to the neutral point of the load are determined.
VaN = Va 0 - VN 0 = Ra ia
VbN = Vb 0 - VN 0 = Rb ib
(3.8)
VcN = Vc 0 - VN 0 = Rc ic
51
dia
R
V
= - a ia + C1 2(Sa1 + ... + Sa( N-2) ) - (Sb1 + ... + Sb( N-2) ) - (Sc1 + ... + Sc( N-2) ) +
3L
dt
L
V
+ C2 2(Sa2 + ... + Sa( N-2) ) - (Sb2 + ... + Sb( N-2) ) - (Sc 2 + ... + Sc( N-2) ) +
3L
VC3
2(Sa 3 + ... + Sa( N-2) ) - (Sb3 + ... + Sb( N-2) ) - (Sc 3 + ... + Sc( N-2) ) +
+
3L
+... +
+
VC( N-2)
dib
R
V
= - b ib + C1 -(Sa1 + ... + Sa( N-2) ) + 2(Sb1 + ... + Sb( N-2) ) - (Sc1 + ... + Sc( N-2) ) +
3L
dt
L
VC2
-(Sa2 + ... + Sa( N-2) ) + 2(Sb2 + ... + Sb( N-2) ) - (Sc 2 + ... + Sc( N-2) ) +
+
3L
V
+ C3 -(Sa3 + ... + Sa( N-2) ) + 2(Sb3 + ... + Sb( N-2) ) - (Sc 3 + ... + Sc( N-2) ) +
3L
+... +
+
VC( N-2)
dic
R
V
= - c ic + C1 -(Sa1 + ... + Sa( N-2) ) - (Sb1 + ... + Sb( N-2) ) + 2(Sc1 + ... + Sc( N-2) ) +
dt
L
3L
VC2
-(Sa2 + ... + Sa( N-2) ) - (Sb2 + ... + Sb( N-2) ) + 2(Sc 2 + ... + Sc( N-2) ) +
+
3L
V
+ C3 -(Sa3 + ... + Sa( N-2) ) - (Sb3 + ... + Sb( N-2) ) + 2(Sc 3 + ... + Sc( N-2) ) +
3L
+... +
VC( N-2)
+
(-Sa( N-2) - Sb( N-2) + 2Sc( N-2) ) +
3L
V
+ DC (-Sa( N-1) - Sb( N-1) + 2Sc( N-1) )
3L
52
(3.9)
53
So, the expressions presented for the 3L3W topology are valid but imposing that
VN0 is equal to the middle DC-Link voltage. Hence, state equations for the DCLink capacitors voltage for 3L4W DCC are (3.4). Nevertheless, the phase
currents state equations change due to the presence of the fourth wire connecting
the neutral point of the load with the middle point of the DC-Link. So, using
3L4W-DCC topology, the phase voltages with respect to the neutral point of the
load can be determined.
VDC
= Ra ia
2
V
= Vb 0 - DC = Rbib
2
V
= Vc 0 - DC = Rc ic
2
VaN = Va 0 VbN
VcN
(3.10)
dia
R
V
1
= - a ia - DC + VC1 (Sa1 + ... + Sa( N-2) ) + VC2 (Sa2 + ... + Sa(N-2) ) +
dt
L
2L L
+... + VC(N-2)Sa(N-2) + VDCSa( N-1)
dib
R
V
1
= - b ib - DC + VC1 (Sb1 + ... + Sb( N-2) ) + VC 2 (Sb2 + ... + Sb( N-2) ) +
dt
L
2L L
+... + VC( N-2)Sb(N-2) + VDCSb( N-1)
dic
R
V
1
= - c ic - DC + VC1(Sc1 + ... + Sc( N-2) ) + VC 2 (Sc2 + ... + Sc( N-2) ) +
dt
L
2L L
+... + VC(N-2)Sc(N-2) + VDCSc( N-1)
54
(3.11)
It can be seen that the DC-Link capacitors voltages state equations can be
determined using (3.4) where fi and gi were defined in (3.5) but assuming that Fi
functions can be determined as follows.
55
Fi = Sai ia + Sbi ib + Sci ic + Sdi iN = (Sai - Sdi )ia + (Sbi - Sdi )ib + (Sci - Sdi )ic
(3.12)
On the other hand, the voltage of the neutral point of the load with respect to 0
(lowest point of the DC-Link) can be determined.
(3.13)
The phase voltages with respect to 0 are calculated thanks to expression (3.6) and
finally, using (3.8), the phase currents state equations are presented.
56
dia
R
V
= - a ia + C1 (Sa1 + ... + Sa( N-2) ) - (Sd1 + ... + Sd( N-2) ) +
dt
L
L
V
+ C 2 (Sa2 + ... + Sa( N-2) ) - (Sd2 + ... + Sd( N-2) ) +
L
V
+ C 3 (Sa3 + ... + Sa( N-2) ) - (Sd3 + ... + Sd( N-2) ) + ... +
L
VC( N-2)
Sa( N-2) - Sd( N-2) +
+
L
+
VDC
Sa( N-1) - Sd( N-1)
L
dib
R
V
= - b ib + C1 (Sb1 + ... + Sb( N-2) ) - (Sd1 + ... + Sd( N-2) ) +
dt
L
L
V
+ C 2 (Sb2 + ... + Sb( N-2) ) - (Sd2 + ... + Sd( N-2) ) +
L
V
+ C 3 (Sb 3 + ... + Sb( N-2) ) - (Sd3 + ... + Sd( N-2) ) + ... +
L
VC( N-2)
Sb( N-2) - Sd( N-2) +
+
L
+
(3.14)
VDC
Sb( N-1) - Sd( N-1)
L
dic
R
V
= - c ic + C1 (Sc1 + ... + Sc( N-2) ) - (Sd1 + ... + Sd( N-2) ) +
dt
L
L
V
+ C 2 (Sc2 + ... + Sc( N-2) ) - (Sd2 + ... + Sd( N-2) ) +
L
V
+ C 3 (Sc 3 + ... + Sc( N-2) ) - (Sd3 + ... + Sd( N-2) ) + ... +
L
VC( N-2)
Sc( N-2) - Sd( N-2) +
+
L
+
VDC
Sc( N-1) - Sd( N-1)
L
57
Figure 3.8. Single phase FCC. In the three-phase model, each phase is connected
to an RL load.
58
H xi = H x (i +1)
0,
1, H xi = 1 and H x (i +1) = 0
(3.15)
Using this definition, the state equations for multilevel FCC can be easily
determined. In general, for M-cell FCC it can be determined currents that flow
through the floating capacitors in phase x.
dVCx1
= FCx1ix
dt
dV
= Cx 2 Cx 2 = FCx 2ix
dt
.....
iCx1 = C p1
iCx2
dVCx( M -1)
dt
(3.16)
= FCx( M -1)ix
And the state equations of the floating capacitor voltages can be determined.
dVCx1 FCx1ix
=
dt
Cx1
dVCx 2 FCx2ix
=
dt
Cx2
.....
dVCx( M -1)
dt
(3.17)
FCx( M -1) ix
Cx( M -1)
These expressions are valid for every flying capacitor voltage ratio only taking
into account that depending on the chosen flying capacitor voltage ratio (OFBCS,
NFBCS or NEFBCS), the flying capacitor voltages (VCxi) magnitude and sign
change.
59
In order to determine the state equations for the phase currents, only the two-cell
FCC case is shown because increasing the number of cells, expressions are not
easily extended. Anyway, expressions for a large number of cells can be
calculated following the same steps presented in this thesis.
The output phase voltages with respect to 0 (lowest point of the DC-Link) are
calculated as follows using two-cell OFBCS ratio.
VDC
V
di
+ FCa1 ( DC - VCa1 )] + Sa 2 VDC - L a
2
2
dt
V
V
di
Vb 0 = Sb1[ DC + FCb1 ( DC - VCb1 )] + Sb 2V DC - L b
2
2
dt
V
V
di
Vc 0 = Sc1[ DC + FCc1 ( DC - VCc1 )] + Sc 2 VDC - L c
2
2
dt
V a 0 = Sa 1 [
(3.18)
dia
dt
dib
Vb 0 = -Sb 0VCb1 + Sb 2VDC + Sb 3 (VDC + VCb1 ) - L
dt
di
Vc 0 = -Sc 0VCa1 + Sc 2 VDC + Sc 3 (VDC + VCc1 ) - L c
dt
Va0 = -Sa 0VCa1 + Sa 2VDC + Sa 3 ( VDC + VCa1 ) - L
(3.19)
3L3W topology fulfils that the voltage of the neutral point of the load with
respect to 0 is determined using (3.7) and the phase voltages with respect to the
neutral point of the load are determined using (3.8). Finally, the phase currents
state equations for two-cell FCC using OFBCS ratio are presented.
60
+VDC
+VDC
+VDC
dia
R
2
1
1
= - a ia - Sa1FCa1VCa1 + Sb1FCb1VCb1 + Sc1FCc1VCc1 +
3L
3L
3L
dt
L
1
1
[Sa1(1 + FCa1 ) + 2Sa2 ] - [Sb1(1 + FCb1) + Sc1(1 + FCc1 ) + 2(Sb2 + Sc2 )]
3L
6L
2
1
1
dib
R
= - b ib - Sb1FCb1VCb1 + Sa1FCa1VCa1 + Sc1FCc1VCc1 +
3L
3L
3L
dt
L
1
1
[Sb1(1 + FCb1) + 2Sb2 ] - [Sa1(1 + FCa1 ) + Sc1(1 + FCc1 ) + 2(Sa2 + Sc2 )]
3L
6L
dic
R
2
1
1
= - c ic - Sc1FCc1VCc1 + Sa1FCa1VCa1 + Sb1FCb1VCb1 +
dt
L
3L
3L
3L
1
1
[Sc1(1 + FCc1 ) + 2Sc2 ] - [Sa1(1 + FCa1 ) + Sb1(1 + FCb1 ) + 2(Sa2 + Sb2 )]
3L
6L
}
}
(3.20)
The phase currents state equations for two-cell FCC using NFBCS and NEFBCS
ratios are presented.
dia
R
1
= - a ia + [2VCa1 (-Sa0 + Sa3 ) - VCb1 (-Sb0 + Sb 3 ) - VCc1(-Sc0 + Sc 3 ) +
dt
L
3L
-VDC (2Sa2 + 2Sa3 - Sb 2 - Sb3 - Sc 2 - Sc 3 )]
dib
R
1
= - a ib + [-VCa1(-Sa0 + Sa3 ) + 2VCb1(-Sb0 + Sb 3 ) - VCc1(-Sc0 + Sc 3 ) +
dt
L
3L
(3.21)
-VDC (-Sa 2 - Sa3 + 2Sb2 + 2Sb 3 - Sc 2 - Sc 3 )]
dic
R
1
= - c ic + [-VCa1(-Sa0 + Sa3 ) - VCb1 (-Sb0 + Sb3 ) + 2VCc1 (-Sc0 + Sc3 ) +
dt
L
3L
-VDC (-Sa 2 - Sa3 - Sb2 - Sb 3 + 2Sc 2 + 2Sc 3 )]
61
dia
R
V
S
= - a ia + DC [Sa1 (1 - FC a1 ) + 2Sa 2 - 1] + VCa1 a1 FC a1
dt
L
2L
L
dib
R
V
S
= - b ib + DC [Sb1 (1 - FCb1 ) + 2Sb 2 - 1] + VCb1 b1 FCb1
2L
dt
L
L
dic
R
V
S
= - c ic + DC [Sc1 (1 - FCc1 ) + 2Sc 2 - 1] + VCc1 c1 FCc1
dt
L
2L
L
(3.22)
dia
R
V
V
1
= - a ia + Ca1 (Sa 3 - Sa0 ) + DC (Sa 2 + Sa 3 - )
dt
L
L
L
2
dib
R
V
V
1
= - b ib + Cb1 (Sb 3 - Sb0 ) + DC (Sb 2 + Sb 3 - )
dt
L
L
L
2
dic
Rc
VCc1
VDC
1
= - ic +
(Sc 3 - Sc0 ) +
(Sc 2 + Sc 3 - )
dt
L
L
L
2
62
(3.23)
VDC
V
) + DC ] + Sd 2 VDC
2
2
(3.24)
(3.25)
Finally, using (3.18) and (3.19), the flying capacitor current state equations are
presented. For two-cell OFBCS ratio,
63
dia VDC
=
[Sa1 (1 - FCa1 ) + 2(Sa 2 - Sd 2 ) - Sd1 (1 - FCd1 )] +
dt
2L
V
V
R
+ Ca1 Sa1FCa1 - Cd1 Sd1FCd1 - a ia
L
L
L
dib VDC
=
[Sb1 (1 - FCb1 ) + 2(Sb 2 - Sd 2 ) - Sd1 (1 - FCd1 )] +
dt
2L
V
V
R
+ Cb1 Sb1FCb1 - Cd1 Sd1FCd1 - b ib
L
L
L
dic VDC
=
[Sc1 (1 - FCc1 ) + 2(Sc 2 - Sd 2 ) - Sd1 (1 - FCd1 )] +
dt
2L
V
V
R
+ Cc1 Sc1 FCc1 - Cd1 Sd1 FCd1 - c ic
L
L
L
(3.26)
dia
R
V
V
V
= - a ia + Ca1 (Sa3 - Sa0 ) - Cd1 (Sd3 - Sd0 ) + DC (Sa2 + Sa3 - Sd2 - Sd3 )
dt
L
L
L
L
dib
R
V
V
V
= - b ib + Cb1 (Sb3 - Sb0 ) - Cd1 (Sd3 - Sd0 ) + DC (Sb 2 + Sb 3 - Sd2 - Sd3 )
dt
L
L
L
L
(3.27)
dic
Rc
VCc1
VCd1
VDC
= - ic +
(Sc 3 - Sa0 ) (Sd3 - Sd0 ) +
(Sc 2 + Sc 3 - Sd2 - Sd3 )
dt
L
L
L
L
64
dia - Ra
0
0 - Sa1FCa1
Sb1FCb1
Sc1FCc1
dt
L
3L
3L
3L
Rb
1
2
1
di
6L[2Sa1(1+ FCa1) + 4Sa2 - Sb1(1+ FCb1) - 2Sb2 - Sc1(1+ FCc1) - 2Sc2 ]
b
0
0
Sa1FCa1 - Sb1FCb1
Sc1FCc1
ia
L
3L
3L
3L
dt
R
1
1
2
i
[2S (1+ FCb1) + 4Sb2 - Sa1(1+ FCa1) - 2Sa2 - Sc1(1+ FCc1) - 2Sc2 ]
0 - c
Sa1FCa1
Sb1FCb1 - Sc1FCc1 b 6L b1
dic 0
L
3
L
3
L
3
L
dt
c
+ 1 [2S (1+ FC ) + 4S - S (1+ FC ) - 2S - S (1+ FC ) - 2S ]VDC
dV = FCa1
c1
c2
a1
a1
a2
b1
b1
b2
VCa1 6L c1
0
0
0
0
0
Ca1 C
a1
VCb1
dt
0
dVCb1
FCb1
VCc1
0
0
0
0
0
0
Cb1
dt
0
dVCc1
FC
c1
0
0
0
0
0
dt
Cc1
Two-cell 3L3W FCC state equations using NFBCS or NEFBCS voltages ratio
2
1
1
dia - Ra
0
0
(-Sa0 + Sa3) - (-Sb0 + Sb3 ) - (-Sc0 + Sc3 )
dt
L
3L
3L
3L
Rb
1
2
1
di
- 3L [2Sa2 + 2Sa3 - Sb2 - Sb3 - Sc2 - Sc3]
b
0
0
- (-Sa0 + Sa3)
(-Sb0 + Sb3 ) - (-Sc0 + Sc3 )
ia
L
3L
3L
3L
dt
R
1
1
2
i
- [-S - S + 2Sb2 + 2Sb3 - Sc2 - Sc3 ]
- c - (-Sa0 + Sa3 ) - (-Sb0 + Sb3 )
(-Sc0 + Sc3) b 3L a2 a3
0
dic 0
ic
3L
L
3L
3L
dt
+ - 1 [-S - S - S - S + 2S + 2S ]VDC
dV = FCa1
c2
c3
VCa1 3L a2 a3 b2 b3
0
0
0
0
0
Ca1 - C
V
dt a1
Cb1
0
dVCb1
FCb1
V
0
0
0
0
0
Cc
1
Cb1
dt
0
dVCc1
FCc1
0
0
0
0
0
dt
Cc1
66
dia - Ra
0
0
0
0
Sa1FCa1
dt
L
L
Rb
1
di
2L [Sa1(1- FCa1 ) + 2Sa2 -1]
b
0
0
0
0
Sb1FCb1
ia
L
L
dt
1
1
R
i
[S (1- FCb1) + 2Sb2 -1]
0
0
0
- c
Sc1FCc1 b 2L b1
dic 0
ic
L
L
dt
+ 1 [S (1- FC ) + 2S -1]VDC
dV = FCa1
c1
c2
0
0
0
0
0 VCa1 2L c1
Ca1 C
V
dt a1
Cb1
0
dVCb1
FCb1
0
0
0
0 VCc1
0
0
C
dt
1
b
dVCc1
FCc1
0
0
0
0
0
dt
Cc1
67
Two-cell 3L4W FCC state equations using NFBCS or NEFBCS voltages ratio
1
dia - Ra
0
0
(Sa3 - Sa0 )
0
0
dt
L
L
1
1
Rb
1
+
(
S
S
)
di
2
3
a
a
L
b
0
0
0
(Sb3 - Sb0 )
0
2
ia
L
L
dt
1
1
1
R
i
(S + S - )
0
0
0
(Sc3 - Sc0 ) b L b2 b3 2
- c
dic 0
L
L
ic
dt
+ 1 (S + S - 1)VDC
=
FCa1
dV
0
0
0
0
0
VCa1 L c2 c3 2
Ca1 - C
V
dt a1
0
Cb1
dVCb1
FCb1
VCc1
0
0
0
0
0
0
C
dt
1
b
dVCc1
FCc1
0
0
0
0
0
dt
Cc1
68
dia - a
0
0
0
0
Sa1FCa1
- Sd1FCd1
L
L
dt L
1
1
Rb
1
di
0
0
0
Sb1FCb1
- Sd1FCd1
b 0
[Sa1(1- FCa1 ) + 2(Sa2 - Sd 2 ) - Sd1(1- FCd1)]
L
L
L
2L
dt
ia
Rc
1
1
i 1
di
0
0
0
0
S
FC
S
FC
c
c1
c1
d1
d1
b 2L [Sb1(1- FCb1) + 2(Sb2 - Sd 2 ) - Sd1(1- FCd1 )]
L
L
L
dt
ic
dV FCa1
1 [S (1- FC ) + 2(S - S ) - S (1- FC )]
0
0
0
0
0
0
Ca1
c2
d2
d1
d1
c1
V
= C
VCa1 + 2L c1
DC
dt a1
VCb1
0
FCb1
dVCb1
0
0
0
0
0
0
VCc1
Cb1
0
dt
Cd1
0
dVCc1
FCc1
0
0
0
0
0
0
dt
C
c1
dVCd1
FCd1
0
0
0
0
0
dt 0
d1
69
Two-cell 4L4W FCC state equations using NFBCS or NEFBCS voltages ratio
1
1
Ra
- (Sd3 - Sd0 )
0
0
(Sa3 - Sa0 )
0
0
-L
L
L
dia
Rb
1
1
dt 0
1
- (Sd 3 - Sd 0 )
0
0
(Sb3 - Sb0 )
0
L (Sa2 + Sa3 - Sd 2 - Sd 3)
L
L
L
dib
ia
Rc
1
1
dt 0
0
0
0
(Sc3 - Sc0 ) - (Sd 3 - Sd 0 ) ib 1 (Sb2 + Sb3 - Sd 2 - Sd 3)
L
L
L
L
dic FC
ic
1 (S + S - S - S )
dt - a1
0
0
0
0
0
0
c2
c3
d2
d 3 VDC
dV = Ca1
VCa1 + L
VCb1
Ca1
0
FC
dt 0
- b1
0
0
0
0
0
Cb1
dVCb1
0
VCc1
Cd1
0
FC
dt 0
- c1
0
0
0
0
0
dVCc1
Cc1
dt
FC
0
0
0
0
0
0
- d1
Cd1
70
Chapter 4
Modulation Techniques for
Multilevel Converters
4.1 Introduction
In previous chapters, several multilevel converter topologies have been
presented. Each topology has different switching configurations in order to
achieve the desired output signals. The converter switching must be controlled to
follow a control reference and modulation strategies are in charge to define the
switching control in the converter. The primary objective of the modulation
algorithm is to synthesize a control reference obtaining a pulse train with the
same averaged value. Several modulation strategies have been proposed in the
literature. Pulse Width Modulation (PWM) and Space Vector PWM (SVPWM)
techniques are typical modulation strategies and they are explained in the next
points.
72
Figure 4.1. Conventional two-level PWM. The low frequency reference signal is
modulated using a triangular carrier with higher frequency.
Figure 4.2. Five-level PWM schema using four triangular carriers disposed to
carry out PD-PWM.
73
Figure 4.3. Five-level PWM schema using four triangular carriers disposed to
carry out POD-PWM.
Figure 4.4. Five-level PWM schema using four triangular carriers disposed to
carry out APOD-PWM.
74
Some authors have compared the different PWM strategies showing the spectral
analysis produced by the modulation processes [41]. These studies say that PDPWM is harmonically superior across the bulk of the modulation region because
is the only technique which places harmonic energy into a common mode carrier
harmonic which cancels in the line to line voltage. In order to show the
modulation quality of the presented PWM schemes, the total harmonic distortion
(THD) using PD-PWM, POD-PWM and APOD-PWM are shown in Figure 4.5,
Figure 4.6 and Figure 4.7 respectively and several PWM comparisons are present
in the literature [42]-[44]. Finally, it must be noticed that many more strategies
have been proposed in order to improve some characteristics of the converter
operation [45]-[50].
75
76
77
VDC
2
C1
S1
S5
S3
a
VDC
2
C2
S2
load
S4
load
S6
load
78
follow. This reference signal ( u ref ) is sampled with a constant frequency and the
converter generates it using a linear combination of possible state vectors. So, the
modulation technique samples the reference signal and looks for the three nearest
state vectors determining their three duty cycles respectively [51]. Hence, the
output signal achieved by the converter is equal to the reference signal averaged
over a sampling period. In order to illustrate SVPWM method, in Figure 4.10 the
r
79
Figure 4.10. Reference vector synthesis using the three nearest state vectors in
the control region
The state vectors space increasing the number of levels of the converter can be
determined in the same way that two-level converter control region was
calculated [53]. For instance, the state vectors space for a five-level DCC is
shown in Figure 4.11. In this case, there are 27 possible different state vectors
and they are also placed in the ab plane forming two concentric hexagons. Only
19 different positions in the ab plane cover the 27 different state vectors and
therefore, there are 8 redundant vectors in five-level DCC state vectors space.
80
It is easy to determine the state vectors space for N-level DCC and it is shown in
Figure 4.12. It is clear that increasing the number of levels, new and concentric
hexagons appear. Besides, the redundancy of the vectors increases if the state
vectors are close to the origin. Increasing the number of levels in the DCC, the
number of triangular sectors that compose the total control region increases and
the search for the three nearest state vectors increases its difficulty. Several
generalized modulation algorithms for multilevel converters have been recently
proposed [53]-[63]. An effective approach that drastically reduces the
computational load using a decision-making algorithm was presented in [64].
The proposed method was based on the decision-based pulse width modulation
introduced in [65]. As it was said before, any modulation algorithm has to carry
out two different tasks. The first one is to identify the three nearest state vectors
to the reference vector. After that, the modulation algorithm has to calculate each
state vector duty cycle.
81
One of the most important contributions of [64] is that the normalised reference
voltage vector u* is transformed into uflat scaling u* imaginary part and
multiplying it by 1
1
3
the
imaginary part of the reference vector making the search for the nearest state
vectors very simple and fast
82
In [64], the first problem is solved for the reference vector in the first sextant.
However, this reference vector can be located in any of the six sectors of the
regular hexagon which contain the switching state vectors. This problem was
solved rotating the reference vector anti-clockwise by an angle (n-1)/3, where n
is the sextant number, n = 1,,6. This rotation displaces any reference vector to
the first sextant to be studied there. This algorithm clearly improves the results of
previous modulation algorithms due to the fact that its simplicity is very high.
Nevertheless, there are several complex operations as the rotation to the first
sextant and the inverse rotation to obtain the final switching sequence and the
final on-state durations.
In order to eliminate these complex operations, a new and faster modulation
algorithm was proposed in [66]. On the same way, the state vectors space is
flattened in order to achieve 45 lines but online calculations are reduced due to
the fact that the modulation algorithm implies only very simple calculations. The
modulation algorithm obtains the switching sequence and the duty cycles in the
simplest way. This modulation algorithm based on geometrical considerations.
One N-level state vectors space sector is shown in Figure 4.14. Each state vector
is represented using the expression {x,y,z}. For example, if it is considered the
state vector {320}, that means that x=3 (phase a state is 3), y=2 (phase b state is
2) and z=0 (phase c state is 0).
It can be easily determined x graphically. y can be calculated limiting vertically
the region where the reference vector is pointing to. Thus, every reference vector
located in this state vectors space sector fulfils that z component is always zero.
x = integer (uan+ubn)
y=integer (2ubn)
(4.1)
z=0
83
u n=-u n+1
u
050
150
250
040
140
030
350
240
130
020
450
340
230
120
010
0.5
u n=-u n+2
330
110
000
320
010
u n=1
530
430
210
u n=1.5
540
440
220
u n=2
550
310
210
510
410
310
u n=0.5
520
420
410
510
Once x, y and z are determined, it is known that the reference voltage is pointing
to a sub-region in this sector. Figure 4.15 shows a generic sub-region in zone 1.
This sub-region is divided in two different triangles.
84
It is necessary to know which is the triangle where the reference vector is found
to determine the other states and the switching times. The condition that the
reference vector should fulfill to be found in triangle number one is:
ub n < ua n + y - x
ub n - ua n < ( y - x)
(4.2)
It must be noticed that this modulation algorithm drastically reduces the online
calculations due to the fact that the search for the nearest state vectors implies
only very simple calculations. The modulation algorithm obtains the switching
sequence and the duty cycles in the simplest way.
In 3L4W converters zero current can flow through the neutral wire and the phase
currents could be not equilibrated. In this case, the g coordinate of the phase-toneutral voltages (VXN) could be not equal to zero and the state vectors space can
not be represented only using the ab plane. Therefore, a three dimensional
representation must be used in order to represent the state vectors space for
3L4W converters.
Previous authors have represented the state vectors space for 3L4W converters
using three dimensional abg coordinates [67]. It can be easily represented and for
instance, the state vectors space for two-level 3L4W conventional converters and
five-level 3L4W DCC are shown in Figure 4.17 and Figure 4.18 respectively.
Figure 4.17. State vectors space for two-level 3L4W conventional converters
using abg coordinates
86
In the three dimensional case, the reference voltage ( u ref ) must be generated
carrying out a linear combination of the four nearest vectors. These nearest state
vectors form a volume (a tetrahedron) and therefore 3D SVPWM algorithms
have to find out the tetrahedron where the reference vector is pointing to. After
discovering the tetrahedron, the modulation algorithm knows the four nearest
vectors (they are the vertexes of the tetrahedron) to carry out the linear
combination of them in order to generate the reference vector averaged over a
sampling period. An example of the reference vector generation in a five-level
DCC is shown in Figure 4.19.
87
Figure 4.19. Reference vector generation using the four nearest vectors in a fivelevel 3L4W DCC
Using abg coordinates, the possible tetrahedrons that compose the state vectors
space have different shapes and volumes. Several volume shapes appear and it is
not easy to develop computationally efficient modulation algorithms to find out
the tetrahedron where the reference vector is pointing to. In spite of it, some
authors have developed 3D SVPWM algorithms using abg coordinates for 3L4W
topologies [67]. But these algorithms are complex and their computational cost is
important. This is the fundamental drawback of this type of 3D SVPWM
algorithms.
88
Figure 4.20. State vectors space for two-level 3L4W conventional converters
using abc coordinates
It must be noticed that for 3L4W case, there are not redundant vectors because
the state vectors are located in different positions. The 3L4W converter state
vectors space increasing the number of levels can be done. For instance, the
three-level 3L4W converter state vectors space is shown in Figure 4.21.
89
Figure 4.21. Three-level 3L4W converter state vectors space using abc
coordinates
Increasing the number of levels of the converter, the state vectors space for an Nlevel 3L4W converter forms a cube in the 3D-space. This cube is formed by a
certain number of sub-cubes depending on the number of the levels of the
converter. Only one sub-cube for two-level converters, eight sub-cubes for threelevel converters, twenty-seven sub-cubes for four-level converters. In general,
(N-1)3 sub-cubes into the total cube, where N is the number of levels of the
multilevel converter.
Using abc coordinates, the modulation algorithm computational cost is lower
than using abg coordinates. In fact, abc coordinates divide the volume control in
cubes doing easier and faster the search for the four nearest vectors to the
reference vector. A fast and efficient generalized multilevel 3D SVPWM
algorithm was presented in [70]. It is based on a generalization of 3D SVPWM
90
(4.3)
c = integer (ucn),
The coordinates (a,b,c) are the coordinates origin corresponding to the reference
system of the sub-cube where the reference vector is pointing to. This sub-cube is
exactly equal as the two-level state vectors space case. So, the multilevel case is
reduced to a two levels case only calculating the factors a, b and c. This is shown
in Figure 4.22.
91
92
Other planes can be used to divide each sub-cube and in this thesis, new
division planes are presented. Four new planes are used to divide the sub-cube
volume and resulting tetrahedrons are shown in Figure 4.24. In this case, five
tetrahedrons compose the sub-cube volume where there is one central tetrahedron
and four external ones. Five is the minimum number of tetrahedrons to compose
the sub-cube. This fact is mathematically demonstrated in [1]. This new space
division is named SD1.
93
Figure 4.23. Sub-cube division using 45 planes (named SD45 space division).
Six tetrahedrons compose the total sub-cube volume
94
CASE 1
010
CASE 2
010
110
011
011
110
111
111
000
000
100 a
c
100 a
001
001
101
b
101
CASE 3
010
CASE 4
010
110
011
011
110
111
111
000
000
100 a
100 a
c
001
101
001
101
CASE 5
010
011
110
111
000
100 a
001
101
Figure 4.24. Sub-cube division using new planes (named SD1). Five tetrahedrons
compose the total sub-cube volume
95
Using the same notation described in [70], the flow diagram to find out the
tetrahedron where the reference vector is pointing to using SD1 is shown in
Figure 4.25. Once the tetrahedron is found, the state vectors to be used and their
duty cycles can be determined using Table I.
Normalized
reference vector:
(uan, ubn, ucn)
a = integer (uan)
b = integer (ubn)
c = integer (ucn)
ra=uan-a
rb=ubn-b
rc=ucn-c
Yes
ra+rb-rc < 0
Case 1
No
Yes
Case 3
ra+rb+rc > 2
Yes
Case 2
No
ra-rb+rc < 0
No
ra-rb-rc > 0
Yes
Case 4
No
Case 5
Figure 4.25. Flow diagram to find out the tetrahedron where the reference vector
is pointing to using space division SD1
96
More possible sub-cube divisions can be considered using SD1 but rotating
them 90 over b axis. The obtained tetrahedrons (named space division SD2) are
represented in Figure 4.26. In the same way that using previous 3D space
divisions, other flow diagram can be defined to find out the tetrahedron where
the reference vector is pointing to. The flow diagram for space division SD2 is
shown in Figure 4.27.
[ ra
rb
rc 1] = [d1
d2
d3
1
S an
2
S
d 4 ] an
3
S an
4
S an
R = Dg S
D = Rg S
1
Sbn
Sbn2
Sbn3
Sbn4
1
Scn
1
Scn2 1
Scn3 1
Scn4 1
(4.4)
-1
Using these equations, the modulation algorithm can determine the duty
cycles. The final results using SD45, SD1 and SD2 are shown in TABLE 4.I,
TABLE 4.II and TABLE 4.III respectively. These tables summarize the
switching sequences and the duty cycles for all possible locations of the
reference vector inside the two-level sub-cube.
97
CASE 6
010
CASE 7
010
110
011
110
011
111
111
000
000
c
100 a
100 a
001
001
101
b
101
b
CASE 8
010
010
110
011
110
011
111
111
000
000
c
CASE 9
100 a
100 a
001
101
001
010
011
110
111
000
c
101
CASE 10
100 a
001
101
Figure 4.26. Sub-cube division SD2. Five tetrahedrons compose the total subcube volume
98
Normalized
reference vector:
(uan, ubn, ucn)
a = integer (uan)
b = integer (u bn)
c = integer (ucn)
ra=uan-a
rb=ubn-b
rc=ucn-c
Yes
-ra+rb+rc > 1
Case 6
No
Yes
Case 8
ra+rb+rc > 2
Yes
Case 9
No
ra+rb-rc > 1
No
ra-rb-rc < 0
Yes
Case 7
No
Case 10
Figure 4.27. Flow diagram to find the tetrahedron where the reference vector is
pointing to using space division SD2
99
TABLE 4.I
SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON
THE TETRAHEDRON CASE USING SPACE DIVISION SD45
Tetrahedron
Case 1
Case 2
Case 3
Case 4
Case 5
Case 6
100
Duty cycles
d1= 1 -ra,
d2= ra - rc,
d3= -rb + rc,
d4= - rb,
d1= 1 - rb,
d2= rb - rc,
d3= - ra + rc,
d4= ra,
d1= 1 - rc,
d2= - ra + rc,
d3= ra - rb,
d4= rb,
d1= 1 - rb,
d2= - ra + rb,
d3= ra - rc,
d4= rc,
d1= 1- rc,
d2= - rb + rc,
d3= - ra + rb,
d4= ra,
d1= 1- ra,
d2= ra - rb,
d3= rb rc,
d4= rc,
TABLE 4.II
SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON
THE TETRAHEDRON CASE USING SPACE DIVISION SD1
Tetrahedron
Case 1
Case 2
Case 3
Case 4
Case 5
Duty cycles
d1= -ra-rb+rc,
d2=1-d1-d3-d4,
d3= rb,
d4= 1-rc,
d1= ra-rb-rc,
d2= 1-d1-d3-d4,
d3= rc,
d4= 1- ra,
d1= ra+rb+rc-2,
d2= 1-rc,
d3= 1-d1-d2-d4,
d4= 1-ra,
d1= -ra+rb-rc,
d2= 1-d1-d3-d4,
d3= rc,
d4= 1-rb,
101
TABLE 4.III
SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE
TETRAHEDRON CASE USING SPACE DIVISION SD2
Tetrahedron
Case 6
Case 7
Case 8
Case 9
Case 10
102
Duty cycles
d1= ra-rb+rc-1,
d2=1-d1-d3-d4,
d3= 1-ra,
d4= 1-rc,
d1= 1-ra-rb-rc,
d2= 1-d1-d3-d4,
d3= rc,
d4= ra,
d1= -1-ra+rb+rc,
d2= 1-d1-d3-d4,
d3= 1-rc,
d4= 1-rb,
d1= -1+ra+rb-rc,
d2= rc,
d3= 1-ra,
d4= 1-d1-d2-d3,
d1=0.5(-1+ra+rb+rc),
d2=0.5(1-ra+rb-rc),
d3=0.5(1-ra-rb+rc),
d4=1-d1-d2-d3,
In order to compare SD45 and SD1 space divisions, the distances between the
reference vector and the four state vectors that compose the tetrahedron where
the reference vector is pointing to can be determined. These distances are named
x1, x2, x3, and x4. In Figure 4.28, the distances xi using SD45 and SD1 are shown.
Figure 4.28. Generation of the reference voltage using the four nearest state
vectors using SD45 (a) and SD1 (b). The distances between the state vectors
and the reference vector are different
Depending on the used space division, the reference vector is generated using
different state vectors. Mathematically, the reference vector is correctly
generated using any space division but the distances xi change and consequently
the ripple of the output signals also changes. The output current ripple is related
to the value of the distances xi. If these distances decrease, it means that the
reference vector is generated with nearer state vectors and therefore the
instantaneous error due to each state vector is lower. A merit figure can be
defined in order to show xi distances in each case and what is the best solution
depending on the reference vector location. This merit figure is defined as:
103
F=
where if
1 1 1 1
+ + +
x1 x2 x3 x4
1
1
> 1000
= 1000
xi
xi
for i = 1...4
(4.5)
In order to pick out what is the best sub-cube division depending on the reference
vector location inside the two-level sub-cube, F functions for both space
divisions are calculated (FSD45 and FSD1). Finally, it is defined the function FT as
the difference of FSD1 and FSD45.
FT = FSD1 - FSD 45
(4.6)
FT can be determined for all possible locations of the reference vector in the subcube. In the control regions where FT is lower than zero, SD45 appears as the
better solution. On the other hand, in the control regions where FT is greater than
zero, SD1 improves the ripple behaviour. In Figure 4.29, FT function is
represented for several values of b coordinate in two-level sub-cube. It is clear
that inside the central tetrahedron defined by SD1, SD45 improves FT. However,
in the outer parts of this central tetrahedron, SD1 improves the FT function. So, if
the reference vector is located into the central tetrahedron, the best solution is to
use SD45 space division and if the reference vector is outside central tetrahedron,
it is better to use SD1 space division.
104
Figure 4.29. Merit figure FT for several b coordinate values between 0 and 1. If FT is
positive or negative, the distances between the reference vector and the state vectors are
smaller using SD1 or SD45 respectively
Simulations have been carried out to show the SD1 performance. The simulated
system is a four-leg four-wire three-level diode clamped converter connected to
an RL load. The DC-Link voltage is equal to 1600 V, L=5 mH, R=22 and the
switching frequency is 5 kHz. The reference is a pure sinusoidal waveform with
modulation index equal to 0.6875. Simulation results using SD45 and SD1 are
shown in Figure 4.30 and Figure 4.31 respectively. It is clear that undesired and
unexpected ripple effects in the output phase currents using SD1 appear.
105
Figure 4.30. Output phase currents using SD45 for a three-level 4L4W DCC
considering VDC=1600V, L=5mH, R=22 and the modulation index
m=0.6875. The reference voltage is a pure sinusoidal waveform and the
switching frequency is 5 kHz
Figure 4.31. Output phase currents using SD1 for a three-level 4L4W DCC
considering VDC=1600V, L=5mH, R=22 and the modulation index
m=0.6875. The reference voltage is a pure sinusoidal waveform and the
switching frequency is 5 kHz
106
Using SD1, the distortion in the output phase currents occur when the reference
vector moves from a sub-cube (sub-cube 1) to an adjacent sub-cube (sub-cube 2).
Adjacent tetrahedrons from both sub-cubes only have two common state vectors.
In the transition between adjacent tetrahedrons, there is one not common state
vector with non zero duty cycle that generates the reference vector. This is shown
in Figure 4.32. In the figure, the not common state vector between adjacent
tetrahedrons in adjacent sub-cubes is emphasized using a circle. The contribution
of this state vector to the output currents is completely different and undesired
ripple effects appear.
Figure 4.32. Transition between adjacent sub-cubes using space division SD1.
State vectors with non zero duty cycle create output current distortion
107
In order to avoid the presence of not common state vectors, adjacent sub-cubes in
the total control region are divided using SD1 and SD2 alternately. Using this
configuration in the control region, adjacent tetrahedrons from adjacent subcubes have three common state vectors and in the transition instant, the fourth
state vector has zero duty cycle. So, the movement between adjacent sub-cubes is
done avoiding the presence of state vectors with non negligible duty cycles. This
space division is named SD12 and is represented in Figure 4.33.
Figure 4.33. Adjacent sub-cubes in the total control region divided using SD1
and SD2 alternately (named SD12 space division)
Considering the combination of the SD1 and SD2 control region division, the
same simulations can be carried out. In Figure 4.34, simulation output phase
currents results using SD12 space division are shown. It can be seen that the
obtained results are very similar.
108
Figure 4.34. Output phase currents using SD12 space division generating a pure
sinusoidal reference for a three level four-leg four-wire diode clamped
converter considering VDC=1600V, L=5mH, R=22 and the modulation
index m=0.6875. The reference voltage is a pure sinusoidal waveform and the
switching frequency is 5 kHz
As the obtained phase current results are similar at first sight, total harmonic
distortion (THD) values are calculated using SD45 and SD12. THD using SD45
and SD12 space division are represented in Figure 4.35 and Figure 4.36
respectively showing that both space divisions achieve similar THD contents.
109
110
111
It can be seen that 4L4W multilevel converter state vectors space forms a
dodecahedron in the 3D-space [67][68][71]. This dodecahedron can be
decomposed into several sub-cubes, and each one can be divided in different
tetrahedrons that generate the total volume of each sub-cube. The 3Ddodecaedron containing the state vectors which generate the reference vector in
4L4W three-level converter is shown in Figure 4.38. As another example, a
4L4W five-level converter is illustrated in Figure 4.39.
Figure 4.38. Generalized 3D state vectors space for 4L4W three-level converter
112
Figure 4.39. Generalized 3D state vectors space for 4L4W five-level converter
The search for the nearest state vectors in multilevel 4L4W converters can be
solved using the same coordinates change that was proposed for 3L4W
multilevel converters and shown in Figure 4.22. Using the sub-cube coordinates,
4L4W multilevel modulation problem is reduced to a 3L4W two-level problem
[72] and the same 3L4W two-level modulation algorithms presented before can
be used. All the expressions proposed before can work equally in the 4L4W
multilevel converter topology.
3D SVPWM algorithms has been successfully tested by simulation and using a
laboratory prototype. The considered conditions are 55 W resistive load, 1.2 mH
smoothing inductance, 10 kHz switching frequency and 40V DC-Link voltage.
The algorithms have been successfully implemented using Matlab (Simulink).
The multilevel simulation results have been obtained using switching models
formulated in terms of control functions and presented in chapter 3 of this thesis.
113
The experimental results have been obtained with a real prototype using a
TMS320VC33 DSP microprocessor.
In order to test the proposed technique an unbalanced voltage reference
composed of a fundamental component with 20V amplitude, 20% of zero
sequence and 20% inverse sequence has been used. Voltage references for each
phase are represented in Figure 4.40. Voltage references of each phase are
illustrated in Figure 4.41.a, Figure 4.42.a and Figure 4.43.a. The simulation
results are shown in Figure 4.41.b, Figure 4.42.b and Figure 4.43.b and the
experimental results are shown in Figure 4.41.c, Figure 4.42.c and Figure 4.43.c.
114
115
amplitude and 120% of the third harmonic has been proved for the sake of
clarity. Voltage reference for each phase is illustrated in Figure 4.44. The voltage
reference, the simulated results and the experimental results of this experiment
are shown in Figure 4.45. Clearly, the voltage signal across the phase resistor
follows the input reference signal. These results show the good performance of
the proposed algorithm.
116
harmonic
117
Chapter 5
Solving the Balancing of the
Capacitors Voltage in
Multilevel Converters
5.1 Introduction
Multilevel converters present several advantages compared to classical two-level
converters [5][6]. They improve the harmonic content of the output signals and
they accept a power increase in the DC-link due to its voltage can be shared
between more transistors. As disadvantages, the multilevel converters increase
the control and the implementation complexity. Recently the control complexity
has been reduced thanks to the use of new and powerful microprocessor systems
[73]-[75]; hence the balance of the DC capacitors voltage is one of the most
important drawbacks of this type of converter topologies. In this chapter, control
strategies to carry out the balance the DC capacitors voltage for multilevel
118
converters are presented. These strategies use the well known technique based on
choosing the correct redundant vector using Space Vector Modulation algorithms
in order to reduce the voltage unbalance [77]-[89]. It is important to notice that
the proposed methods are completely generalized and due to it, they are
independent of the load and independent of the number of levels of the converter.
Some simulation and experimental results show the obtained balance using the
proposed techniques.
If any unbalance in the DC capacitors voltage appears, the output phase voltages
have distortion and the harmonic content of the output signals decreases its
quality. In fact, if the switching control is not be made carefully and a control
algorithm is not carried out, the problem immediately appears and the DC
capacitors voltage will be unbalanced.
119
N -2
NRV = N + 6i ( N - i )
(5.1)
i =1
120
DVCi = VCi -
VDC
N -1
(5.2)
121
On the other hand, in multilevel FCC topology, each flying capacitor voltage
value is different [26]. For instance, a four-cell conventional FCC using OFBCS
flying capacitor voltages ratio is represented in Figure 5.3 showing the flying
capacitor voltages values. For M-cell OFBCS FCC, DVCi can be defined as the
unbalance of the flying capacitor Ci as follows:
DVCi = VCi -
(M - i)
VDC
M
(5.3)
Figure 5.3. Four-cell FCC topology showing the different flying capacitors
voltage values using OFBCS flying capacitor voltages ratio
122
123
the balancing control algorithms. In this thesis it is assumed that the DC-Link
voltage is constant thanks to an external voltage source (controlled rectifier,
external independent voltage source).
As it was said before it was defined DVCi as the unbalance of capacitor Ci
determined by the difference between the real capacitor voltage and the desired
capacitor voltage (see expressions (5.2(5.3). Depending on the converter
topology, the voltage unbalance expression is different. Using the signal criteria
defined in Figure 5.4, the control strategy to achieve DC capacitors voltage
balance can be easily developed. If current iSi sign and unbalance DVCi sign are
not equal, the unbalance will decrease. So, the control algorithms should choose
the redundant vector that fulfils this property.
isi
Ci
VCi
VDC +
isj
Cj
VCj
124
these
balancing
control
algorithms
by
simulations
using
125
products of DVCi and iSi with i=1,.,N-1. In this way, the control algorithm assures
that the final chosen redundant vectors maximize, in average, the tendency to the
voltage balance of all DC capacitors. In fact, this control method really implies a
minimization of the electrical energy stored in the chain of DC capacitors [91].
The minimization of this parameter directly means the minimization of the
averaged unbalance of DC capacitors. But in general, increasing the number of
levels and considering N-level, it is not always possible to find a redundant
vector that tends to equilibrate all the DC capacitors voltage.
It is important to notice that all the necessary expressions to be applied in the
control algorithms are very simple and they can be easily implemented in a
microprocessor system being the control strategy computational cost very low.
Besides, the control method is completely generalized and due to it, it is
independent of the load type and it is independent of the number of levels of the
converter.
126
ki = N - 1 with m =
i =1
5 for 4 - wire converters
m
(5.4)
VDC = VSi
i =1
d
dt
(5.5)
m
dVS 1
= ki iSi
0 = C
dt
i =1
i =i
m
127
In N-level 3L3W DCC, each phase load is connected to some DC-Link point
applying the state vector imposed by the SVPWM algorithm. These connections
depending on the applied state vector can be represented in a very simple way
considering ideal power switching devices and assuming that all capacitors have
the same capacitance value. In N-level 3L3W DCC only two different cases must
be studied to determine iSi currents for all possible redundant state vectors.
Current iP3 is the phase current flowing through the phase connected to the
highest level, iP1 is the phase current flowing through the phase connected to the
lowest level and iP2 is the phase current flowing through the phase connected to a
medium level.
I. State vectors where k2>0, k3>0 and k4 and k1 can not be simultaneously
zero
This configuration is the generalized version of a redundant vector where the
phases of the load are connected to different points of the DC-Link. In fact, if
k1=0 and k4=0 simultaneously, the state vector is not redundant. This
configuration is shown in Figure 5.5.
128
Figure 5.5. 3L-3W DCC with case 1 configuration (k2>0, k3>0 and k4 and k1 can
not be simultaneously zero)
Analyzing this case, iSi expressions can be determined as follows.
V C 4 + V C 3 + VC 2 + V C 1 = V DC
d
dt
= - k 2 iS 2 - k 3 iS 3
C
k 4 iS 4 + k 1 iS 1
k 2 i P 2 + ( k 2 + k 3 )i P 3
N -1
( k 2 + k 3 + 1 - N )i P 3 + k 2 i P 2
iS 3 = iS - i P 3 =
N -1
( k + k 3 + 1 - N )i P 3 + ( k 2 + 1 - N )i P 2
= iS + i P 1 = 2
N -1
iS 4 = iS 1 = iS
iS =
iS 2
(5.6)
129
II. State vectors where k1 and k4 are not simultaneously equal to zero and
k3=0, k2 >0 or k2 =0, k3 >0
Figure 5.6. 3L-3W DCC with case 2 configuration (k1 and k4 are not
simultaneously equal to zero and k3=0, k2 >0 or k2 =0, k3 >0)
Analyzing this case, iSi expressions can be determined as follows.
V C 4 + V C 2 + V C 1 = V DC
k 4 iS 4 + k 1 iS 1 = - k 2 iS 2
k 2 iP 2
N -1
( k + k4 )
=- 1
iP 2
N -1
iS 4 = iS 1 = iS
iS =
iS 2 = iS - i P 2
130
(5.7)
All the redundant state vectors can be studied changing the values of ki factors
and recalculating iSi values. After determining the currents through the DC-link
capacitors associated to each redundant state vector, the balancing control
algorithm must choose carefully the best redundant state vector in order to
equilibrate the DC-link capacitors voltage.
VDC = VC1 + VC 2 + VC 3 + VC 4 + VC 5
d
dt
dV
dV
dV
dV
dV
0 = C C1 + C C 2 + C C 3 + C C 4 + C C 5
dt
dt
dt
dt
dt
0 = k1iS1 + k 2iS 2 + k3iS 3 + k4iS 4 + k5iS 5
C
(5.8)
In order to generalize the study and to know the way to choose the best redundant
vector to carry out the balance of the DC-link voltage, all the possibilities are
studied. Several possible switching configurations appear depending on the
position of the connection of the fourth leg. All the cases can be summarized in
131
Figure 5.7 (case 1), Figure 5.8 (case 2), Figure 5.9 (case 3) and Figure 5.10 (case
4). As it was said for 3L3W DCC case, current iP3 is the phase current flowing
through the phase connected to the highest level, iP1 is the phase current flowing
through the phase connected to the lowest level and iP2 is the phase current
flowing through the phase connected to a medium level. Besides, iN is the current
that flows through the phase connected to neutral point of the load (the fourth
leg).
132
133
134
135
136
All the cases can be easily solved and iSi results can be summarized as follows.
Case 1:
1
[k2iP1 + (k2 + k3 )iP2 + (k2 + k3 + k4 )iP3 ]
N -1
1
iS 2 = [( N -1- k2 )iP1 + (k1 + k4 + k5 )iP2 + (k1 + k5 )iP3 ]
N -1
1
iS 3 =
[k2i 1 - (k1 + k4 + k5 )iP2 - (k1 + k5 )iP3 ]
N -1 P
1
iS 4 =
[k2iP1 + (k2 + k3 )iP2 - (k1 + k5 )iP3 ]
N -1
iS1 =
Case 2:
1
[-k2iP1 + k3iP2 + (k3 + k4 )iP3 ]
N -1
1
iS 2 =
[( N -1- k2 )iP1 + k3iP2 + (k3 + k4 )iP3 ]
N -1
1
iS 3 = [k i + (N -1- k3 )iP 2 + (k1 + k2 + k5 )iP3 ]
N -1 2 P1
1
iS 4 =
[-k2iP1 + k3iP2 - (k1 + k2 + k5 )iP3 ]
N -1
iS1 =
Case 3:
(5.9)
1
[-(k2 + k3 )iP1 - k3iP2 + k4iP3 ]
N -1
1
iS 2 =
[(k1 + k4 + k5 )iP1 - k3iP2 + k4iP3 ]
N -1
1
iS 3 =
[(k + k + k )i + ( N -1- k3 )iP2 + k4iP3 ]
N -1 1 4 5 P1
1
iS 4 = [(k2 + k3 )iP1 + k3iP2 + ( N -1- k4 )iP3 ]
N -1
iS1 =
Case 4:
1
[(k2 + k3 + k4 )iP1 + (k3 + k4 )iP2 + k4iP3 ]
N -1
1
iS 2 =
[(k1 + k5 )iP1 - (k3 + k4 )iP2 - k4iP3 ]
N -1
1
iS 3 =
[(k + k )i + (k1 + k2 + k5 )iP2 - k4iP3 ]
N -1 1 5 P1
1
iS 4 =
[(k1 + k5 )iP1 + (k1 + k2 + k5 )iP2 + ( N -1- k4 )iP3 ]
N -1
iS1 = -
137
It can be studied, for instance, the three-level case. In this case, several double
and triple redundant state vectors appear. These redundant state vectors can be
summarized in TABLE 5.I. All the possible redundant vectors can be classified
in the four cases explained before.
Using the expressions proposed in TABLE 5.I, iSi currents can be easily
calculated depending on the selected redundant state vector. In the three-level
case, there are only two DC-Link capacitors; hence iS1 and iS2 can be determined.
It can be remembered that using the expression (5.8) it must be fulfilled the
expression iS2 =-iS1. As it was presented in (5.2), DVCi in the three-level case is:
DVCi = VCi -
VDC
2
(5.10)
Considering three-level 4L4W DCC, in all the possible cases, the current through
capacitor C1 (iS1) in the redundant state vectors has opposite signs. This result is
very important because in three-level case, the control algorithm can always
select the sense of currents flowing through DC-link capacitors C1 and C2
choosing the redundant vector that tends to equilibrate the DC-link voltage.
138
State vector
000|0
Redundant vectors
111|1
222|2
Case
000|1
111|2
001|0
112|1
010|0
121|1
100|0
211|1
001|1
112|2
010|1
121|2
100|1
211|2
011|0
122|1
101|0
212|1
110|0
221|1
011|1
122|2
101|1
212|2
110|1
221|2
111|0
222|1
TABLE 5.I. Each redundant vector in 4L4W DCC can be studied using one of
the four simplified cases presented in Figure 5.7, Figure 5.8, Figure 5.9 and
Figure 5.10
139
Figure 5.11. DC-Link Capacitor C1 voltage and output phase currents showing
the good performance of the balancing control algorithm for three-level
4L4W DCC
140
In order to show the good performance of the control algorithm, some simulation
results with higher number of levels are shown. It can be considered the same
experiment described in the three-level case (see Figure 5.11) but using a fivelevel converter and assuming that the modulation index is equal to 0.56. An
initial unbalance in the DC-link capacitors voltages is applied to show the
unbalance dynamics using the control algorithm. Therefore the simulation
experiment has been carried out considering five-level 4L4W DCC topology
connected to an RL load composed by R=22, L=5mH, fsw (switching
frequency)=5 kHz, C1=C2=500 F and VDC (DC-Link voltage)=1600V. The
reference waveform is a sinusoidal signal with modulation index m=0.56 and
80% third harmonic. Using five-level DCC four capacitors compose the DC-link
and their desired voltages are VDC/4 that is 400 volts in this case. In this
simulation, initially, VC1=470v, VC2=360v, VC3=370v and VC4=400v. In Figure
5.12 simulation results of the DC-link voltages are represented.
Figure 5.12. DC-link Capacitors voltage showing the good performance of the
balancing control algorithm starting with a initial unbalance using a five-level
4L4W DCC
141
142
Several experiments were carried out to test the converter and the 4L4W DCC
balancing control algorithm. All the expressions presented before can be applied
directly only doing the factor N (number of levels of the converter) equal to 3. In
the experiments, the converter is connected to a three-phase RL load where
R=23.5 and L=1.4mH. The total DC-Link voltage is 80 volts. It is assumed a
sinusoidal reference voltage where the modulation index was equal to 1 and an
80% of third harmonic content. In Figure 5.14, phase to phase voltage and the
voltage across the resistor (phase to neutral of the load voltage) is shown
demonstrating that the 3D-SVPWM algorithm presented in [72] is carried out
properly.
But this figure does not include the DC-Link capacitors voltages measure. If this
experiment is carried out without using the balancing control algorithm, the DCLink capacitors voltages turn unstable because the 3D-SVPWM algorithm does
not consider any special choosing between the redundant vectors in the switching
sequence. This voltage unbalance is shown in Figure 5.15. A detail of this
experiment is shown in Figure 5.16. The modulation is carried out correctly
generating the reference signal but DC-Link capacitors voltages begin to be
unbalanced immediately after starting the execution of the modulation algorithm.
Figure 5.15 and Figure 5.16 clearly show the need to include a balancing control
algorithm in the modulation algorithm.
If the proposed balancing algorithm is used, the DC-Link capacitor voltages will
be balanced while the reference voltage is still be correctly generated. The good
performance includes situations where the DC-Link capacitors voltages are
initially unbalanced. In Figure 5.17, it can be seen that an initial unbalance is
applied to the converter and the modulation algorithm and the balancing control
algorithm begin to be executed. The output voltages are generated while the
voltages unbalance quickly begins to decrease. It can be seen that some distortion
143
appears in the initial output voltages due to the voltages unbalance present in the
converter. The balancing control algorithm continues working all the time
achieving the balance of DC-Link capacitors voltages. It is shown in Figure 5.18
and Figure 5.19. After balancing the DC-Link voltages, the initial distortion in the
output voltages have disappeared demonstrating that it is created by the DC-Link
capacitors unbalance. It is shown in Figure 5.20.
The balancing control algorithm does not suppose any restriction in the load. In
fact, it works with balance or unbalance loads because it is absolutely independent
of the load. In order to test it, it was carried out the same experiment but using an
unbalanced load using L=1.4mH and R=23.5 in two phases and L=1.4mH and
R=47 in the third phase. The experimental results were completely satisfactory
achieving the voltages balance and generating the reference waveforms.
144
145
146
147
One of the most important contributions of this thesis is the proposal of this
control algorithm. In fact, it is the first control algorithm to balance the DC-link
capacitor voltages for 4L4W DCC. All possible redundant vectors are deeply
studied showing all possible simplified converter models. The analytical
expressions to determine the currents flowing through DC-link capacitors are
presented. The balancing control algorithm uses these equations and finds the
best redundant state vectors in order to minimize the voltage unbalance in
average. It is important to note that the algorithm computational cost is really low
and it is independent of the load type and independent of the number of levels of
the converter. A 50KW real prototype of a 4L4W-DCC was built and
experimental results showing the good performance of the proposed algorithm
are presented.
In 3L4W topologies, the neutral point of the load is connected to the middle point
of the DC-Link bus. Simplified models for 3L4W topologies can be developed
considering that a state vector is applied to the converter. In this way, each phase
load is connected to a point of the DC-Link and the fourth wire is connected to
the middle point of the DC-Link bus. All simplified models for 4L4W DCC can
be used imposing that the neutral wire is connected to the middle point of DCLink bus. So, for instance, Figure 5.7 can represent a N-level 3L4W DCC with k1
148
equal to (N-1)/2. In the same way, Figure 5.8, Figure 5.9 and Figure 5.10 are
valid with k1 + k2, k1 + k2+ k3 and k1 + k2+ k3+ k4 equal to (N-1)/2 respectively.
Therefore, the study of this topology is a particularization of the study of 4L4W
DCC topology and the DC capacitor currents equations for 3L4W DCC topology
are exactly the same as 3L4W DCC topology but applying the fourth wire
restriction.
N -1
2
N -1
Case 2 : k1 + k2 = k3 + k4 + k5 =
2
N -1
Case 3 : k1 + k2 + k3 = k4 + k5 =
2
N -1
Case 4 : k1 + k2 + k3 + k4 = k5 =
2
Case 1: k1 = k2 + k3 + k4 + k5 =
(5.11)
However, using 3L4W topologies redundant vectors do not appear due to the fact
that the fourth wire can not change its connection point. So, the control algorithm
can not choose the redundant vector to minimize the voltages unbalance. The
SVPWM algorithm directly applies the state vectors and there is not any
possibility to change them.
149
In a single phase M-cell FCC there are only 2M different switching configurations
depending on binary Sxi values and therefore all possible converter switching
configurations can be defined using M bits. An easy way to calculate output
phase voltages with respect to the middle point of the DC-link labelled as point 0
(Vx0) using each single cell binary value (Sxi) is the following:
Vx0 =
150
(S
i =1
xi
S x ( i +1) - S xi S x ( i +1) )V xi + ( S x 1 - S x 1 )
VDC
2
(5.12)
Considering OFBCS voltage ratio the number of output voltage levels is the
number of basic cells plus one. It can be defined phase x state (PSx) as an integer
value that shows the output voltage level in phase x. PSx equal to zero means that
the minimum possible voltage is in the phase output. For N-level OFBCS FCC,
the output phase voltage Vx0 and the factor PSx can be easily determined by
N -1
PS x = S xi
(5.13)
i =1
Vx 0 =
VDC
V
PS x - DC
N -1
2
In the three-level case, the obtained OFBCS FCC is shown in Figure 5.22.
Studying this case, the possible switching configurations are shown in TABLE
5.II. It can be seen that in the three level FCC, two different switching
configurations obtain the same output phase voltage referred to 0.
151
SX1
SX2
Phasex-0 voltage
Phasex State
ON
ON
VDC/2
ON
OFF
OFF
ON
OFF
OFF
-VDC/2
Redundant
switching
configurations
( N - 1)!
k !( N - 1 - k )!
(5.14)
The proposed balancing control algorithm for OFBCS FCC is based on the
existence of redundant switching configurations. Considering other voltage ratios
presented in [28], this property does not appear and there is not any redundant
switching configuration to obtain the same output voltage in the FCC. So, if
some of these voltage ratios are chosen, the balancing control algorithm will be
less efficient in order to solve the balancing voltage problem. So, the proposed
balancing control algorithm assumes that OFBCS voltage ratio is used.
152
Figure 5.23. Switching configurations redundancy for each OFBCS FCC phase
state depending on the number of levels
153
The SVPWM algorithm determines the switching sequence that must be applied
to the converter. The balancing control algorithm studies these state vectors and
applies the redundancy properties to minimize and compensate the voltage errors
in the floating capacitors. The control algorithm studies all the state vectors of
the switching sequence one by one following the flow diagram shown in Figure
5.24. Each redundant state vector in the switching sequence is studied
considering each phase separately because each phase state can be achieved by
several redundant switching configurations. The balancing control algorithm
considers each possibility and finally, chooses the best switching configuration to
balance the flying capacitors voltage minimizing the sum of the products of the
currents that flow through to the flying capacitors and their unbalances. This sum
is defined as G and it is related with the energy in the system [91].
154
M -1
G = iSxi DVxi
(5.15)
i =1
At this point, the balancing control algorithm knows the best switching
configuration in each phase of the converter supposing an specific state vector.
So, the control algorithm must repeat this step using all possible redundant state
vectors.
Figure 5.24. Balancing control algorithm flow diagram. Each state vector in the
switching sequence is studied applying the best redundant state vector
Finally, the balancing control algorithm chooses the best redundant state vector
with the best switching configuration. So, the final election determines the state
vector in the converter and the switching configuration in each phase of the
converter that minimizes G factor.
155
Vx1 =
VDC
+ D x1 , with x = a, b, c
2
(5.16)
(5.17)
At this point, the control algorithm knows the best switching configuration in
phase a assuming phase a state equal to 1. In the same way, the control
algorithm can determine the best switching configuration in phase b supposing
the phase state equal to 0 and in phase c supposing the phase state equal to 1.
It can be noticed that phase state equal to 0 has not switching redundancy and
there is only one possible switching configuration to obtain that phase state.
156
(5.18)
(5.19)
157
158
159
Figure 5.28. DC-link capacitor voltages controllability limits for N-level 3L3W
DCC depending on the modulation index and the phase angle
160
161
Figure 5.30. DC-link Capacitors voltage limits for 4L4W multilevel converters
Anyway, these controllability limits only show the control region using the
redundant vectors in SVPWM techniques. External control loops can be applied
trying to make bigger the region under control [96] and control for back-to-back
converters can be studied [97][98]. Besides, other optimization algorithms can be
162
163
Chapter 6
Contributions and General
Conclusions
This work is focused on the study of multilevel converters. First of all, an
overview of the most typical converter topologies has been presented. The way
of switching depending on the multilevel converter topology is shown. Finally, a
new multilevel FCC topology is presented changing the flying capacitor voltages
ratio achieving an output voltage range increase and an improvement in the
output waveforms quality thanks to an increase of the number of output levels in
the converter. Besides, possible drawbacks for the proposed topology are shown.
In chapter 3, several analytical models for different multilevel converter
topologies are developed. These mathematical models are based on the use of
switching functions and the determination of state equations for the phase
currents and the DC capacitor voltages. Several models are explained in detail
and a systematic method to develop new ones for future multilevel converters is
shown. Simulation results presented in next chapters use analytical models
presented in this one.
164
165
166
will be the most powerful tool to reach greater results and to continue making
progress.
Finally, the list of publications derived from this thesis work is shown in chapter
8.
167
Chapter 7
Further Works
As future works, other new multilevel converter topologies can be studied. New
MatLab/Simulink models can be developed and finally a complete comparison
between all topologies can be done. Firstly, more real models can be developed
taking into account real power devices substituting ideal switches. On the other
hand, mathematical models for NFBCS-FCC and NEFBCS-FCC can be
developed. Moreover, N-level OFBCS-FCC and N-level cascade converter
expressions can be determined. Besides, new mathematical models for multilevel
converters connected to other loads as non linear loads and electrical machines
can be done.
Once analytical models are determined, new SVPWM techniques can be
presented. The first step is to calculate the state vectors space for new multilevel
converter topologies (as NFBCS-FCC and NEFBCS-FCC) and the next step is to
develop new 2D and 3D SVPWM strategies.
One future work related to this thesis is to build 5-level 4L4W DCC and a
generalized 3-level 4L4W FCC to carry out experiments to demonstrate all
168
169
Chapter 8
Publications Derived from
the Thesis Work
The following publications in transactions, journals and conferences have been
derived from the thesis work.
Publication Title
International Magazine
[104]
[101]
170
[70]
[100]
International Conferences
Publication Title
International Conference
The 29th Annual Conference
of the IEEE Industrial
Electronics Society, 2003.
IECON '03.
30th Annual Conference of
IEEE Industrial Electronics
Society, 2004. IECON 2004.
I Seminario Anual de
Automtica, Electrnica
Industrial e Instrumentacin,
SAAEI 2005
31th Annual Conference of
IEEE Industrial Electronics
Society, 2005. IECON 2005.
12th International Power
Electronics and Motion
Control (EPE-PEMC06)
Power Electronics/Intelligent
Motion/Power Quality
(PCIM06)
13th IEEE Mediterranean
Electrotechnical Conference
(MELECON06)
Reference
Code
[105]
[72]
[103]
[102]
[107 ]
[108 ]
[109 ]
[110 ]
171
Chapter 9
References
[1] Maria de los ngeles Martn Prats, thesis dissertation: Nuevas Tcnicas de
modulacin vectorial para convertidores electrnicos de potencia
multinivel, Electronic Engineering Department, University of Seville (Spain)
2003.
[2] Three dimensional space vector modulation for four-leg inverters using
natural coordinates; Perales, M.A.; Prats, M.M.; Portillo, R.; Mora, J.L.;
Franquelo, L.G.; Industrial Electronics, 2004 IEEE International Symposium
on, Volume 2, 4-7 May 2004 Page(s):1129 - 1134 vol. 2
[3] Modeling of a three level converter used in a synchronous rectifier
application; Escobar, G.; Leyva-Ramos, J.; Carrasco, J.M.; Galvan, E.;
Portillo, R.C.; Prats, M.M.; Franquelo, L.G.; Power Electronics Specialists
Conference, 2004. PESC 04. 2004 IEEE 35th Annual, Volume 6, 20-25 June
2004 Page(s):4306 - 4311 Vol.6
[4] Control of a three level converter used as a synchronous rectifier;
Escobar, G.; Leyva-Ramos, J.; Carrasco, J.M.; Galvan, E.; Portillo, R.C.;
Prats, M.M.; Franqueto, L.G.; Power Electronics Specialists Conference,
2004. PESC 04. 2004 IEEE 35th Annual, Volume 5, 20-25 June 2004
Page(s):3458 - 3464 Vol.5
[5] R. Teodorescu, F. Blaabjerg, J.K Pedersen, E. Cengelci, S.U. Sulistijo,
B.O.Woo, and P. Enjeti. Multilevel converters-a survey. European
Conference on Power Electronics and Applications, 1999.
[6] J.S Lai and F.Z. Peng. Multilevel converters-a new breed of power
converters. IEEE Transactions on Industry Applications, vol. 32:509517,
1996.
[7] Active Harmonic Elimination for Multilevel Converters; Du, Z.; Tolbert,
L.M.; Chiasson, J.N.; Power Electronics, IEEE Transactions on
Volume 21, Issue 2, March 2006 Page(s):459 469.
[8] Low switching frequency active harmonic elimination in multilevel
converters with unequal DC voltages; Zhong Du; Tolbert, L.M.; Chiasson,
J.N.; Hui Li; Industry Applications Conference, 2005. Fourtieth IAS Annual
Meeting. Conference Record of the 2005, Volume 1, 2-6 Oct. 2005
Page(s):92 - 98 Vol. 1.
172
173
[32] Modeling of multilevel converters; Meynard, T.A.; Fadel, M.; Aouda, N.;
Industrial Electronics, IEEE Transactions on, Volume 44, Issue 3, June
1997 Page(s):356 364.
[33] Modeling, analysis and control of cascaded-multilevel converter-based
STATCOM; Sirisukprasert, S.; Huang, A.Q.; Lai, J.-S.; Power Engineering
Society General Meeting, 2003, IEEE, Volume 4, 13-17 July 2003.
[34] Dynamic Model and Control of the NPC-Based Back-to-Back HVDC
System; Yazdani, A.; Iravani, R.; Power Delivery, IEEE Transactions on,
Volume 21, Issue 1, Jan. 2006 Page(s):414 424.
[35] Modeling and simulation of the linear generator PWM multilevel inverter;
Rahim, N.A.; Mahrous, E.A.; Hew, W.P.; Nor, K.M.; Power Engineering
Conference, 2003. PECon 2003. Proceedings. National 15-16 Dec. 2003
Page(s):95 98.
[36] Modeling of multilevel voltage source converter; Deshpande, N.R.; Sasi, N.;
Sawant, R.R.; Power Electronics Systems and Applications, 2004.
Proceedings. 2004 First International Conference on, 9-11 Nov. 2004
Page(s):24 29.
[37] P. M. Bhagwat and V. R. Stefanovic, Generalized structure of a multilevel
PWM inverter, IEEE Trans. Ind. Applicat., vol. IA-19, pp. 10571069,
Nov./Dec. 1983.
[38] Pulsewidth modulation-a survey; Holtz, J.; Industrial Electronics, IEEE
Transactions on, Volume 39, Issue 5, Oct. 1992 Page(s):410 - 420.
[39] L.M Tolbert and T.G. Habetler; Novel multilevel inverter carrier-based
PWM method. IEEE Transactions on Industry Applications, vol. 35:1098
1107, 1999.
[40] Multicarrier PWM strategies for multilevel inverters; McGrath, B.P.;
Holmes, D.G.; Industrial Electronics, IEEE Transactions on, Volume 49,
Issue 4, Aug. 2002 Page(s):858 867.
[41] An analytical technique for the determination of spectral components of
multilevel carrier-based PWM methods; McGrath, B.P.; Holmes, D.G.;
Industrial Electronics, IEEE Transactions on, Volume 49, Issue 4, Aug.
2002 Page(s):847 857.
[42] Comparisons of PWM and one-cycle control for power amplifier with
multilevel converter Chan, C.C.; Zheng Ming Zhao; Qian, C.; Meng, S.;
Industrial Electronics, IEEE Transactions on, Volume 49, Issue 6, Dec.
2002 Page(s):1342 1344.
[43] Modulation techniques comparison for three levels VSI converters; Bueno,
E.J.; Garcia, R.; Marron, M.; Urena, J.; Espinosa, F.; IECON 02 [Industrial
Electronics Society, IEEE 2002 28th Annual Conference of the], Volume 2,
5-8 Nov. 2002 Page(s):908 - 913 vol.2.
[44] Comparative evaluation of modulation algorithms for neutral-point-clamped
converters; Bendre, A.; Krstic, S.; Vander Meer, J.; Venkataramanan, G.;
175
Industry Applications, IEEE Transactions on, Volume 41, Issue 2, MarchApril 2005 Page(s):634 - 643.
[45] Reciprocity-transposition-based sinusoidal pulsewidth modulation for diodeclamped multilevel converters; Venkataramanan, G.; Bendre, A.; Industrial
Electronics, IEEE Transactions on, Volume 49, Issue 5, Oct. 2002
Page(s):1035 1047.
[46] A discontinuous carrier-based multilevel modulation for multilevel
converters; Cecati, C.; Dell'Aquila, A.; Lecci, A.; Liserre, M.; Monopoli,
V.G.; Industrial Electronics Society, 2004. IECON 2004. 30th Annual
Conference of IEEE, Volume 1, 2-6 Nov. 2004 Page(s):280 - 285 Vol. 1.
[47] A 3-D generalized direct PWM algorithm for multilevel converters; Ning-Yi
Dai; Man-Chung Wong; Yuan-Hua Chen; Ying-Duo Han; Power
Electronics Letters, IEEE, Volume 3, Issue 3, Sept. 2005 Page(s):85 88.
[48] Computed PWM for flying capacitor multicell converters; Delmas, L.;
Meynard, T.A.; Gateau, G.; Industrial Electronics, 2004 IEEE International
Symposium on, Volume 2, 4-7 May 2004 Page(s):953 - 956 vol. 2.
[49] Reduced Switching Frequency Computed PWM Method for Multilevel
Converter Control; Du, Z.; Tolbert, L.M.; Chiasson, J.N.; Power Electronics
Specialists, 2005 IEEE 36th Conference on, June 12, 2005 Page(s):2560
2564.
[50] A discontinuous carrier-based multilevel modulation for multilevel
converters; Cecati, C.; Dell'Aquila, A.; Lecci, A.; Liserre, M.; Monopoli,
V.G.; Industrial Electronics Society, 2004. IECON 2004. 30th Annual
Conference of IEEE, Volume 1, 2-6 Nov. 2004 Page(s):280 - 285 Vol. 1.
[51] Novel modulation techniques for DC-side commutated inverters; Bornhardt,
K.E.; Power Electronics and Variable-Speed Drives, 1991., Fourth
International Conference on 17-19 Jul 1990 Page(s):92 - 97.
[52] Optimized space vector switching sequences for multilevel inverters;
McGrath, B.P.; Holmes, D.G.; Lipo, T.; Power Electronics, IEEE
Transactions on, Volume 18, Issue 6, Nov. 2003 Page(s):1293 - 1301.
[53] M. Cosan, H. Mao, D. Borojevic, and F. C. Lee, Space vector modulation
of three-level voltage source inverter, Proc. VPEC Seminar, pp. 123128,
1996.
[54] H. L. Liu and G. H. Cho, Three-level space vector PWM in low index
modulation region avoiding narrow pulse problem, IEEE Trans. Power
Electron., vol. 9, pp. 481486, Sept. 1994.
[55] B. Kaku, I. Miyashita, and S. Sone, Switching loss minimized space vector
PWM method for IGBT three-level inverter, Proc. IEEElect. Power
Applicat., vol. 144, no. 3, pp. 182190, May 1997.
[56] N. Celanovic and D. Boroyevich, A comprehensive study of neutralpoint
voltage balancing problem in three level neutral-point-clamped voltage
176
source PWM inverters, IEEE Trans. Power Electron., vol. 15, pp. 242
249, Mar. 2000.
[57] H.T. Mouton. Natural balancing of three-level neutral-point-clamped PWM
inverters. IEEE Transactions on Industrial Electronics, vol. 49:10171025,
2002.
[58] M. Cosan, H. Mao, D. Borojevic, and F. C. Lee, Space vector modulation
of three-level voltage source inverter, Proc. VPEC Seminar, pp. 123128,
1996.
[59] J. H. Seo, C. H. Choi, and D. S. Hyun, A new simplified space-vector
PWM method for three-level inverter, IEEE Trans. Power Electron., vol.
16, no. 4, pp. 545550, Jul. 2001.
[60] Y. Liu, X. Wu, and L. Huang, Implementation of three-level inverter using
a novel space vector modulation algorithm, in IEEE PowerCon2002, vol.
1, 2002, pp. 606610.
[61] A. R. Bakhshai, H. R. S. Rad, and G. joos, Space vector modulation based
on classification method in three-phase multi-level voltage source
inverters, in IEEE IAS Annu. Meeting, vol. 1, 2001, pp. 597602.
[62] Q. Song, W. Liu, G. Yan, and Y. Chen, DSP-based universal space vector
modulator for multi-level voltage-source inverters, in Proc. IEEE IECON
2003, vol. 2, 2003, pp. 17271732.
[63] Dengming Peng, F.C. Lee, and D. Boroyevich. A novel svm algorithm for
multilevel three-phase converters. Power Electronics Specialists
Conference, 2.
[64] Effective algorithm for multilevel converters with very low computational
cost; Prats, M.M.; Carrasco, J.M.; Franquelo, L.G.; Electronics Letters,
Volume 38, Issue 22, 24 Oct 2002 Page(s):1398 - 1400.
[65] J.O Krah and J. Holtz. High-performance current regulation and efficient
PWM implementation for low-inductance servo motors. IEEE Transactions
on Industry.
[66] New fast space-vector modulation for multilevel converters based on
geometrical considerations; Prats, M.M.; Portillo, R.; Carrasco, J.M.;
Franquelo, L.G.; IECON 02 [Industrial Electronics Society, IEEE 2002 28th
Annual Conference of the] Volume 4, 5-8 Nov. 2002 Page(s):3134 - 3139
vol.4.
[67] R. Zhang, V. H. Prasad, D. Boroyevich, and F. C. Lee, Three-dimensional
space vector modulation for four-leg voltage-source converters, IEEE
Trans. Power Electron., vol. 17, no. 3, pp. 314326, May 2002..
[68] C. Liu, D. Peng, and R. Zhang, Four-legged converter 3-D SVM scheme
over-modulation study, in Proc. IEEE APEC 2000, vol. 1, 2000, pp. 562
568.
177
178
179
181
Chapter 10
Acknowledgments
I would like to show all my gratitude to all the people that helped me in these years. Firstly
thanks to Dr. Juan Manuel Carrasco Sols because he gave me the opportunity to work in this
department. Thank you for your constant support and for your confidence. Thank you for
helping me to go to USA and Norway to improve my formation.
Thanks to Prof. Leopoldo Garca Franquelo for helping me in all the researching process. It was
a great pleasure for me to be your PhD student. Thanks for motivating me to continue working.
Of course, thanks to all my work mates. Specially thanks to Ramn Portillo. Thanks to Eugenio
Domnguez, Sergio Vzquez, Juan Jos Arcos, Juan A. Snchez, Mara de los ngeles Prats
and Eduardo Galvn. Thanks to all the people in DINEL Department. Thank you Jon Tombs,
Carmen Aracil, Miguel Aguirre, Federico Barrero, Manuel Perales, Jos Luis Mora
In the international chapter, I would like to thank hugely to Prof. Alex Stankovic. He received
me in Norhteastern University in 2004 and he helped me a lot. Thanks to Milun Perii, Hugo
Rodrguez, Rosario and Sergio Ceballos. I was really lucky for meeting them of you in Boston.
In 2005 I was in NTNU in Trondheim (Norway). I would like to thank to Prof. Tore Undeland
for receiving me. Thanks to Giuseppe Guidi, Marta Molinas, Sofia Guidi, William Gulvik,
Arkadiuz Kulka and all the people in ENO group.
Of course, thanks to my parents and family. Thank you for believing in me.
Finally, I would like to thank Marta all her patience and support.
182