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HT9580
Character Pager Controller
Features
General Description
therefore provides excellent decoder sensitivity. The controller contains a full function
pager decoder at a 512, 1200, 2400 bps data
rates. Using an M6502 core takes advantage of
a flexible external control interface, LCD driver
chips and abundant programming resources
from worldwide providers. The internal SPI
would communicate with SPI of FLEXTM high
speed pager decoder.
The HT9580 is a high performance pager controller which can be used for Chinese Pager
system applications. The HT9580 4-in-1 Character Pager Controller combines a POCSAG decoder with a M6502 microprocessor core, 2
Mbits Character ROM and 256 Kbits SRAM to
provide both high decoder performance and excellent system flexibility. The decoder utilizes a
2-bit random error correction algorithm and
FLEX
TM
Preliminary
HT9580
Block Diagram
R e g is te r S e c tio n
C o n tr o l S e c tio n
R E S IR Q
N M I
L o g ic
In d e x
R e g is te r
Y
A 1
A 2
A 4
A B L
S Y N C
A 8
A c c u m u la to r
A
In te rn a l A D L
A 9
A 1 0
A B H
M L
T im in g
C o n tro l
S p e c ia l B u s
A 7
A 1 2
R D Y
In s tr u c tio n
D e c o d e r
A L U
In te rn a l A D L
A 6
C lo c k
G e n e ra to r/
O s c illa to r
P C L
P ro c e s s o r
S ta tu s
R e g is te r P
P C H
In p u t D a ta
L a tc h
(D L )
A 1 3
D a ta B u s
B u ffe r
P H I2 (IN )
O S C 1
P H I1 (O U T )
P H I2 (O U T )
S O
R /W
B E
A 1 4
A 1 5
IR Q
V P
S ta c k P o in t
R e g is te r ( s )
A 5
A 1 1
N M I
In d e x
R e g is te r
X
A 0
A 3
In te rru p t
L o g ic
R E S E T
O S C 2
In te rru p t
L o g ic
D 0
L e g e n d
D 1
D 2
= 8 B it L in e
D 3
D 4
= 1 B it L in e
D 5
D 6
D 7
M 6 5 0 2 C o re
P ro g ra m
R O M
A d d re s s
D e c o d e r
6
T M R 0 ( 8 b it)
S R A M
X 1
S y s te m
C lo c k
T M R 1 ( 1 6 b it)
L C D _ E
C h a ra c te r
R O M
L C D _ R W
L C D _ C S 0
L C D _ C S 1
L C D
D r iv e r
In te rfa c e
L C D _ C L
W D T
L C D _ A 0
M U X
P _ M O D E
X 1
S y s te m
C lo c k
T M R 1
P A C
P A
P A 0 ~ P A 5
P B C
P B
P B 0 ~ P B 7
P C C
P C
T o n e G e n e ra to r
P C 0 ~ P C 1
D u ty C y c le C o n tr o l
B Z
R T C
R S S I
D ig ita l
F ilte r
B A F
D A _ O U T
P r e - s c a le r
M U X
M U X
R A 1
R A 1
R A 1
R A 1
8 - b it
D /A
D A 7
D A 6
D A 5
D A 4
D A 3
D A 2
D A 1
D A 0
D a ta P h a s e
R e c o v e ry
B C H C o d e
D e c o d e r
S ta tu s
C o n tr o lle r
P O C S A G
R F P o w e r
C o n tr o lle r
U s e r A d d re s s
a n d
C o n fig u r a tio n
M e m o ry
D e c o d e r
D a ta
O u tp u t
C o n tro l
S P I
C ir c u it
B S 1 /S S
B S 2 /S C K
B S 3 /M O S I
D I/M IS O
B A L /S R D Y
S P I C o n tro l
X 1
X 2
D e c o d e r
Preliminary
HT9580
Pin Assignment
R S S I
D I/M IS O
B S 3 /M O S I
B S 2 /S C K
B S 1 /S S
T S
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
R E S E T
T S C
T S 1
O S C 2
O S C 1
V S S
X 2
X 1
V D D
L C D _ C S 1
L C D _ C S 0
L C D _ C L
L C D _ A 0
L C D _ R W
L C D _ E
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
R /W
S R A M _ C E
M A S K _ C E
O E
P S E N
8 0
6 1
6 0
H T 9 5 8 0
8 0 L Q F P
4 1
4 0
2 0
2 1
D A
B A
S R
V S
V D
B Z
P C
P C
P B
P B
P B
P B
P B
P B
P B
P B
T M
A 0
A 1
A 2
_ O U T
F
D Y /B A L
S
D
1
0
7
6
5
4
3
2
0
1
R 1
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
A 1 5
V S S
P _ M
V D D
R A 1
R A 1
R A 1
R A 1
4
7
O D E
Preliminary
HT9580
Pin Description
Pin No.
Pin Name
I/O
Description
1, 25, 56
VDD
LCD_CS1
LCD_CS0
LCD_CL
LCD_A0
LCD_RW
LCD_E
15~8
D0~D7
I/O
16
R/W
17
SRAM_CE
18
MASK_CE
19
OE
20
PSEN
21~24
RA17~RA14
Internal or external program ROM selection without pull-high resistor. If the pin connects to VDD, the internal program ROM will
be fetched (normal type), otherwise the external program ROM
will be fetched when the pin connects to VSS (Romless).
43~28
A0~A15
Address bus pins. This is used for memory and I/O exchanges on
the data bus.
44
TMR1
26
P_MODE
45~52
PB0~PB7
I/O
General Input/Output Port B. The input cell structures can be selected as CMOS or CMOS with pull-high resistors.
53~54
PC0~PC1
I/O
General Input/Output Port C. The input cell structures can be selected as CMOS or CMOS with pull-high resistors.
55
BZ
Preliminary
Pin No.
Pin Name
BAL
I/O
HT9580
Description
SRDY
SPI slave ready This slave ready pin is a Schmitt trigger input
with pull-high resistor. When the slave initiates the SPI transfer,
a high to low transition activates an interrupt. When the master
initiates the SPI transfer, a high to low transition trigger the
master to start the transfer.
59
BAF
60
DA_OUT
RSSI
RSSI output from IF circuit. This pin should be pulled high or low
externally when this pin is not used.
DI
POCSAG code input serial data. CMOS input with pull-high resistor.
MISO
BS3
MOSI
BS2
58
61
62
63
64
65
66
SPI serial clock the SCK signal is used to synchronize the data
transfer. If HT9580 is in the master mode, the SCK is output
clock. Otherwise, SCK is input clock if HT9580 is in the slave
mode.
SCK
I/O
BS1
SS
SPI slave select this signal is used to enable the SPI slave for
transfer.
TS
Decoder test mode input pin, active low with pull-high resistor.
I/O
72~67
PA0~PA5
73
RESET
74
TSC
mC test mode input pin, active low with internal pull-high resistor. The test circuit will be activated when this pin pulls low.
75
TS1
Decoder test mode input pin, active low with pull-high resistor.
The internal test mode will be activated when this pin pulls low.
77
76
OSC1
OSC2
I
O
80
79
X1
X2
I
O
Preliminary
HT9580
D.C. Characteristics
Symbol
Parameter
Ta=25C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3V application
2.4
3.0
3.5
IDD
Operating Current
3V
No load,
OSC1=1MHz
fX1=76.8kHz
300
mA
ISTP
3V
100
mA
VIL
3V
0.3VDD
VIH
3V
0.7VDD
VIL1
3V
0.3VDD
VIH1
3V
0.7VDD
VIL2
3V
0.9
VIH2
3V
1.0
VOL
3V
0.4
VOH
3V
2.3
IOL
3V
VOL=0.3V
2.0
3.6
mA
IOH
3V
VOH=2.7V
-1.2
-2.2
mA
IOL1
3V
VOL=0.3V
4.5
mA
IOH1
3V
VOH=2.7V
-1.5
-2.5
mA
IOL2
3V
VOL=0.3V
350
mA
IOH2
VOH=2.7V
-1.0
mA
ROSC
RC Oscillator Resistor
3V
fOSC=1MHz
51
kW
RPH
3V
100
250
kW
Preliminary
HT9580
A.C. Characteristics
Symbol
Ta=25C
Parameter
Test Conditions
VDD Conditions
Min.
Typ.
Max.
Unit
fOSC1
3V
76.8
1000
2000
kHz
DOSC1
3V
40
50
60
fX1
3V
32.768
76.8
153.6
kHz
tRESET
ms
Functional Description
Memory map
0 0 0 0 H
0 0 3 B H
0 0 4 0 H
0 0 6 D H
0 0 8 0 H
0 1 C F H
0 1 D 0 H
0 1 F F H
0 2 0 0 H
0 3 F F H
I/O
a n d D a ta S p a c e
6 0 B y te s
1 0 0 0 H
M e s s a g e B u ffe r
4 6 B y te s
G lo b a l D a ta M e m o r y
3 3 6 B y te s
In te rn a l
C h a ra c te r R O M
S p a c e
(B a n k 0 )
8 K b y te s
2 F F F H
S ta c k s
4 8 B y te s
B a n k 0 ~ B a n k 3 1 ( 2 M b its )
G lo b a l D a ta M e m o r y
5 1 2 B y te s
1 0 0 0 H
1 0 0 0 H
In te r n a l/E x te r n a l
C h a ra c te r R O M
8 K b y te s
E x te rn a l
C h a ra c te r R O M
S p a c e
(B a n k 0 )
8 K b y te s
2 F F F H
2 F F F H
3 0 0 0 H
In te r n a l/E x te r n a l
S R A M
8 K b y te s
B a n k 0 ~ B a n k 3 1 ( 2 M b its )
4 F F F H
5 0 0 0 H
3 0 0 0 H
P ro g ra m R O M S p a c e
2 8 K B y te s
In
S
S
(B
te rn a l
R A M
p a c e
a n k 0 )
8 K b y te s
4 F F F H
B F F F H
C 0 0 0 H
B a n k 0 ~ B a n k 3 (3 2 K B y te s )
P ro g ra m R O M S p a c e
1 6 3 7 8 B y te s
F F F A H
N M I-L
F F F B H
N M I-H
F F F C H
R E S E T -L
F F F D H
R E S E T -H
F F F E H
IR Q -L
F F F F H
IR Q -H
3 0 0 0 H
E x te rn a l
S R A M
S p a c e
(B a n k 0 )
8 K b y te s
4 F F F H
B a n k 0 ~ B a n k 3 1 (2 5 6 K B y te s )
Preliminary
HT9580
Bit 7
Bit 6
0000H
Config.
HALT
CLK_SEL
0001H
WDT-TMR
0002H
CLR WDT
Address
Bit 5
Bit 4
OSC_MOD
LPM
TMR0_PR1 TMR0_PR0
X
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0001 0000
RTC
BZ_CLK
MDUT
MGEN
WDTEN
WS2
WS1
WS0
0000 0111
uuuu uuuu
0003H
BZ-L
BZL7
BZL6
BZL5
BZL4
BZL3
BZL2
BZL1
BZL0
0000 0000
0004H
BZ-H
BZH7
BZH6
BZH5
BZH4
BZH3
BZH2
BZH1
BZH0
0000 0000
0005H
INT ctrl
RTCEN
ORMSK
RTCMSK
0006H
INT flag
RTC_FG
DR_FG
BF_FG
WDTOVFG
OR_FG
0007H
TMRC
TMR1MOD
TMR1EN
TMR0EN
0000 0000
0008H
TMR1L
TM1D7
TM1D6
TM1D5
TM1D4
TM1D3
TM1D2
TM1D1
TM1D0
uuuu uuuu
TM1IMSK TM0IMSK
0000 1111
0009H
TMR1H
TM1D15
TM1D14
TM1D13
TM1D12
TM1D11
TM1D10
TM1D9
TM1D8
uuuu uuuu
000AH
TMR0
TM0D7
TM0D6
TM0D5
TM0D4
TM0D3
TM0D2
TM0D1
TM0D0
uuuu uuuu
000BH
PA data
PA5
PA4
PA3
PA2
PA1
PA0
uu11 1111
000CH
PB data
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
1111 1111
000DH
PC data
PC1
PC0
uuuu uu11
uu11 1111
000EH
PAC
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
000FH
PBC
PBC7
PBC6
PBC5
PBC4
PBC3
PBC3
PBC1
PBC0
1111 1111
0010H
PCC
PCC1
PCC0
uuuu uu11
0011H
PA WUE
PAWUE5
PAWUE4
PAWUE3
PAWUE2
PAWUE1
PAWUE0
uu00 0000
0012H
PA IM
PAIM5
PAIM4
PAIM3
PAIM2
PAIM1
PAIM0
uu11 1111
0013H
PB IM
PBIM7
PBIM6
PBIM5
PBIM4
PBIM3
PBIM2
PBIM1
PBIM0
1111 1111
0014H
PC IM
PCIM1
PCIM0
uuuu uu11
0015H
MROM-BP
BP_MODM1 BP_MODM0
M_BP5
M_BP4
M_BP3
M_BP2
M_BP1
M_BP0
0000 0000
0016H
SRAM-BP
BP_MODS1
S_BP5
S_BP4
S_BP3
S_BP2
S_BP1
S_BP0
0000 0000
0017H
LCD_CTRL
LCD-CLK
CLK-MOD
LCD-CS1
LCD-CS0
LCD-A0
LCD-WRB
0000 1101
0018H
LCD_CMD
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
uuuu uuuu
0019H
Decoder
Control/
flag
BL
OR
STB
RES
ON
uu0u uu01
001AH~
002EH
Decoder
Configuration
Memory
BP_MODS0
LCD-CHIP1 LCD-CHIP0
uuuu uuuu
002FH
D/A-L
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0000 0000
0030H
D/A-H
D/A_PD
RSSI
BAT
uuuu u1uu
0031H
Buffer
Status
MSG_END
count_5
count_4
count_3
count_2
count_1
count_0
0uuu uuuu
0032H
SPI-CONFIG
S/M
LEN1
LEN0
REQST
SPIFG
CLK_EDG
SPI_EN
START
0111 1000
0033H
SPI-SPEED
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0000 0000
0034H
SPI-OUT3
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0035H
SPI-OUT2
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0036H
SPI-OUT1
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0037H
SPI-OUT0
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0038H
SPI-IN3
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0039H
SPI-IN2
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
003AH
SPI-IN1
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
003BH
SPI-IN0
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
Preliminary
HT9580
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0000H
Config.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0001 0000
0001H
WDT-TMR
R/W
R/W
R/W
R/W
R/W
R/W
0000 0111
0002H
CLR WDT
uuuu uuuu
Address
0003H
BZ-L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0004H
BZ-H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0005H
INT ctrl
R/W
R/W
R/W
R/W
R/W
0000 1111
0006H
INT flag
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0007H
TMRC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0008H
TMR1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
0009H
TMR1H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
000AH
TMR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
000BH
PA data
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
000CH
PB data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
000DH
PC data
R/W
R/W
uuuu uuuu
000EH
PAC
R/W
R/W
R/W
R/W
R/W
R/W
uu11 1111
000FH
PBC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1111 1111
0010H
PCC
R/W
R/W
uuuu uu11
0011H
PA WUE
R/W
R/W
R/W
R/W
R/W
R/W
uu00 0000
0012H
PA IM
R/W
R/W
R/W
R/W
R/W
R/W
uu00 0000
0013H
PB IM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0014H
PC IM
R/W
R/W
uuuu uu00
0015H
MROM-BP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0016H
SRAM-BP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0017H
LCD_CTRL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 1101
0018H
LCD_CMD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
0019H
Decoder
Control/
flag
R/W
R/W
R/W
uu0u uu01
001AH~
002EH
Decoder
Configuration
Memory
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
uuuu uuuu
002FH
D/A-L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0030H
D/A-H
R/W
uuuu u1uu
0031H
Buffer
Status
0uuu uuuu
0032H
SPI-CONFIG
R/W
R/W
R/W
R/W
R/W
R/W
0111 1000
0033H
SPI-SPEED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0034H
SPI-OUT3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0035H
SPI-OUT2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0036H
SPI-OUT1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0037H
SPI-OUT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000
0038H
SPI-IN3
0000 0000
0039H
SPI-IN2
0000 0000
003AH
SPI-IN1
0000 0000
003BH
SPI-IN0
0000 0000
Preliminary
HT9580
Configuration register
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0000H
Config.
HALT
CLK_SEL
OSC_MOD
LPM
RTC
BZ_CLK
MDUT
MGEN
0001 0000
Oscillator configuration
O S C 1
O S C _ M O D
O S C
C o n tro l
X 1 - c lo c k
S S T
1 0 - b it R ip p le
C o u n te r
F re q u e n c y
D o u b le r
D F
S u b - c lo c k
0 : R C
1 : D F
O S C
In p u t
The HT9580 will generate two RTC frequencies, 1Hz and 2Hz respectively, determined by
bit RTC. If the bit is logic low, the 1Hz RTC frequency will be selected, otherwise the 2Hz RTC
frequency will be selected. The RTC counter is
enabled/disabled by bit RTCEN and can be
masked or not masked as determined by the bit
RTCMSK of the interrupt control register
X 1 - c lo c k
X 1
S S T C o n tro l
H A L T
C lo c k S e le c t
C L K _ S E L
S y s te m
C lo c k
0 : X 1 - c lo c k
1 : O S C In p u t
1 H z & T im e O u t
X 1 - c lo c k
C o u n te r
R T C
2 H z & T im e O u t
T im e O u t
R T C
Preliminary
(0005H). If the RTC counter is enabled, the
RTC counter will start to count. The RTC counter source clock is the X1-clock, so the X1 clock
setting via by SPF12, SPF13 and SPF14 should
be correct.
RTC
D D
1 0 0 k W
L P M
(L o w
p o w e r m o d e c o n tr o l)
5 0 k W
HT9580
X 2
H T 9 5 8 0
5 0 k W
X 1
1 0 0 k W
V S S
L o w
p o w e r o s c illa to r fu n c tio n
The system clock oscillator can be enabled/disabled by the register bit, HALT. The system
clock circuit is powered down, when the bit is
set to high. On the other hand, the system clock
System clock
HALT
enable
System clock
powered down
Register
Name
Bit 7
Bit 6
0001H
WDT-TMR
0002H
CLR WDT
Bit 5
Bit 4
TMR0_PR1 TMR0_PR0
X
State on
POR
Bit 3
Bit 2
Bit 1
Bit 0
WDTEN
WS2
WS1
WS0
0000 0011
uuuu uuuu
sub-clock divided by 8. The counter is segmented as a 9-bit prescaler and a 7-bit user programmable counter. The input clock is first
divided by 512 (9-stage) to get the nominal
time-out period. The output of the 9-bit
pre-scaler can then be divided by a 7-bit programmable counter to generate the longer
watchdog time-out depending on the users requirements. The 7-bit programmable counter is
controlled by 3 register bits, WS0~2. The
watchdog timer is enabled/disabled by a control
bit WDTEN. To prevent the overflow of this
watchdog timer, a clear-WDT operation should
1
Enable the
WDTEN
watchdog timer
11
0
Disable the
watchdog timer
Preliminary
The WDT 7-bit counter is programmed by bits
WS0~WS2. The division ratio for the counter is
listed in the table.
WS2
WS1
WS0
Division
Ratio
1:1
HT9580
TMR0_PR0
TMR0
Prescaler
Ratio
1:2
1/4
1:4
1/8
1:8
1:16
1/16
1:32
1/32
1:64
1:128
1 /8
X 1 - c lo c k
9 - b it P r e s c a le r
W S 0 ~ 2
7 - b it C o u n te r
8 to 1 M U X
W D T tim e - o u t
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
State on
POR
Bit 0
0003H
BZ-L
BZL7
BZL6
BZL5
BZL4
BZL3
BZL2
BZL1
BZL0
0000 0000
0004H
BZ-H
BZH7
BZH6
BZH5
BZH4
BZH3
BZH2
BZH1
BZH0
0000 0000
12
Enable the
Disable the
buzzer generator buzzer generator
Preliminary
the application circuits is always active. Therefore it is recommended that both BZ-L and
BZ-H be cleared and that the MGEN bit in the
configuration register (0000H) also be cleared,
when it is desired to disable or stop the buzzer.
When BZ-L and BZ-H are all 00H, the tone generator is disabled and BZ is high. The value of
t h e f r eq uenc y d i v i d er, r a ng es fr o m 2
(BZ-L=01H, BZ-H=00H)~65536 (BZ-L=FFH,
BZ-H=FFH). Writing to BZ-L only writes the
data into a low byte buffer, while writing to
BZ-H will write the high byte data and the contents of the low byte buffer into the PFD counter.
S y s te m
C lo c k
X 1 - c lo c k
HT9580
X 1 - c lo c k
B Z _ C L K = 0
1 6 - b it
P F D C o u n te r
B Z _ C L K = 1
P W M
M o d u la to r
M G E N
B Z _ C L K
B Z
M D U T
M D U T = 0
M D U T = 1
Interrupt registers
Register
Name
Bit 7
0005H
INT ctrl
0006H
INT flag
Address
Bit 6
Bit 5
Bit 4
RTC_FG
DR_FG
Bit 1
Bit 0
State on
POR
Bit 3
Bit 2
RTCEN
ORMSK
RTCMSK
TM1IMSK
TM0IMSK
0000 1111
BF_FG
WDTOVFG
OR_FG
TM1OVFG
TM0OVFG
0000 0000
Preliminary
timer overflow and RTC_FG is an indicator for
the RTC time out interrupt request flag. The
OR_FG will be set high when an out-of-range
status from low to high or high to low transition
occurrs. Those flags such as TM0OVFG,
TM1OVFG, BF_FG, DR_FG, OR_FG and
RTC_FG should be cleared by the software after they are activated.
1
HT9580
1
TM0OVFG
Timer 0
overflows
No timer 0
overflow
TM1OVFG
Timer 1
overflows
No timer 1
overflow
Watchdog
WDTOVFG timer has
overflown
No watchdog
timer overflow
RTCEN
RTC counter is
enabled
RTC counter is
disabled
BF_FG
Battery fail
request
No battery fail
request
RTCMSK
RTC interrupt
is masked
RTC interrupt is
not masked
DR_FG
Data ready
request
No data ready
request
TM0IMSK
OR_FG
Out-of-range
request
No out-of-range
request
Timer 1
overflow
interrupt is not
masked
RTC_FG
RTC interrupt
request
TM1IMSK
Timer 1
overflow
interrupt is
masked
No RTC
interrupt
request
ORMSK
Out-of-range
interrupt is
masked
Out-of-range
interrupt is not
masked
D a ta R e a d y
S P I R e q s t
B a tte r y F a il
N M I
M 6 5 0 2
C o r e
T M 0 /1 IM S K
T M 0 /1 O V F G
R T C _ F G
IR Q
R T C M S K
O R _ F G
O R M S K
14
Preliminary
tim e r 0
o v e r flo w
tim e r 1
o v e r flo w
tim e r 0
o v e r flo w
tim e r 1
o v e r flo w
HT9580
tim e r 0
o v e r flo w
tim e r 0
o v e r flo w
tim e
IR Q
M a s k e d b y
T M 0 O V F G
M a s k e d b y
T M 0 IM S K
M a s k e d b y
T M 1 O V F G
T M 0 IM S K
T M 1 IM S K
C le a r e d b y s o ftw a r e
C le a r e d b y s o ftw a r e
C le a r e d b y s o ftw a r e
T M 0 O V F G
C le a r e d b y s o ftw a r e
C le a r e d b y s o ftw a r e
T M 1 O V F G
least 1 ms
15
Preliminary
HT9580
5 0 0 0 H
P ro g ra m
R O M
S p a c e
F F F A H
D a ta R e a d y & B a tte r y F a il S e r v ic e
R o u tin e V e c to r L o w B y te
F F F B H
D a ta R e a d y & B a tte r y F a il S e r v ic e
R o u tin e V e c to r H ig h B y te
F F F C H
P ro g ra m
R e s e t V e c to r L o w
F F F D H
P ro g ra m
R e s e t V e c to r H ig h B y te
R E S E T
B y te
F F F E H
IR Q
S e r v ic e R o u tin e V e c to r L o w
F F F F H
IR Q
S e r v ic e R o u tin e V e c to r H ig h B y te
R E S E T
In te r n a l P u ll- u p
S y s te m
C lo c k
D D
H T 9 5 8 0
B y te
P o w e r O n D e te c to r
1 0 - b it R ip p le C o u n te r
C h ip R e s e t G e n e r a to r
W D T O v e r flo w
V D D
V D D
1 0 2 4 C lo c k C y c le s
8 C lo c k C y c le s
R E S E T
O S C
R E S E T
T im e - O u t
W D T T im e - O u t
C h ip R e s e t
C h ip R e s e t
16
Preliminary
HT9580
Timer registers
Register
Name
Bit 7
0007H
TMRC
0008H
TMR1L
0009H
000AH
Address
State on
POR
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1MOD
TMR1CLK
TMR0CLK
TMR1EDG
TMR0EDG
TMR1EN
TMR0EN
0u00 0000
TM1D7
TM1D6
TM1D5
TM1D4
TM1D3
TM1D2
TM1D1
TM1D0
uuuu uuuu
TMR1H
TM1D15
TM1D14
TM1D13
TM1D12
TM1D11
TM1D10
TM1D9
TM1D8
uuuu uuuu
TMR0
TM0D7
TM0D6
TM0D5
TM0D4
TM0D3
TM0D2
TM0D1
TM0D0
uuuu uuuu
Bits
Function
TMR0EN,
TMR1EN
0
1
TMR0EDG,
TMR1EDG
2
3
TMR0CLK
TMR1CLK
TMR1MOD
17
Preliminary
S y s te m
T M R 0 C L K
1
C lo c k
D a ta B u s
T im e r C o u n te r
P r e lo a d R e g is te r
0
X 1 - C lo c k
HT9580
P r e s c a le r
T M R 0 _ P R 1
E d g e S e le c t
T M R 0 _ P R 0
T im e r 0 C o u n te r
( 8 - b it)
T M R 0 E D G
R e lo a d
O v e r flo w
T o In te rru p t
T M R 0 E N
S y s te m
T M R 1 C L K
1
C lo c k
X 1 - C lo c k
D a ta B u s
T im e r /e v e n t C o u n te r
P r e lo a d R e g is te r
0
R e lo a d
T M R 1
E d g e S e le c t
1
T M R 1 M O D
T im e r 1 C o u n te r
( 1 6 - b it)
T M R 1 E D G
O v e r flo w
T o In te rru p t
T M R 1 E N
18
Preliminary
HT9580
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
uu11 1111
000BH
PA data
PA5
PA4
PA3
PA2
PA1
PA0
000CH
PB data
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
1111 1111
000DH
PC data
PC1
PC0
uuuu uu11
000EH
PAC
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
uu11 1111
000FH
PBC
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
1111 1111
0010H
PCC
PCC1
PCC0
uuuu uu11
0011H
PA WUE
PAWUE5
PAWUE4
PAWUE3
PAWUE2
PAWUE1
PAWUE0
uu00 0000
0012H
PA IM
PAIM5
PAIM4
PAIM3
PAIM2
PAIM1
PAIM0
uu11 1111
0013H
PB IM
PBIM7
PBIM6
PBIM5
PBIM4
PBIM3
PBIM2
PBIM1
PBIM0
1111 1111
0014H
PC IM
PCIM1
PCIM0
uuuu uu11
Port B
Port B is a general-purpose I/O port controlled
by the PBC register. The PBIM register controls the input cell structures: normal CMOS
inputs or CMOS inputs with pull-high resistors.
Port A
Port A is a general-purpose I/O port. The PAC
register controls the data directions for port A.
When set as input data type, this port has
wake-up capability and the input cell structures are schmitt trigger types. While in a
HALT condition, a falling edge signal on Port
A can wake-up the mC. In addition, the input
cell structures can be configured as pull-high or
non-pull-high. When set as an output data type,
the output structures are CMOS outputs.
1
The pin output
logic high
PAC
As input pin
As output pin
PAIM
CMOS input
structure
with pull-high
resistor
0
Pin output
logic low
PBC
Input pin
Output pin
PBIM
CMOS input
CMOS input
structure with
structure without
pull-high
pull-high resistor
resistor
PB
PA
1
Pin output
logic high
Port C
This is a general-purpose I/O port contolled by
the PCC register. The PCIM register controls
the input cell structures: normal CMOS inputs
or CMOS inputs with pull-high resistors.
1
PC
CMOS input
structure without pull-high
resistor
19
0
The pin output
logic low
PCC
As input pin
As output pin
PCIM
CMOS input
structure
with pull-high
resistor
CMOS input
structure
without pull-high
resistor
Preliminary
V
E N
M
D D
P u ll- u p
R e s is to r
X
P A D a ta
HT9580
P A C
P A W U E
P A IM
O n e
S h o t
C ir c u it
T o
C P U
Register
Name
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
M_BP5
M_BP4
M_BP3
M_BP2
M_BP1
M_BP0
0000 0000
Bit 6
M_BP4
M_BP3
M_BP2
31
32
Reserved
Reserved
63
Reserved
Reserved
Memory Area
20
31
Preliminary
HT9580
0 0 0 0 0 H
C N S P a tte rn
(G B P a tte rn )
(A 1 8 = "0 ")
3 F F F F H
4 0 0 0 0 H
R e s e rv e d
(A 1 8 = "1 ")
Step 1
7 F F F F H
Step 5
The formula obtains A0~A18 from the received GB or CNS code. If it is in the lower 2
Mbits space, A18=0. Otherwise, A18=1 if it is
in reserved space.
The following example will load 32 bytes continuous (one Chinese word) pattern from the
internal mask ROM and store them to the
start address $C3C2C1C0 H (if absolute index
addressing mode is used).
Step 2
LDX #00H
LDY #00H
READ:
LDA $B3B2B1B0, X
STA $C3C2C1C0, Y
INX
INY
CPX #20H
BNZ READ
Step 3
A 1 2
A 1 1
A 1 0
A 1 1
A 1 0
B
3
R A 1 3
R A 1 2
(0 ,0 ,R A 1 3 ,R A 1 2 )
B
2
A 9
0
A 8
0
A 9
A 7
A 6
0
A 8
0
A 7
(A 1 1 ,A 1 0 ,A 9 ,A 8 )
21
A 6
B
1
A 5
0
A 4
0
A 5
A 3
A 2
0
A 4
(A 7 ,A 6 ,A 5 ,A 4 )
0
A 3
A 2
B
0
A 1
0
A 0
0
A 1
A 0
(A 3 ,A 2 ,A 1 ,A 0 )
Preliminary
HT9580
Register
Name
0016H
SRAM-BP
Bit 7
Bit 6
BP_MODS1 BP_MODS0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
S_BP5
S_BP4
S_BP3
S_BP2
S_BP1
S_BP0
0000 0000
The SRAM bank point register can switch to either external 256 Kbytes or internal 32 Kbytes
SRAM space. The selection table is based on the
following table. The space size of each SRAM
bank is 8 Kbytes. Bits BP_MODS1 and
BP_MODS0 define whether internal or external SRAM devices are used. (BP_MODS1,
BP_MODS0)=(0, 1), is for internal SRAM deBP_MODS1 BP_MODS0
S_BP5
S_BP4
S_BP3
S_BP2
S_BP1
S_BP0
BP Value
Memory Area
Reserved
Reserved
Reserved
63
Reserved
31
Register
Name
Bit 7
0017H
LCD_CTRL LCD-CHIP1
0018H
LCD_CMD
LCD_D7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LCD-CHIP0
LCD-CLK
CLK-MOD
LCD-CS1
LCD_D6
LCD_D5
LCD_D4
LCD_D3
State on
POR
Bit 1
Bit 0
LCD-CS0
LCD-A0
LCD-WRB
0000 1101
LCD_D2
LCD_D1
LCD_D0
uuuu uuuu
LCD-CTRL register corresponds to the chip select pin of the LCD driver. The bit LCD-CS0 is
used to control the master LCD driver chip
while LCD-CS1 is for the slave LCD driver
chip. Both bits are active low. The bit
CLK_MOD is used to enable or disable the
pin out of LCD_CL. If the bit is set low, the
clock output of pin LCD_CL will be disabled,
otherwise the LCD_CL clock will be set according to the following Truth Table.
22
Preliminary
HT9580
LCD-CHIP0=1
LCD-CHIP1=0
LCD-CHIP1=1
N/A
LCD-CHIP0=1
LCD-CHIP1=0
LCD-CHIP1=1
N/A
The following is a comparison table of the HT9580 pin description between the SED15X (KSX) series
and the MC141X series LCD driver.
HT9580
(Pin)
LCD_A0
SED15X(KSX) Series
A0
MC141X Series
LCD_CS0 CS (Master)
LCD_CS1 CS (Slave)
D0~D7
CS
R/W
OSC2
LCD_E
D0~D7
LCD_RW R/W
LCD_CL
CL
Read/write input
23
Preliminary
L C D
5
L C D _ A 0
3
M a s te r
S la v e
C S (M a s te r)
2
L C D _ C S 1 ( S la v e )
C S ( S la v e )
1 5 ~ 8
D 0 ~ D 7
D 0 ~ D 7
L C D _ E
S E D 1 5 X (K S X )
E
L C D _ R W
R /W
4
L C D _ C L
D r iv e r
A 0
L C D _ C S 0 (M a s te r)
H T 9 5 8 0
HT9580
C L
a n d "L C D -C H IP 0 " = 0
L C D D r iv e r
5
L C D _ A 0
3
L C D _ C S 0 (M a s te r)
C E ( S la v e )
1 5 ~ 8
D 0 ~ D 7
D 0 ~ D 7
L C D _ E
M C 1 4 1 X
C S
6
L C D _ R W
L C D _ C L
S la v e
C E (M a s te r)
2
L C D _ C S 1 ( S la v e )
H T 9 5 8 0
M a s te r
D /C
R /W
4
O S C 2
24
a n d "L C D -C H IP 0 " = 1
Preliminary
L C D
5
L C D _ A 0
3
M a s te r
C S ( S la v e )
1 5 ~ 8
D 0 ~ D 7
D 0 ~ D 7
H D 6 6 4 1 0
R D
L C D _ E
6
W R
L C D _ R W
4
C R
LCD-CHIP0="0"
LCD-CHIP1="0"
LCD-CHIP0="1"
LCD-CHIP1="0"
S la v e
C S (M a s te r)
2
L C D _ C S 1 ( S la v e )
L C D _ C L
D r iv e r
R S
L C D _ C S 0 (M a s te r)
H T 9 5 8 0
HT9580
Application
a n d "L C D -C H IP 0 " = 0
Note
LCD-CHIP0="0"
LCD-CHIP1="1"
LCD-CHIP0="1"
LCD-CHIP1="1"
N/A
The contents of the on-chip RAM and of the register remain unchanged.
25
Preliminary
HT9580
D/A registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
002FH
D/A-L
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0000 0000
0030H
D/A-H
D/A_PD
RSSI
BAT
uuuu u1uu
Address
Bit 2
Bit 0
State on
POR
The system can quit the HALT mode by an external reset, an interrupt, an external falling
edge signal on port A or an RTC time out.
The HT9580 has one internal 8-bit D/A converter which can measure the battery voltage
and the RSSI input signal from the IF of the RF
circuit. The DA0~DA7 is the digital input of the
D/A converter and the analog outputs to the pin
named DA_OUT. Bit BAT of the DA-H register
(0030H) is the output of the comparator. Its input at the - terminal is from the D/A output
and the + terminal comes from the input pin
R S S I
V
Bit 1
D D
B A T
B A T
D /A _ P D
V D D
(D /A )
D A 7
D A 6
D A 5
V S S
D A 4
D A 3
D A 2
D A 1
D A 0
D A _ O U T
2 R
2 R
2 R
2 R
2 R
2 R
2 R
2 R
R
R
2 R
T h e c o n fig u r a tio n o f th e 8 - b it D /A c o n v e r te r a n d p o w e r d o w n c o n tr o l
26
Preliminary
HT9580
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0031H
Buffer
Status
MSG_END
count_5
count_4
count_3
count_2
count_1
count_0
0uuu uuuu
M e s s a g e B u ffe r
0 0 4 0 H
A d d re s s C o d e w o rd
0 0 4 1 H
M e s s a g e C o d e w o rd 1
0 0 4 2 H
M e s s a g e C o d e w o rd 2
0 0 5 3 H
M e s s a g e C o d e w o rd 1 9
0 0 5 4 H
M e s s a g e C o d e w o rd 2 0
0 0 5 5 H
N /A
0 0 6 D H
N /A
0 0 3 1 H
Example 1
27
Preliminary
HT9580
M e s s a g e B u ffe r
0 0 4 0 H
A d d re s s C o d e w o rd
0 0 4 0 H
M e s s a g e C o d e w o rd 4 6
0 0 4 1 H
M e s s a g e C o d e w o rd 1
0 0 4 1 H
M e s s a g e C o d e w o rd 4 7
0 0 4 2 H
M e s s a g e C o d e w o rd 2
0 0 4 2 H
M e s s a g e C o d e w o rd 4 8
0 0 4 3 H
M e s s a g e C o d e w o rd 4 9
0 0 4 4 H
M e s s a g e C o d e w o rd 5 0
0 0 4 5 H
N /A
0 0 6 D H
N /A
0 0 6 C H
M e s s a g e C o d e w o rd 4 4
0 0 6 D H
M e s s a g e C o d e w o rd 4 5
0 0 3 1 H
1 s t D a ta R e a d y In te rru p t
0 0 3 1 H
2 n d D a ta R e a d y In te rru p t
Example 2
The data ready interrupt will generate when
message is terminated, synchronization code
P O C S A G D A T A
S tru c tu re
F ra m e 5
F ra m e 6
F ra m e 7
S y n c
F ra m e 0
F ra m e 1
F ra m e 2
D I
N M I
D R _ F G
M e s s a g e B u ffe r
(4 6 b y te s )
V a lid D a ta
28
Preliminary
HT9580
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
State on
POR
0032H
SPI-CONFIG
S/M
LEN1
LEN0
REQST
SPIFG
CLK_EDG
SPI_EN
START
0111 1000
S/M
Master mode
(SCK is output)
Slave mode
(SCK is input)
Rising edge
Falling edge
LEN0
16
32
1
The SPI circuit and SPI
I/O pins will
be enabled
START
No data exchange
Data
exchange
start
29
Preliminary
HT9580
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
State on
POR
0033H
SPI-SPEED
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0000 0000
The register will determine the SCK clock frequency of SPI. When SPEED register are 00H, the SCK
clock output is high. The value of the frequency divider, ranging from 1 (SPEED=01H)~255
(SPEED=FFH). If SPEED=00H, the SCK output will be disabled.
X 1 - c lo c k
8 - b it S P E E D C o u n te r
S C K
S P I C o n tro l
S P I
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
State on
POR
0034H
SPI-OUT3
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0035H
SPI-OUT2
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0036H
SPI-OUT1
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0037H
SPI-OUT0
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
The SPI-OUT3~0 are used when transmitting data on the serial bus. Only valid data write to the register SPI-OUT3~0 and "START" initiating will begin the SPI data transmission from HT9580 to
FLEXTM decoder. After completion of the 4-byte data transfer, the "SPIFG" status bit will be set and
the internal signal REQST will generate a falling edge signal for NMI. The bit7 of SPI-OUT3 is
MSB and bit0 of SPI-OUT0 is LSB.
S P IF G
R E Q S T
(N M I)
R E Q S T
( r e g is te r )
L o g ic H ig h
S T A R T
( r e g is te r )
S C K
(fro m
M O S I
H T 9 5 8 0 )
S P I-O U T 3 ~ 0
(fro m
M IS O
d e c o d e r)
S P I-IN 3 ~ 0
M S B
M S B
L S B
L S B
S S (to d e c o d e r)
(fro m
S R D Y
d e c o d e r)
S P I p a c k e t e x c h a n g e in itia te d b y th e H T 9 5 8 0
30
Preliminary
HT9580
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
State on
POR
0038H
SPI-IN3
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
0039H
SPI-IN2
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
003AH
SPI-IN1
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
003BH
SPI-IN0
D7
D6
D5
D4
D3
D2
D1
D0
0000 0000
The SPI-IN3~0 are used when receiving data on the serial bus. When SPI transmits only valid data
writes to the register SPI-OUT3~0, "START" will initiate the SPI data transmission from HT9580 to
FLEXTM decoder. After completion of the 4-byte data transfer, the "SPIFG" status bit will be set and
the internal signal "REQST" will generate a falling edge signal for NMI. The bit7 of SPI-IN3 is MSB
and bit0 of SPI-IN0 is LSB.
S P IF G
R E Q S T
(N M I)
R E Q S T
( r e g is te r )
S T A R T
( r e g is te r )
S C K
(fro m
M IS O
d e c o d e r)
S P I-IN 3 ~ 0
(fro m
M O S I
H T 9 5 8 0 )
S P I-O U T 3 ~ 0
M S B
M S B
L S B
1
L S B
S S (to d e c o d e r)
(fro m
S R D Y
d e c o d e r)
S P I p a c k e t e x c h a n g e in itia te d b y th e H T 9 5 8 0
31
Preliminary
The POCSAG paging code
P R E A M B L E
HT9580
B A T C H 2
L A S T B A T C H
1 0 1 0 .........1 0 1 0 1 0 1 0 1 0
S y n c h
C W
C W
B it N u m b e r
1
0
A d d re s s c o d e w o rd
C W
C W
F R A M E 0
C W
F R A M E 1
2 to 1 9
2 0 /2 1
1 8 A d d r e s s B its
2 F u n c tio n
B its
2 0
2 2 to 3 1
M e s s a g e B its
M e s s a g e c o d e w o rd
Id le c o d e w o r d
3 1 Id le c o d e
S y n c h c o d e w o rd
3 1 S y n c h c o d e
C W
F R A M E 7
3 2
1 0
C R C
b its
1 0
C R C
b its
P
P
B it p a tte r n
B it p a tte r n
Bit 21 (LSB)
Call Type
Data Format
Numeric
4-bit package
Alert only
Alert only
Alpha-numeric
7-bit package
32
Preliminary
On status
In the ON status, the decoder pulses the receiver, quick charge and PLL enable outputs
(respectively BS1, BS2 and BS3) according to
the code structure and the synchronization
algorithm. Data received serially at the data
input (DI) is processed for call receipt.
STB status
In the STB status the decoder will neither activate the receiver, quick charge or PLL enable outputs, nor process any data at the data
input. The crystal oscillator remains active to
permit communication with the microcontroller.
Battery saving
Error correction
Item
Description
Address
code-word
Message
code-word
Operating states
Bit rates
ON status
STANDBY status
The operating state is determined by control
address (0019H) bit 0 and monitored by bit 3
of address (0019H).
Operating Status
On state
STANDBY state
HT9580
33
Preliminary
HT9580
The filtered data is used to synchronize an internal clock generator by monitoring transitions. The recovered clock phase can be
adjusted in steps of 1/8, 3/32, 1/16, or 1/32 bit
period per received bit.
All step size are used when bit synchronization has not been achieved, the smallest when
a valid data sequence has been detected.
Erroneous code-words
Function Bits
Description
Any two consecutive
code-words or the
code-word directly following
the address code-word in
error
Bit 20 (MSB)
Bit 21 (LSB)
SPF16=0
Numeric (4-bit)
SPF17=0
Numeric (4-bit)
SPF18=1
Alphanumeric
(7-bit)
SPF19=1
Alphanumeric
(7-bit)
The decoder data output format is determined by the value SPF16~SPF19. When it is
logic low, the 4-bit (numeric) package will be
selected. Otherwise, the 7-bit (alphanumeric)
package is selected. The following tables illustrate the above two different conditions.
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Error Flag
D3
D2
D1
D0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Error Flag
D6
D5
D4
D3
D2
D1
D0
10
11
12
13
14
15
Bit
Bit No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
34
Preliminary
Idle word indication
HT9580
10
11
12
13
14
15
Bit
Bit No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
Error indication
After error correction, any code-word containing more than 2-bit random errors or 4-bit
burst errors (option) in the address or message code-word may be indicated from the error flag position.
Decoder and mC interface
B it 4
D R _ F G
(0 0 0 6 H )
B F _ F G
(0 0 0 6 H )
0 0 1 9 H
B it 7
B it 6
B it 5
B L
O R
B it 4
B it 3
B it 2
S T B
B it 1
B it 0
R E S
O N
B it 0
B it 1
B it 2
B it 3
B it 4
P O C S A G
D I
B A
B S
B S
B S
D e c o d e r
D e c o d e r D a ta O u tp u t
R F
C K T .
D a ta R e a d y In te rru p t
S P I R E Q S T
V
m C (N M I)
1
m C P A 7
(W a k e u p )
3
R S S I
B it 5
B it 6
B it 7
M e s s a g e B u ffe r
(4 6 B y te s )
P a g e r S y s te m
C L K
D e b o u n c e
C ir c u it
IL
IH
= 0 .9 V
= 1 .0 V
B A F ( B a tte r y F a il In te r r u p t)
Note: The value of 0019H-bit3 STB is set when decoder enters the standby mode and cleared when decoder enters the ON mode.
The value of 0006H-bit4 BF_FG is dependent on the BAF pin ststus.
The value of 0019H-bit5 OR is always changed by an out of range signal.
The value of 0019H-bit6 BL is cleared 0" by the decoder Battery low signal and set 1" when
the mC sets this bit high.
The value of 0006H-bit5 DR_FG is set 1" by the decoder Data-Ready interrupt signal and
cleared 0 when the mC clears DR_FG.
35
Preliminary
HT9580
DR_FG
Bit
R/W
Description
R/W
ON
RES
Bit
R/W
Description
R/W
R/W
36
Preliminary
Symbol
STB
OR
BL
Bit
3
HT9580
R/W
Description
R/W
37
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
Preliminary
Test mode
HT9580
the received data (including address codeword and message codeword) length is terminated within 46 bytes, one batch is over
or if the 46 bytes data buffer is full if data
length is more than 46 bytes. If the data in
the message buffer is terminated, the
MSG_END (0031H) bit will set high.
The test mode of the decoder is selected by setting the TS pin low at any time. In the test
mode, the RF control outputs BS1 and BS3 are
constantly set high, but BS2 is set low. After the
TS pin is set high the decoder exits the test
mode.
Bit7
Bit6
Sync. State
Bit5
Bit4
Call Address
Bit3
Bit2
Dup. Call
Valid Address
Bit1
Bit0
Function Code
Bit5
Bit4
Call Address
RIC A
RIC B
RIC C
RIC D
RIC E
RIC F
Interrupt indication
38
Preliminary
Out-of-range indication
HT9580
Receiver Establishment
Time TBS1
512 bps
1200/2400 bps
7.81ms
53.33ms
15.63ms
6.67ms
31.25ms
13.33ms
62.50ms
26.67ms
Quick Charge
Adjustment Time TBS2
The HT9580 provides a duplicate call suppression with time-out facility, to identify duplicate call reception. In the display pager
mode, duplicate call indication is achieved
only via the mC interface. A call is assumed to
be a duplicate if its latest address and function bit setting is equal to the previous received call within the time interval defined by
SPF06, SPF07.
Receiver, Quick charge and PLL signal control
SPF00 SPF01
Option
512 bps
1200/2400 bps
7.81ms
1.67ms
15.63ms
6.67ms
15.63ms
11.67ms
19.53ms
13.33ms
Option
SPF02 SPF03
Option
512 bps
1200/2400 bps
SPF04 SPF05
0ms
0ms
31.25ms
26.67ms
46.87ms
40.00ms
62.50ms
53.33ms
D a ta In
T
B S 1
B S 1
T
B S 2
B S 2
T
B S 3
B S 3
39
Preliminary
memory is mapped
001AH~002EH.
HT9580
to
the
address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
001AH
ENA
A00
A01
A02
A03
A04
A05
A06
001BH
A07
A08
A09
A10
A11
A12
A13
A14
001CH
A15
A16
A17
FA2
FA1
FA0
001DH
ENB
B00
B01
B02
B03
B04
B05
B06
001EH
B07
B08
B09
B10
B11
B12
B13
B14
001FH
B15
B16
B17
FB2
FB1
FB0
0020H
ENC
C00
C01
C02
C03
C04
C05
C06
0021H
C07
C08
C09
C10
C11
C12
C13
C14
0022H
C15
C16
C17
FC2
FC1
FC0
0023H
END
D00
D01
D02
D03
D04
D05
D06
0024H
D07
D08
D09
D10
D11
D12
D13
D14
0025H
D15
D16
D17
FD2
FD1
FD0
0026H
ENE
E00
E01
E02
E03
E04
E05
E06
0027H
E07
E08
E09
E10
E11
E12
E13
E14
0028H
E15
E16
E17
FE2
FE1
FE0
0029H
ENF
F00
F01
F02
F03
F04
F05
F06
002AH
F07
F08
F09
F10
F11
F12
F13
F14
002BH
F15
F16
F17
FF2
FF1
FF0
002CH
SPF00
SPF01
SPF02
SPF03
SPF04
SPF05
SPF06
SPF07
002DH
SPF08
SPF09
SPF10
SPF11
SPF12
SPF13
SPF14
SPF15
002EH
SPF16
SPF17
SPF18
SPF19
40
Preliminary
HT9580
SPF10
The following features can be selected by appropriate programming of the specially programmed function bits:
SPF00~SPF01
SPF11
SPF12
SPF13
SPF14
Connected
Crystal (Hz)
Baud Rate
(bps)
512
32768
76.8k
512
76.8k
1200
76.8k
2400
153.6k
512
153.6k
1200
153.6k
2400
SPF04~SPF05
SPF06~SPF07
SPF16~SPF19
SPF08~SPF09
41
Preliminary
HT9580
CPU Core
bus memory. In the low state the data bus has
valid data from the mC to be stored at the addressed memory location.
The HT9580 is a high performance pager controller specifically designed for use in new generation radio pagers. It is based on the M6502
core. The 6502 Microprocessor offers complete
hardware and software capability with existing
6500 series of products as well as significant enhancements.
Parameter
Description
tcyc
tad
tah
tdis
tdih
tdod
tdoh
tdenbd
twed
tsyd
tsyh
tvd
tvh
tsos
tsoh
trds
trdh
tress
tresh
42
Preliminary
tc
HT9580
y c
C L K
ta
d
A D D R
ta
R D
A d d re s s
td
W R A d d re s s
is
R E A D
D A T A I
td
ih
td
o d
W R IT E
D A T A O
td
td
e n b d
o h
D A T A E N
tw
W E _ N
ts
ts
y h
, tv
y d
, tv
e d
S Y N C ,
V P B
R D Y ,
R E S _ N
S O B _ N
trd h , tre
trd s , tre
s s
, ts
s h
, ts
o h
o s
The Accumulator is a general purpose 8-bit register which stores the results of most arithmetic and logic operations. In addition, the
accumulator usually contains one of the two
data words used in these operations.
Index register
There are two 8-bit Index Register (X and Y)
which may be used to count program steps or to
provide an index value to be used in generating
an effective address. When executing an instruction which specifies indexed addressing,
the mC fetches the opcode and the base address,
and modifies the address by adding the index
register to it prior to performing the desired operation. Pre- or post-indexing of indirect addresses is possible.
Program counter
The 16-bit program counter register provides
the addresses which step the mC through sequential program instructions. Each time the
HT9580 fetches an instruction from the program memory, the lower byte of the program
counter (PCL) is placed on the low-order bits of
the address bus and the higher byte of the program counter (PCH) is placed on the high-order
43
Preliminary
Status register
I: IRQ
1=true
1=negative
0
A c c u m u la to r A
0
In d e x R e g is te r Y
0
X
In d e x R e g is te r X
P C H
P C L
7
0
1=BRK, 0=IRQ
N: Negative
1=true
V: Overflow
1=disable
B: BRK command
1=true
D: Decimal mode
B
1=true
Z: Zero
1 5
Note: C: Carry
Stack pointer
1 5
HT9580
P ro g ra m
C o u n te r P C
0
S
S ta c k P o in te r
T h e w id th o f th e c o r r e s p o n d in g r e g is te r s
44
Preliminary
HT9580
Interrupt System
the interrupt vector from locations FFFA (low
byte) and FFFB (high byte), thereby transferring program control to the non-maskable interrupt routine. The NMI is generated from
data ready interrupt or battery fail interrupt
flag (0006H). However, it should be noted that
this is an edge-sensitive input. As a result, another interrupt will occur if there is another
negative-going transition and the program has
not returned. Also, no interrupt will occur if
NMI is low and a negative-going edge has not
occurred since the last non-maskable interrupt.
The NMI signal going low causes 3 bytes of information to be pushed onto the stack before
jumping to the interrupt handler. The first byte
is the high byte in the program counter. The
second byte is the program counter low byte.
The third byte is the status register value.
These values are used to return to its original
state prior to NMI interrupt.
Preliminary
HT9580
Addressing modes
The M6502 supports fifteen (15) addressing
modes, shown in table below. In interpreting
this table you should note that:
Mode
Description
IMP
ACC
IMM
ZPG
ZERO PAGE: The first 256 RAM locations (0000H~00FFH) are used for fast access
and small code size. The upper 8-bit of the address are always zero. [data=(00, IAL)]
ZPX
ZERO PAGE INDIRECT X: The X register is added to the byte following the opcode to
give a new zero page address. Note that the upper 8-bit of the address are always zero.
[data=(00, IAL+X)]
ZPY
ZERO PAGE INDIRECT Y: The Y register is added to the byte following the opcode to
give a new zero page address. Note that the upper 8-bit of the address are always zero.
Only the LDX and the STX opcodes use this mode. [data=(00, IAL+Y)]
ABS
ABSOLUTE: The two bytes following the opcode give the absolute address of the data.
[data=(BAH, BAL)]
ABX
ABSOLUTE X: The X register is added to the two bytes following the opcode to produce
a new 16-bit address. {data=[(BAH, BAL)]+X}
ABY
ABSOLUTE Y: The Y register is added to the two bytes following the opcode to produce
a new 16-bit address. {data=[(BAH, BAL)]+Y}
ABI
ABSOLUTE INDIRECT: The two bytes following the opcode are used as a pointer to
memory. Only the JMP opcode uses this mode. [data=(BAH, BAL)]
AIX
INDEXED ABSOLUTE INDIRECT X: The two bytes following the opcode are added to
the X register to yield a new 16-bit address. The contents of this address and the following one are used as an indirect address. Only the JMP opcode uses this mode.
{data=[(BAH, BAL+X+1), (BAH, BAL+X)]}
IND
INDIRECT: The byte following the opcode is used as a pointer to the zero page. The
contents of this address and the following one are used as the address to finally access
the data. {data=[(IAL+1), (IAL)]}
46
Preliminary
HT9580
Mode
Description
INX
INDIRECT X: The byte following the opcode is added to the X register to produce a new
zero page address. The contents of this address and the following one are used as the
address to finally access the data. Note that when the X register is added to the byte
following the opcode, the upper byte of the address is always zero. {data=[(00,
IAL+X+1), (00, IAL+X)]}
INY
INDIRECT Y: The byte following the opcode is a zero page address. The contents of
this location and the next one produce a 16-bit address which is then added to the Y
register to finally obtain the data. {data=<[(00, IAL+1), (00, IAL)]+Y>}
REL
RELATIVE: The byte following the opcode is added in 2's complement fashion to the
PC. The byte is sign extended. Used by branching instructions.
47
Preliminary
HT9580
Application Circuits
OSC1, OSC2 require an external resistor
V
(1 .5 V )
D D
4 7 0 m H
+
+
S c h o ttk y D io d e
L X
2 2 m F
O U T
D C /D C
V S S
3 V
2 2 m F
R H 5 R 3 0 2
S la v e
L C D
D is p la y
H o lte k
P a g e r
M a s te r
L C D
D r iv e r
H T 9 3 L C 4 6
L C D
D 0 ~
L C D
R E S
L C D
L C D
L C D
L C D
V D D
_ E
D 7
_ R
E T
_ C
_ C
_ C
_ A
S 0 (M a s te r)
S 1 ( S la v e )
B A F
B Z
4 9
4 6
4 7
4 8
4 4
6 6
D A _ O U T
P B 4
P B 1
P B 2
P B 3
X 2
X 1
S W 1
7 2
S W 2
7 1
S W 3
7 0
V
O S C 1
P A 3 ~ P A 5
O S C 2
T M R 1
T S
P A 0
H T 9 5 8 0
0 .1 m F
5 3
5 4
1 .5 V
P _ M O D E
P A 2
P S E N
R E S E T
P C 0
A 0 ~ A 1 3
R A 1 4 ~ R A 1 7
P C 1
D 0 ~ D 7
M A S K _ C E
6 8 0 W
S R A M _ C E
M o to r
R F
R e c e iv e r
6 1
V S S
5 9
5 1 0 W
5 5
0 .1 m F
6 0
7 9
8 0
0 .1 m F
B u z z e r
7 6 .8 k H z
7 7
V
D D
7 6
N o rm a l T y p e
2 6
R o m le s s
D 0 ~ D 7
2 0
A 0 ~ A 1 5
C E
O E
1 .5 V
L a m p
6 2
5 8
D 0 ~ D 7
A 0 ~ A 1 5
7 3
V D D
6 3
P A 1
D D
1 0 0 k W
6 4
1 .5 V
D D
C S
E E P R O M S K
D I
D O
V S S
6 5
B S 1
B S 2
B S 3
D I
B A L
R S S I
P B 0
P B 5 ~ P B 7
1 k W
1 .5 V
1 , 2 5 , 5 6
R /W
M
V S S
2 7 , 5 7 , 7 8
48
O E
H T 2 7 L C 5 1 2
P ro g ra m
R O M
A 0 ~ A 1 7
D 0 ~ D 7
1 8
1 7
1 6
1 9
R O M C E
M a s k R A M
R A M C E
W E
O E
N o te : T h e e x te r n a l m e m o r y is o p tio n a l
Preliminary
HT9580
OSC1, OSC2 do not require a resistor. The OSC1 clock comes from an internal pad DF only
V
D D
(1 .5 V )
S c h o ttk y D io d e
4 7 0 m H
+
+
L X
2 2 m F
O U T
D C /D C
V S S
3 V
2 2 m F
1 .5 V
R H 5 R 3 0 2
S la v e
1 , 2 5 , 5 6
L C D
D is p la y
H o lte k
P a g e r
M a s te r
L C D
D r iv e r
H T 9 3 L C 4 6
L C D
D 0 ~
L C D
R E S
L C D
L C D
L C D
L C D
V D D
_ E
D 7
_ R
E T
_ C
_ C
_ C
_ A
S 0 (M a s te r)
S 1 ( S la v e )
B A F
6 6
S W 1
7 2
S W 2
7 1
7 0
S W 3
V
D A _ O U T
P B 4
P B 1
P B 2
P B 3
X 2
X 1
4 4
P B 0
P B 5 ~ P B 7
D F
P A 3 ~ P A 5
O S C 1
P A 0
H T 9 5 8 0
0 .1 m F
5 3
5 4
1 .5 V
P A 2
P S E N
R E S E T
0 .1 m F
6 0
7 9
8 0
B u z z e r
0 .1 m F
7 6 .8 k H z
1 5 3 .6 k H z
V
D D
N o rm a l T y p e
2 6
R o m le s s
D 0 ~ D 7
2 0
A 0 ~ A 1 3
R A 1 4 ~ R A 1 7
P C 0
P C 1
A 0 ~ A 1 5
C E
M A S K _ C E
R /W
M
V S S
2 7 , 5 7 , 7 8
49
O E
H T 2 7 L C 5 1 2
P ro g ra m
R O M
A 0 ~ A 1 7
D 0 ~ D 7
6 8 0 W
M o to r
5 1 0 W
5 5
O E
S R A M _ C E
L a m p
V S S
5 9
D 0 ~ D 7
1 .5 V
1 k W
P _ M O D E
A 0 ~ A 1 5
7 3
6 1
P A 1
D D
1 0 0 k W
R F
R e c e iv e r
5 8
O S C 2
T M R 1
T S
V D D
6 2
6 3
1 .5 V
B Z
4 9
4 6
4 7
4 8
6 4
D D
C S
E E P R O M S K
D I
D O
V S S
6 5
B S 1
B S 2
B S 3
D I
B A L
R S S I
D 0 ~ D 7
1 8
1 7
1 6
1 9
R O M C E
M a s k R A M
R A M C E
W E
O E
N o te : T h e e x te r n a l m e m o r y is o p tio n a l
Preliminary
HT9580
(1 .5 V )
D D
4 7 0 m H
+
+
S c h o ttk y D io d e
L X
2 2 m F
O U T
D C /D C
V S S
3 V
1 , 2 5 , 5 6
S la v e
L C D
D is p la y
H o lte k
P a g e r
M a s te r
L C D
D r iv e r
H T 9 3 L C 4 6
1 .5 V
2 2 m F
R H 5 R 3 0 2
L C D
D 0 ~
L C D
R E S
L C D
L C D
L C D
L C D
V D D
_ E
D 7
_ R
E T
_ C
_ C
_ C
_ A
S 0 (M a s te r)
S 1 ( S la v e )
K
S I
O
Y
S I
B A F
B Z
4 9
4 6
4 7
4 8
D A _ O U T
P B 4
P B 1
P B 2
P B 3
4 4
6 6
X 2
X 1
S W 1
7 2
S W 2
7 1
S W 3
7 0
V
D D
1 0 0 k W
7 3
0 .1 m F
5 3
5 4
1 .5 V
O S C 1
P A 3 ~ P A 5
O S C 2
T M R 1
T S
P A 0
H T 9 5 8 0
P A 2
P _ M O D E
5 8
V S S
6 1
5 9
5 1 0 W
5 5
0 .1 m F
6 0
7 9
8 0
0 .1 m F
B u z z e r
7 6 .8 k H z
7 7
V
D D
7 6
N o rm a l T y p e
2 6
R o m le s s
D 0 ~ D 7
A 0 ~ A 1 5
P S E N
R E S E T
D 0 ~ D 7
2 0
A 0 ~ A 1 5
C E
O E
A 0 ~ A 1 3
R A 1 4 ~ R A 1 7
P C 0
P C 1
M A S K _ C E
S R A M _ C E
R /W
M
V S S
2 7 , 5 7 , 7 8
50
O E
H T 2 7 L C 5 1 2
P ro g ra m
R O M
A 0 ~ A 1 7
D 0 ~ D 7
6 8 0 W
M o to r
6 2
P A 1
1 .5 V
L a m p
R F
R e c e iv e r
F le x TM
D e c o d e r
6 3
1 .5 V
D D
C S
E E P R O M S K
D I
D O
V S S
6 4
P B 0
P B 5 ~ P B 7
1 k W
S C
M O
M IS
S R D
R S
V D D
6 5
S S
D 0 ~ D 7
1 8
1 7
1 6
1 9
R O M C E
M a s k R A M
R A M C E
W E
O E
N o te : T h e e x te r n a l m e m o r y is o p tio n a l
Preliminary
HT9580
No change
Updated
The number of bytes column gives the number of bytes for the opcode.
The number of cycles column gives the number of clock cycles for the opcode. (A+b indicates one additional cycle when a branch is taken within the same page, or 2 cycles if the branch is to a different
page.)
The last column are the description or brief descriptions of the opcode.
The operator notation is as follows:
=>
assignment
2s complement add
2s complement subtract
Bitwise OR
&
Bitwise AND
Bitwise exclusive OR
<<
Left rotate
>>
Right rotate
<
Left shift
>
Right shift
Accumulator
Carry flag
X index register
Y index register
Stack pointer
Memory
51
Preliminary
Name
Flags
Opcode
Addr
Mode
N V E B D I Z C
No.
Bytes
No.
Cyc.
HT9580
Description
ADC
69
IMM
+ +
+ +
ADC
65
ZPG
+ +
+ +
ADC
75
ZPX
+ +
+ +
ADC
6D
ABS
+ +
+ +
ADC
7D
ABX
+ +
+ +
ADC
79
ABY
+ +
+ +
ADC
72
IND
+ +
+ +
ADC
61
IDX
+ +
+ +
ADC
71
IDY
+ +
+ +
AND
29
IMM
A&M=>A
AND A with M
AND
25
ZPG
A&M=>A
AND A with M
AND
35
ZPX
A&M=>A
AND A with M
AND
2D
ABS
A&M=>A
AND A with M
AND
3D
ABX
A&M=>A
AND A with M
AND
39
ABY
A&M=>A
AND A with M
AND
32
IND
A&M=>A
AND A with M
AND
21
IDX
A&M=>A
AND A with M
AND A with M
AND
31
IDY
A&M=>A
ASL
0A
ACC
+ +
ASL
06
ZPG
+ +
ASL
16
ZPX
+ +
ASL
0E
ABS
+ +
ASL
1E
ABX
+ +
BBR0
0F
REL
5+b
BBR1
1F
REL
5+b
BBR2
2F
REL
5+b
BBR3
3F
REL
5+b
BBR4
4F
REL
5+b
BBR5
5F
REL
5+b
BBR6
6F
REL
5+b
BBR7
7F
REL
5+b
BBS0
8F
REL
5+b
BBS1
9F
REL
5+b
BBS2
AF
REL
5+b
BBS3
BF
REL
5+b
BBS4
CF
REL
5+b
52
Preliminary
Name
Opcode
Addr
Mode
Flags
N V E B D I Z C
No.
Bytes
HT9580
No.
Cyc.
Description
BBS5
DF
REL
5+b
BBS6
EF
REL
5+b
BBS7
FF
REL
5+b
BCC
90
REL
2+b
BCS
B0
REL
2+b
BEQ
F0
REL
2+b
BIT
89
IMM
7 6
BIT
24
ZPG
7 6
BIT
34
ZPX
7 6
BIT
2C
ABS
7 6
BIT
3C
ABX
7 6
BMI
30
REL
2+b
BNE
D0
REL
2+b
BPL
10
REL
2+b
BRA
80
REL
2+b
BRK
00
IMP
BVC
50
REL
2+b
BVS
70
REL
2+b
CLC
18
IMP
C<=0
CLD
D8
IMP
D<=0
CLI
58
IMP
I<=0
CLV
B8
IMP
V<=0
CMP
C9
IMM
+ +
A-M=>N, Z, C
CMP
C5
ZPG
+ +
A-M=>N, Z, C
CMP
D5
ZPX
+ +
A-M=>N, Z, C
CMP
CD
ABS
+ +
A-M=>N, Z, C
CMP
DD
ABX
+ +
A-M=>N, Z, C
CMP
D9
ABY
+ +
A-M=>N, Z, C
CMP
D2
IND
+ +
A-M=>N, Z, C
CMP
C1
INX
+ +
A-M=>N, Z, C
CMP
D1
INY
+ +
A-M=>N, Z, C
CPX
E0
IMM
+ +
X-M=>N, Z, C
CPX
E4
ZPG
+ +
X-M=>N, Z, C
CPX
EC
ABS
+ +
X-M=>N, Z, C
CPY
C0
Imm
+ +
Y-M=>N, Z, C
CPY
C4
ZPG
+ +
Y-M=>N, Z, C
53
Preliminary
Flags
Opcode
Addr
Mode
CPY
CC
ABS
DEC
C6
ZPG
Name
HT9580
No.
Bytes
No.
Cyc.
+ +
Y-M=>N, Z, C
M<=M -1
N V E B D I Z C
Description
DEC
D6
ZPX
M<=M -1
DEC
CE
ABS
M<=M -1
DEC
DE
ABX
M<=M -1
DEC
3A
ACC
A<=A -1
DEX
CA
IMP
X<=X -1
DEY
88
IMP
Y<=Y -1
EOR
49
IMM
A<=A^M
EOR
45
ZPG
A<=A^M
EOR
55
ZPX
A<=A^M
EOR
4D
ABS
A<=A^M
EOR
5D
ABX
A<=A^M
EOR
59
ABY
A<=A^M
EOR
52
IND
A<=A^M
EOR
41
INX
A<=A^M
EOR
51
INY
A<=A^M
INC
E6
ZPG
M<=M+1
INC
F6
ZPX
M<=M+1
INC
EE
ABS
M<=M+1
INC
FE
ABX
M<=M+1
INC
1A
ACC
A<=A+1
INX
E8
IMP
X<=X+1
INY
C8
IMP
Y<=Y+1
JMP
4C
ABS
PC<M
JMP
6C
ABI
PC<=(M)
JMP
7C
AIX
PC<=(M)
JSR
20
ABS
LDA
A9
IMM
A<=M
LDA
A5
ZPG
A<=M
LDA
B5
ZPX
A<=M
LDA
AD
ABS
A<=M
LDA
BD
ABX
A<=M
LDA
B9
ABY
A<=M
LDA
B2
IND
A<=M
LDA
A1
INX
A<=M
54
Preliminary
Name
Opcode
Addr
Mode
Flags
N V E B D I Z C
No.
Bytes
HT9580
No.
Cyc.
Description
LDA
B1
INY
A<=M
LDX
A2
IMM
X<=M
LDX
A6
ZPG
X<=M
LDX
B6
ZPY
X<=M
LDX
AE
ABS
X<=M
LDX
BE
ABY
X<=M
LDY
A0
IMM
Y<=M
LDY
A4
ZPG
Y<=M
LDY
B4
ZPX
Y<=M
LDY
AC
ABS
Y<=M
LDY
BC
ABX
Y<=M
LSR
4A
ACC
+ +
LSR
46
ZPG
+ +
LSR
56
ZPX
+ +
LSR
4E
ABS
+ +
LSR
5E
ABX
+ +
NOP
EA
IMP
No operation
ORA
09
IMM
A<=A|M
ORA
05
ZPG
A<=A|M
ORA
15
ZPX
A<=A|M
ORA
0D
ABS
A<=A|M
ORA
1D
ABX
A<=A|M
ORA
19
ABY
A<=A|M
ORA
12
IND
A<=A|M
ORA
01
INX
A<=A|M
ORA
11
INY
A<=A|M
PHA
48
IMP
Push A on stack
PHP
08
IMP
PHX
DA
IMP
Push X on stack
PHY
5A
IMP
Push Y on stack
PLA
68
IMP
PLP
28
IMP
PLX
FA
IMP
PLY
7A
IMP
RMB0
07
ZPG
RMB1
17
ZPG
From Stack
55
Preliminary
Flags
Opcode
Addr
Mode
RMB2
27
ZPG
RMB3
37
ZPG
RMB4
47
ZPG
RMB5
57
ZPG
RMB6
67
ZPG
Name
HT9580
No.
Bytes
No.
Cyc.
N V E B D I Z C
Description
RMB7
77
ZPG
ROL
2A
ACC
+ +
ROL
26
ZPG
+ +
ROL
36
ZPX
+ +
ROL
2E
ABS
+ +
ROL
3E
ABX
+ +
ROR
6A
ACC
+ +
ROR
66
ZPG
+ +
ROR
76
ZPX
+ +
ROR
6E
ABS
+ +
ROR
7E
ABX
+ +
RTI
40
IMP
From Stack
RTS
60
IMP
PC<=from stack
SBC
E9
IMM
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
E5
ZPG
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
F5
ZPX
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
ED
ABS
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
FD
ABX
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
F9
ABY
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
F2
IND
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
E1
INX
+ +
+ +
A<=A-M-C (C is a borrow)
SBC
F1
INY
+ +
+ +
A<=A-M-C (C is a borrow)
SEC
38
IMP
C<=1
SED
F8
IMP
D<=1
SEI
78
IMP
I<=1
SMB0
87
ZPG
SMB1
97
ZPG
SMB2
A7
ZPG
SMB3
B7
ZPG
SMB4
C7
ZPG
SMB5
D7
ZPG
56
Preliminary
Flags
Opcode
Addr
Mode
SMB6
E7
ZPG
SMB7
F7
ZPG
STA
85
ZPG
STA
95
ZPX
STA
8D
ABS
STA
9D
ABX
STA
99
ABY
STA
81
INX
STA
91
INY
STX
86
ZPG
Name
HT9580
No.
Bytes
No.
Cyc.
M<=A
M<=A
M<=A
M<=A
M<=A
M<=A
M<=A
M<=X
N V E B D I Z C
Description
STX
96
ZPY
M<=X
STX
8E
ABS
M<=X
STY
84
ZPG
M<=Y
STY
94
ZPX
M<=Y
STY
8C
ABS
M<=Y
STZ
64
ZPG
M<=0
STZ
74
ZPX
M<=0
STZ
9C
ABS
M<=0
STZ
9E
ABX
M<=0
TAX
AA
IMP
X<=A
TAY
A8
IMP
Y<=A
TRB
14
ZPG
M<=!A&M, Z=A&M
TRB
1C
ABS
M<=!A&M, Z=A&M
TSB
04
ZPG
M<=A|M, Z=A&M
TSB
0C
ABS
M<=A|M, Z=A&M
TSX
BA
IMP
X<=S
TXA
8A
IMP
A<=X
TXS
9A
IMP
S<=X
TYA
98
IMP
A<=Y
57
Preliminary
HT9580
Opcode Matrix
The table below shows the matrix of M6502 opcodes:
LSB
MSB
BRK
imp
ORA
inx
BPL
rel
ORA
iny
JSR
abs
AND
inx
BMI
rel
AND
iny
RTI
imp
EOR
inx
BVC
rel
EOR
iny
RTS
imp
ADC
inx
BVS
rel
ADC
iny
BRA
rel
STA
inx
BCC
rel
STA
iny
LDY
imm
ASL
acc
TSB
abs
ORA
abs
ASL
abs
BR0
zpg
ORA
aby
INC
acc
TRB
abs
ORA
abx
ASL
abx
BR1
zpg
PLP
imp
AND
imm
ROL
acc
BIT
abs
AND
abs
ROL
abs
BR2
zpg
RB3
zpg
SEC
imp
AND
aby
DEC
acc
BIT
abx
AND
abx
ROL
abx
BR3
zpg
LSR
zpg
RB4
zpg
PHA
imp
EOR
imm
LSR
acc
JMP
abs
EOR
abs
LSR
abs
BR4
zpg
EOR
zpx
LSR
zpx
RB5
zpg
CLI
imp
EOR
aby
PHY
imp
EOR
abx
LSR
abx
BR5
zpg
STZ
zpg
ADC
zpg
ROR
zpg
RB6
zpg
PLA
imp
ADC
imm
ROR
acc
JMP
abi
ADC
abs
ROR
abs
BR6
zpg
STZ
zpx
ADC
zpx
ROR
zpx
RB7
zpg
SEI
imp
ADC
aby
PLY
imp
JMP
aix
ADC
abx
ROR
abx
BR7
zpg
STY
zpg
STA
zpg
STX
zpg
SB0
zpg
DEY
imp
BIT
imm
TXA
imp
STY
abs
STA
abs
STX
abs
BS0
zpg
STA
ind
STY
zpx
STA
zpx
STX
zpy
SB1
zpg
TYA
imp
STA
aby
TXS
imp
STZ
abs
STA
abx
STZ
abx
BS1
zpg
LDA
inx
LDX
imm
LDY
zpg
LDA
zpg
LDX
zpg
SB2
zpg
TAY
imp
LDA
imm
TAX
imp
LDY
abs
LDA
abs
LDX
abs
BS2
zpg
BCS
rel
LDA
iny
LDA
ind
LDY
zpx
LDA
zpx
LDX
zpy
SB3
zpg
CLV
imp
LDA
aby
TSX
imp
LDY
abx
LDA
abx
LDX
aby
BS3
zpg
CPY
imm
CMP
inx
CPY
zpg
CMP
zpg
DEC
zpg
SB4
zpg
INY
imp
CMP
imm
DEX
imp
CPY
abs
CMP
abs
DEC
abs
BS4
zpg
BNE
rel
CMP
iny
CMP
zpx
DEC
zpx
SB5
zpg
CLD
imp
CMP
aby
PHX
imp
CMP
abx
DEC
abx
BS5
zpg
CPX
imm
SBC
inx
SBC
zpg
INC
zpg
SB6
zpg
INX
imp
SBC
imm
NOP
imp
SBC
abs
INC
abs
BS6
zpg
BEQ
rel
SBC
iny
SBC
zpx
INC
zpx
SB7
zpg
SED
imp
SBC
aby
PLX
imp
SBC
abx
INC
abx
BS7
zpg
ORA
ind
AND
ind
TSB
zpg
ORA
zpg
ASL
zpg
RB0
zpg
PHP
imp
ORA
imm
TRB
zpg
ORA
zpx
ASL
zpx
RB1
zpg
CLC
imp
BIT
zpg
AND
zpg
ROL
zpg
RB2
zpg
BIT
zpx
AND
zpx
ROL
zpx
EOR
zpg
EOR
ind
ADC
ind
CMP
ind
CPX
zpg
SBC
ind
58
CPX
abs
Preliminary
HT9580
Application Note
The LCD_CTRL and LCD_CMD registers are used to control the LCD Drivers. The following example shows how to initiate the MC141803 LCD driver.
The following bit settings are used for the LCD_CTRL register.
; ************
; * LCD CONTROL *
; ************
chip1
SET
chip0
SET
clk
SET
cmod
SET
; enable/disable LCD_CL
cs1
SET
cs0
SET
a0
SET
rw
SET
LCDCT
EQU 17h
The following three macros define three different modes including LCD COMMAND WRITE,
LCD DATA WRITE and LCD DATA READ modes.
; ***************************
; LCDM COMMAND MODE
; LCD_A0=0 command mode
; LCD_WRB=0 write mode
; COMMAND store to ACC
; ***************************
LCD_C
MACRO
RMB
a0, LCDCT
RMB
rw, LCDCT
STA
LCDCM
SMB
rw, LCDCT
ENDM
59
Preliminary
HT9580
; ***************************
; LCDM WRITE MODE
; LCD_A0=1 data mode
; LCD_WRB=0 write mode
; DATA store to ACC
; ***************************
LCD_W
MACRO
SMB
a0, LCDCT
RMB
rw, LCDCT
STA
LCDCM
RMB
a0, LCDCT
SMB
rw, LCDCT
ENDM
; ***************************
; LCDM READ MODE
; LCD_A0=1 data mode
: LCD_WRB=1 read mode
; DATA store to ACC
; ***************************
LCD_R
MACRO
SMB
a0, LCDCT
SMB
rw, LCDCT
LDA
LCDCM
RMB
a0, LCDCT
ENDM
60
Preliminary
HT9580
#01011001B
STA
LCDCT
LDA
#76H
; normal operation
LCD_C
LDA
#7BH
LCD_C
LDA
#7FH
LCD_C
LDA
#2BH
LCD_C
LDA
#2DH
LCD_C
LDA
#31H
LCD_C
LDA
#2FH
LCD_C
LDA
#33H
LCD_C
LDA
#29H
; set display on
LCD_C
LDA
#36H
LCD_C
LDA
#0H
LCD_W
LDA
#04H
LCD_C
LDA
#37H
LCD_C
LDA
#0H
LCD_W
LDA
#3DH
Preliminary
HT9580
LCD_C
LDA
#0
; set page 0
LCD_C
LDA
#23H
LCD_C
LDA
#83H
LCD_C
RTS
62
Preliminary
HT9580
63