$ Power Supply Design

CARMA Correlator: Power Supply Design
D. W. Hawkins (dwh@ovro.caltech.edu)
Revision: 1.56
December 4, 2006
Contents
1 Introduction
2 Basic circuit components review
2.1 Capacitor . . . . . . . . . . . . . .
2.2 Inductor . . . . . . . . . . . . . . .
2.3 Inductor-Capacitor (LC) . . . . . .
2.4 Resistor-Inductor-Capacitor (RLC)
2.5 Capacitor voltage ripple . . . . . .
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4
4
8
11
14
18
3 Buck and synchronous buck converters

3.1 Topology . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Continuous-mode and discontinuous-mode operation
3.3 RMS current analysis . . . . . . . . . . . . . . . . .
3.4 Synchronous buck operation . . . . . . . . . . . . . .
3.5 Output capacitance selection . . . . . . . . . . . . .
3.6 Input capacitance selection . . . . . . . . . . . . . .
3.7 MOSFET selection . . . . . . . . . . . . . . . . . . .
3.7.1 MOSFET and controller parameters . . . . .
3.7.2 Maximum junction temperature . . . . . . .
3.7.3 On-resistance temperature dependence . . . .
3.7.4 High-side MOSFET selection . . . . . . . . .
3.7.5 Low-side MOSFET selection . . . . . . . . .
3.8 Buck and synchronous buck design . . . . . . . . . .
3.9 Multi-phase synchronous buck converters . . . . . .
3.10 Eciency . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Reducing body-diode conduction loss . . . . . . . . .
3.12 Load-dependent output voltage . . . . . . . . . . . .
3.13 Control loop compensation . . . . . . . . . . . . . .
3.13.1 Voltage-mode control . . . . . . . . . . . . .
3.13.2 Current-mode control . . . . . . . . . . . . .
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22
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27
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39
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41
41
47
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4 Linear regulators
51
5 DDR termination regulators
52
6 Design examples
6.1 Linear Technology LTC1624 buck converter; 12V to 5V at 3A . . . . . . . . . . . .
6.2 Linear Technology LTC1625 synchronous buck converter; 12V to 5V at 3A . . . .
6.3 Fairchild (AN-6005) FAN5069 synchronous buck; 12V to 1.4V at 25A . . . . . . .
6.4 Altera Stratix II DSP Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 LTC1778 1.2V supply: Design; 16V to 1.2V at 8A . . . . . . . . . . . . . .
6.4.2 LTC1778 1.2V supply: Simulation . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 LTC1778 1.2V supply: Power Analysis . . . . . . . . . . . . . . . . . . . . .
6.4.4 LTC1778 1.2V supply: Measurements . . . . . . . . . . . . . . . . . . . . .
6.4.5 LTC1778 3.3V and 5V supplies . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Monolithic converters (integrated MOSFETs) . . . . . . . . . . . . . . . . . . . . .
6.5.1 Linear Technology converters . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2 Linear Technology LTC3414; 3.3V to 1.2V at 4A . . . . . . . . . . . . . . .
6.5.3 Linear Technology LTC3418; 3.3V to 1.2V at 8A . . . . . . . . . . . . . . .
6.5.4 Texas Instruments converters . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.5 Texas Instruments TPS54610; 1.2V at 4A . . . . . . . . . . . . . . . . . . .
6.5.6 Texas Instruments TPS54910; 1.2V at 8A . . . . . . . . . . . . . . . . . . .
6.5.7 Texas Instruments TPS54610EVM-192; 5V to 3.3V at 6A measurements . .
6.5.8 Texas Instruments TPS54910EVM-213; 3.3V to 1.8V at 9A measurements .
6.5.9 Texas Instruments TPS54010EVM-067; 3.3V to 1.5V at 13A measurements
6.5.10 Texas Instruments TPS54xxx; external synchronization . . . . . . . . . . .
6.6 Texas Instruments TPS40090 multi-phase buck converter . . . . . . . . . . . . . .
6.6.1 Single-phase 12V to 1.5V at 25A . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2 Four-phase 12V to 1.5V at 100A . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3 TPS40090EVM-001 measurements . . . . . . . . . . . . . . . . . . . . . . .
6.6.4 TPS40090EVM-001 compensation network . . . . . . . . . . . . . . . . . .
6.7 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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54
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84
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92
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104
107
112
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122
123
123
125
127
133
135
7 CARMA Board Power Supplies

7.1 CPU and System Controller Supplies . . . . . . . . . . . .
7.1.1 LTC4245 hot-swap controller . . . . . . . . . . . .
7.1.2 Core 1.2V at 8A, DDR-SDRAM VDD 2.5V at 8A
7.1.3 VTT 1.25V at 3A . . . . . . . . . . . . . . . . . .
7.1.4 System controller 1.5V at 500mA . . . . . . . . . .
7.2 Data Processing FPGA Supplies . . . . . . . . . . . . . .
7.2.1 LTC4215 hot-swap controller . . . . . . . . . . . .
7.2.2 Core voltage 1.2V at 60A . . . . . . . . . . . . . .
7.2.3 FPGA I/O voltages; 1.5V and 2.5V at 5A . . . . .
7.2.4 FPGA pre-driver supply; 3.3V at 1A . . . . . . . .
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136
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136
140
143
143
144
144
148
153
157
A Mean, RMS, and standard deviation
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158
CARMA Correlator
December 4, 2006
Introduction
The CARMA Digitizer/Correlator Board uses numerous power rails sourced from either the standard
compact PCI supply voltages of 3.3V, 5V, or 12V, or from the custom FPGA supply which is designed
to operate over the range 5V to 12V. Power rails generated on the board consist of processor core,
I/O, and DDR memory voltages, FPGA core and I/O voltages, PLL, digitizer, and RF voltages.
The low-current digital, or low-noise analog supplies are generated using linear regulators, while the
high-current digital supplies are generated using switch-mode power supplies (SMPS); in particular,
Buck or Synchronous Buck step-down converters. The manufacturer data sheets for the converters
often contain design equations without reference to their origin. This document contains derivations
of the design equations, circuit analysis, and simulation.
Background information on circuit components and switch-mode power supplies, can be found
online at Wikipedia, the free encyclopedia: http://en.wikipedia.org. Example keywords are;
Resistor, Electrical resistance, Capacitor, Capacitance, Inductor, Inductance, RC circuit, LC circuit,
RLC circuit, DC-DC converter, and Buck converter. Application notes that provide an overview of
DC-to-DC converter designs are [49, 62], while articles on powering FPGAs are [1315].
The circuit simulations contained in this document used the free LTSPICE/SwitcherCAD III
software available from Linear Technology; http://www.linear.com/company/software.jsp.
CARMA Correlator
December 4, 2006
Basic circuit components review
Buck and Synchronous Buck converters perform voltage translation by switching the input voltage
across an inductor and capacitor, producing a lower output voltage. The waveforms observed in
sections of the buck converter circuit are more easily understood after a review of some basic circuit
component properties.
2.1
Capacitor
A capacitors capacitance C is the ratio of stored charge Q to voltage V applied across the capacitor
terminals;
Q
V
(1)
1
1
1 Q2
CV 2 =
= VQ
2
2 C
2
(2)
C=
The energy stored in the capacitor is
E=
The current in a capacitor is related to the change in voltage via

I(t) =
dV (t)
dQ(t)
=C
dt
dt
and conversely the current in a capacitor produces a change in voltage via

1 t
V (t) =
I( )d
C 0
(3)
(4)
Figure 1 shows a capacitor driven by a pulsed voltage source, while Figure 2 shows the transient
response. The transient response is determined by (3), i.e., for the rising-edge of the voltage pulse,
dV /dt = 1V/0.5s = 2V/s, so I = 100F 2V/s = 200A. A load capacitance of several hundred
to a few thousand microfarads is not unreasonable in a power supply, so if the power-on voltage
source rises on the order of microseconds, a current pulse of several hundred amperes would be
generated, and would possibly result in connector damage (eg. pins on a compact PCI connector are
rated for 1A each, and the 5V rail has only 8 pins assigned). Buck converters generally incorporate
a soft-start feature that allows the supply to go into current-limit for a user-specied period during
power-up, the supply eectively becomes a current source, and increases the time taken to charge
the supply capacitance.
Figure 2 also models a digital I/O switching state into a capacitive load. For example, an interFPGA bus on the CARMA board operates at 1.5V, at a clock frequency of 125MHz, and each I/O
drives a load of approximately 5pF. An ideal eye-pattern generally has a rise or fall time of about
one-sixth the clock period, or about 1.3ns for this example, so dV /dt = 1.5V/1.3ns = 1.2V/ns, and
I = 5pF 1.2V/ns = 6mA per I/O pin. Assuming 200 I/O pins toggle high at the same time
(corresponding to about half the inter-FPGA bus and CPU bus I/Os), the required current is a
1.2A pulse lasting 1.3ns. This current is sourced from the FPGA I/O power decoupling capacitors,
and corresponds to dQ = I dt = 1.2A 1.3ns = 1.6nC of charge removed from the decoupling
capacitors. The drop in voltage on the decoupling capacitors is dV = dQ/C, if a 1-percent voltage
dip is specied, the required decoupling capacitance is C = 1.6nC/15mV = 100nF. An equivalent
calculation is to say that the I/O supply decoupling capacitance has to be 100 times larger than the
switched I/O load capacitance, i.e., C = 100 200 5pF = 100nF.
CARMA Correlator
December 4, 2006
V1
V1
C1
100F
PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)
.tran 0 10u 0 0.0001u
Figure 1: Basic capacitor circuit with a voltage source.
V(V1)
1.2V
1.1V
1.0V
0.9V
0.8V
Volts
0.7V
0.6V
0.5V
0.4V
0.3V
0.2V
0.1V
0.0V
I(C1)
250A
200A
150A
100A
Amps
50A
0A
-50A
-100A
-150A
-200A
-250A
0s
1s
2s
3s
4s
5s
6s
7s
8s
9s
10s
Figure 2: Capacitor response to voltage pulses. Current pulses occur when dV /dt = 0.
CARMA Correlator
December 4, 2006
Figure 3 shows a capacitor driven by a pulsed current source, while Figure 4 shows the transient
response. The transient response is determined by (4), i.e., the voltage on the capacitor is proportional to the integrated current. Each current pulse in Figure 4 consists of four states; linearly
increasing current, constant current, linearly decreasing current, and no current. The corresponding
voltage states are; a (positive) quadratic increase in voltage, a linear increase in voltage, a (negative) quadratic increase in voltage, constant voltage. The voltage on the capacitor can be solved by
integrating each of the current sections, or more simply by determining the area under each current
pulse. The height of the current pulse is 1A, the rising and falling edges last for 0.5s, while the
high time is 1s, resulting in an area of 1.5C. The total voltage increase for each pulse is then
V = 1.5C/100F = 15mV per pulse.
CARMA Correlator
December 4, 2006
V1
I1
C1
PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)
100F
.tran 0 10u 0 0.0001u
Figure 3: Basic capacitor circuit with a current source.
I(I1)
1.2A
1.0A
Amps
0.8A
0.6A
0.4A
0.2A
0.0A
V(V1)
50mV
40mV
Volts
30mV
20mV
10mV
0mV
0s
1s
2s
3s
4s
5s
6s
7s
8s
9s
10s
Figure 4: Capacitor response to current pulses. Voltage accumulates on the capactor for each pulse.
CARMA Correlator
2.2
December 4, 2006
Inductor
An inductors inductance L is the ratio of magnetic ux produced in the inductor for current I;
(5)
1
LI 2
2
(6)
L=
The energy stored in an inductor is
E=
The voltage across an inductor is related to the change in current via

V (t) = L
dI(t)
dt
and conversely the voltage across an inductor produces a change in current via

1 t
I(t) =
V ( )d
L 0
(7)
(8)
Figure 5 shows an inductor driven by a pulsed voltage source, while Figure 6 shows the transient
response. The transient response is determined by (8), i.e., the current through the inductor is
proportional to the integrated voltage. Each voltage pulse in Figure 6 consists of four states; linearly
increasing voltage, constant voltage, linearly decreasing voltage, and no voltage. The corresponding
current states are; a (positive) quadratic increase in current, a linear increase in current, a (negative)
quadratic increase in current, constant current. The current on the inductor can be solved by
integrating each of the voltage sections, or more simply by determining the area under each voltage
pulse. The height of the voltage pulse is 1V, the rising and falling edges last for 0.5s, while the
high time is 1s, resulting in an area of 1.5Vs. The total current increase for each pulse is then
I = 1.5Vs/1H = 1.5A per pulse.
Figure 7 shows a inductor driven by a pulsed current source, while Figure 8 shows the transient
response. The transient response is determined by (7), i.e., for the rising-edge of the current pulse,
dI/dt = 1A/0.5s = 2A/s, so V = 1H 2A/s = 2V.
A comparison of the capacitor circuits and responses with the inductor circuits and responses
shows the duality between the components.
CARMA Correlator
December 4, 2006
V1
V1
L1
1H
PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)

.tran 0 10u 0 0.0001u
Figure 5: Basic inductor circuit with a voltage source.
V(V1)
1.2V
1.0V
Volts
0.8V
0.6V
0.4V
0.2V
0.0V
I(L1)
5.0A
4.5A
4.0A
3.5A
Amps
3.0A
2.5A
2.0A
1.5A
1.0A
0.5A
0.0A
0s
1s
2s
3s
4s
5s
6s
7s
8s
9s
10s
Figure 6: Inductor response to voltage pulses. Current accumulates in the inductor for each pulse.
CARMA Correlator
December 4, 2006
V1
I1
L1
1H
PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)

.tran 0 10u 0 0.0001u
Figure 7: Basic inductor circuit with a current source.
I(I1)
1.2A
1.0A
Amps
0.8A
0.6A
0.4A
0.2A
0.0A
V(V1)
2.5V
2.0V
1.5V
1.0V
Volts
0.5V
0.0V
-0.5V
-1.0V
-1.5V
-2.0V
-2.5V
0s
1s
2s
3s
4s
5s
6s
7s
8s
9s
10s
Figure 8: Inductor response to current pulses. Current pulses occur when dI/dt = 0.
10
CARMA Correlator
2.3
December 4, 2006
Inductor-Capacitor (LC)
Figure 9 shows a SPICE LC circuit. The transfer function of the circuit for the output voltage is;
ZC (s)
V2 (s)
=
V1 (s)
ZL (s) + ZC (s)
1/(sC)
=
sL + 1/(sC)
1/(LC)
= 2
s + 1/(LC)
2
= 2 0 2
s + 0
(9)
1
0 =
.
LC
(10)
where 0 is the resonant frequency,
The s-domain response for a unity voltage-step input, and expansion into partial fractions, is
2
1
2 0 2
s s + 0
s
1
= 2
s s + 02
V2 (s) =
(11)
The inverse Laplace transform of this gives the time-domain response (the inverse is easily determined
using a table of inverse relations for each of the partial fraction components, eg. see [80])
v2 (t) = {1 cos(0 t)} u(t)
(12)
where u(t) is the Heaviside step function.

The transfer function of Figure 9 for the circuit current is;
I2 (s)
V2 (s)
=
V1 (s)
ZC (s)V1 (s)
1
=
sL + 1/(sC)
s/L
= 2
s + 1/(LC)
s
1
= 2
L s + 02
(13)
The s-domain response for a unity voltage-step input, is

s
1 1

L s s2 + 02

0
C
2
=
L s + 02
I2 (s) =
(14)
and the time-domain response is

i2 (t) =
C
sin(0 t) u(t)
L
(15)
11
CARMA Correlator
December 4, 2006
Figure 10 shows the transient response of the LC circuit to a unity voltage-step input. The plots
show the input voltage-step, output voltage, and output current. The circuit output waveforms ring
(resonate) at the resonant frequency of the circuit;
0 = 100krad/s
0
= 15.9kHz
f0 =
2
1
T0 =
= 62.8s
f0

C
= 10A
L
(16)
Since the capacitor voltage and current oscillate with a 90-degree phase dierence, no power is
dissipated, so the ringing does not dissipate.
Note that by default, a SwitcherCAD inductor has a 1m series resistance. This hidden resistor
creates an RLC circuit, so to remove it, open the hacks tab (Simulate, Control Panel, Hacks tab),
and check Always default inductors to Rser=0. The transient response amplitude is then constant
with time.
12
CARMA Correlator
December 4, 2006
L1
V1
V2
1H
V1
C1
100F
PWL(0 0 49u 0 50u 1)

.tran 0 500u 0 2.5u
V(V1)
Volts
1.2V
1.1V
1.0V
0.9V
0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
0.2V
0.1V
0.0V
2.0V
1.8V
1.6V
1.4V
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
Amps
Volts
Figure 9: LC circuit.
10A
8A
6A
4A
2A
0A
-2A
-4A
-6A
-8A
-10A
V(V2)
I(L1)
0s
50s
100s
150s
200s
250s
300s
350s
400s
450s
500s
Figure 10: LC unity voltage-step transient response.
13
CARMA Correlator
2.4
December 4, 2006
Resistor-Inductor-Capacitor (RLC)
Figure 11 shows a SPICE RLC circuit. The transfer function of the circuit for the output voltage
is;
ZC (s)
V2 (s)
=
V1 (s)
ZL (s) + ZR (s) + ZC (s)
1/(sC)
=
sL + R + 1/(sC)
1/(LC)
= 2
s + sR/L + 1/(LC)
02
= 2
s + 20 s + 02
02
=
2
(s + 0 ) + 02 (1 2 )
02
=
(s + 0 )2 + d2
(17)
where 0 is the undamped resonant or natural frequency, is the damping coecient

1 R 1
R
=
=
2 L 0
2
C
,
L
(18)
and d is the damped frequency

d = 0

1 2
(19)
The s-domain response for a unity voltage-step input, and expansion into partial fractions, is
1
s
1
=
s
1
=
s
1
=
s
V2 (s) =
02
(s + 0 )2 + d2
s + 20
(s + 0 )2 + d2
s + 0
0
d
2
2
(s + 0 ) + d
d (s + 0 )2 + d2
s+
(s + )2 + d2
d (s + )2 + d2
(20)
where is the damping coecent, and = 1/ is the time constant of the system, with
= 0 =
1 R
.
2 L
(21)
14
CARMA Correlator
December 4, 2006
The inverse Laplace transform of the s-domain response gives the time-domain response [80]

v2 (t) = 1 exp(t) cos(d t)

exp(t) sin(d t) u(t)
d

d
0
= 1
exp(t)
cos(d t)
sin(d t)
u(t)
d
0
0

0
2
exp(t)
1 cos(d t) sin(d t) u(t)
= 1
d

0
= 1
exp(t) [sin() cos(d t) cos() sin(d t)] u(t)
d

0
= 1
exp(t) sin(d t + ) u(t)
d
(22)
where

sin() = 1 2
cos() =
(23)
Equation 22 is the standard result for the step response of a second order system (p48 [6]).
The transfer function of Figure 11 for the circuit current is;
I2 (s)
V2 (s)
=
V1 (s)
ZC (s)V1 (s)
1
=
sL + R + 1/(sC)
s/L
= 2
s + sR/L + 1/(LC)
s/L
=
(s + 0 )2 + 0 (1 2 )
s
1
=
L (s + 0 )2 + d2
(24)
The s-domain response for a unity voltage-step input, is

s
1 1

L s (s + 0 )2 + d2
1 1
d
=
L d (s + 0 )2 + d2

C 0
d
L d (s + 0 )2 + d2
I2 (s) =
(25)
and the time-domain response is

i2 (t) =
C 0
exp(t) sin(d t) u(t)

L d
(26)
For R = 0, = 0, = 0, and = /2 rad, so (22) and (26) revert to the LC responses in (12) and
(15).
Figure 12 shows the transient response of the RLC circuit to a unity voltage-step input. Relative
to the LC response, the RLC circuit resonates at the damped frequency d 0 , and the amplitude
15
CARMA Correlator
December 4, 2006
drops o with a time constant , where

= 0.05
/2rad
d 100krad/s
fd = 15.9kHz
Td = 62.8s
(27)
= 2L/R = 200s
C 0
= 10A
L d
Note that by default, a SwitcherCAD inductor has a 1m series resistance. This hidden resistor
adds in series to the circuit R component, so to remove it, open the hacks tab (Simulate, Control
Panel, Hacks tab), and check Always default inductors to Rser=0.
16
CARMA Correlator
December 4, 2006
V1
R1
L1
0.01
1H
V2
V1
C1
100F
PWL(0 0 49u 0 50u 1)

.tran 0 1m 0 5u
Figure 11: RLC circuit.
V(V1)
1.2V
1.0V
Volts
0.8V
0.6V
0.4V
0.2V
Amps
Volts
0.0V
V(V2)
2.0V
1.8V
1.6V
1.4V
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
10A
8A
6A
4A
2A
0A
-2A
-4A
-6A
-8A
-10A
0.0ms
I(L1)
0.1ms
0.2ms
0.3ms
0.4ms
0.5ms
0.6ms
0.7ms
0.8ms
0.9ms
1.0ms
Figure 12: RLC unity voltage-step transient response.
17
CARMA Correlator
2.5
December 4, 2006
Capacitor voltage ripple
The input and output capacitors in buck converters are used for energy storage and ltering. The
ripple currents due to the switching nature of buck converters dier on the input and output due
to the dierent current waveforms experienced at each location. The input current can be modeled
as a square-wave of current pulses repeating at the frequency of the converter, with a magnitude
equivalent to the output current of the converter, and a duration equal to the duty-cycle of the
converter. The output current from the converter is a triangular waveform, with the current rising
during the controller on-time, and decreasing during the controller o-time. The input and output
voltage ripple of the converter is directly related to the amount of capacitance, and its equivalent
series resistance (ESR).
TODO: Add an input current ripple simulation and equations.
Figure 13 shows a circuit used to model the inductor current in a buck converter, while Figure 14 shows the transient response with the voltage across the inductor, and the inductor current.
SwitcherCAD gives an incorrect current solution unless the initial operating point is skipped; Simulate, Edit Simulate Command, check Skip initial operating point solution. This failure is likely
due to an incorrect DC bias solution, however, adding initial conditions, eg. .ic V(V2)=0.25, and
various resistors did not help. SwitcherCAD will also fail to solve the circuit if the inductor has no
series resistance, so use the hacks tab (Simulate, Control Panel, Hacks tab), and uncheck Always
default inductors to Rser=0. This is a typical issue with inductors in SPICE, eg. see the discussion
on pp12-13 in reference [79].
Figure 15 shows a circuit used to model the integration of the buck converter inductor current
by the output capacitor, while Figure 16 shows the transient response. The pulsed current source
generates a positive current ramp for 0.5us, and negative current ramp for 1.5us. The peak current
is 1A, so the integrated current per pulse is 1A2s/2 = 1/C. So the increase in capacitor voltage
is 1C/100F = 10mV per pulse. Figure 16 shows ve current pulses, and the nal capacitor voltage
is 50mV. An alternative way to calculate the average voltage on the capacitor, is to note that the
average current in Figure 16 is 0.5A, so after 10s, the voltage is 0.5A 10s/100F = 50mV.
Figure 17 shows a circuit used to model the ripple voltage on the output capacitor, while Figure 18
shows the transient response. Relative to the circuit in Figure 15, Figure 17 adds a load current
that draws 0.5A after 50s, i.e., when the load voltage reaches 0.25V. The peak-to-peak ripple in
the output voltage for time greater than 50s is determined by the inductor ripple current, and the
size of the output capacitor.
Once the load current in Figure 17 starts drawing 0.5A, the average current in the capacitor is
zero, i.e., the current for a pulse starts at -0.5A linearly increases to 0.5A for 0.5s, and then linearly
decreases from 0.5A back to -0.5A. The voltage ripple waveform follows a quadratic shape during
each linear current change, creating a negative bump during the rising current, and a positive bump
during the falling current. The peak-to-peak voltage ripple for a peak-to-peak current pulse of size
Ipp for rising current time tr , and falling current time tf , can be determined by calculating the areas
of the current triangles for each half of the switching periods;

IOUT tR
IOUT tF
1
VOUT =
C
4
2
4
2
(28)
IOUT
=
8f C
where f = 1/(tR +tF ) is the switching frequency of the current source (buck converter). For example,
the ripple voltage in Figure 18 is VOUT = 1/(8 500kHz 100F = 2.5mV, or 1-percent of the
output voltage. Equation 28 is generally used to determine the minimum output capacitor size
required to meet an output ripple voltage requirement, based on a specied inductor ripple current.
18
CARMA Correlator
December 4, 2006
L1
V1
V2
1H
V1
V2
0.25
PULSE(0 1 0 0.1u 0.1u 0.4u 2u)
.tran 0 10u 0 100p uic

Figure 13: Buck inductor current circuit.
V(V1)-V(V2)
800mV
600mV
Volts
400mV
200mV
0mV
-200mV
-400mV
I(L1)
400mA
350mA
300mA
Amps
250mA
200mA
150mA
100mA
50mA
0mA
-50mA
0s
1s
2s
3s
4s
5s
6s
7s
8s
9s
10s
Figure 14: Buck inductor current transient response.
19
CARMA Correlator
December 4, 2006
V1
I1
C1
100F
PULSE(0 1 0 0.5u 1.5u 0 2.0u)

.tran 0 10u 0 0.0001u
Figure 15: Buck capacitor voltage ramp circuit.
I(I1)
1.0A
0.8A
Amps
0.6A
0.4A
0.2A
0.0A
V(V1)
60mV
50mV
Volts
40mV
30mV
20mV
10mV
0mV
0s
1s
2s
3s
4s
5s
6s
7s
8s
9s
10s
Figure 16: Buck capacitor voltage ramp transient response.
20
CARMA Correlator
December 4, 2006
V1
I1
I2
C1
PULSE(0 1 0 0.5u 1.5u 0 2.0u)
100F
PWL(0 0 49.999u 0 50u 0.5)
.tran 0 100u 0 100p

Figure 17: Buck capacitor voltage ripple circuit.
I(I1)
1.0A
0.8A
Amps
0.6A
0.4A
0.2A
0.0A
V(V1)
300mV
250mV
Volts
200mV
150mV
100mV
50mV
0mV
0s
10s
20s
30s
40s
50s
60s
70s
80s
90s
100s
Figure 18: Buck capacitor voltage ripple transient response.
21
CARMA Correlator
December 4, 2006
current flow with control switch closed

HS
VIN
CIN
VSW
high-side
(control)
switch
LS
low-side
(synchronous
rectifier)
switch
current flow
with sync
switch closed
VOUT
VOUT
COUT
VIN
(a)
(b)
Figure 19: Buck converter topologies; (a) single-phase and (b) multi-phase. (a) also shows the
current ow with respect to closures of the high-side (control) switch, and low-side (synchronous
rectier) switch.
VOUT
VIN
VOUT
VIN
PWM
controller
PWM
controller
(a)
(b)
Figure 20: Buck versus synchronous buck. (a) a buck converter consists of a control-switch typically
implemented using a MOSFET, and a synchronous-switch implemented using a diode. (b) a synchronous buck converter also uses a MOSFET for the synchronous-switch, and an optional Schottky
diode to reduce MOSFET body diode conduction losses.
3
3.1
Buck and synchronous buck converters

Topology
Figure 19 shows the basic topology for single-phase and multi-phase (poly-phase) buck converters.
A buck converter steps-down an input voltage to a lower output voltage by modulating the voltage
across an inductor. The high-side or control switch in a buck converter can be implemented using
a bipolar transistor, P-channel MOSFET, or N-channel MOSFET. The low-side or synchronous
switch can be implemented using a diode, or in supplies with low output voltages, with an Nchannel MOSFET. A buck converter that uses an N-channel MOSFET for the synchronous switch
is refered to as a synchronous buck converter, while the diode version is refered to simply as a buck
converter. Figure 20 shows typical buck and synchronous buck circuits.
22
CARMA Correlator
3.2
December 4, 2006
Continuous-mode and discontinuous-mode operation
The transfer function of a buck converter is determined for the circuit in steady-state, i.e., the output
capacitance has been charged to VOUT , and the load current has stabilized to IOUT . Depending on
the load current, the buck converter operates in one of two modes; continuous-mode or discontinuousmode. Figure 21 and Figure 22 show idealized steady-state waveforms for a buck converter operating
in continuous-mode and discontinous-mode respectively.
For continuous-mode operation, the modulation voltage at location VSW in Figure 19(a) is either
VIN (HS on, LS o), or 0V (HS o, LS on), as shown in Figure 21(a). Figure 21(b) shows that the
voltage across the inductor is then (VIN VOUT ) or VOUT , leading to the current owing through
the inductor given by (8), and shown in Figure 21(c). The current owing through the inductor is
sourced from the input supply during the high-side switch on-time, as shown in Figure 21(d), and
from ground during the high-side switch o-time (low-side switch on-time) as shown in Figure 21(e).
The output capacitor integrates the capacitor current, (IL (t) IOUT ), according to (4), generating
the voltage ripple shown in Figure 21(f).
The transfer function, VOUT /VIN , for the steady-state continuous-mode can be found by noting
that the increase in current during the high-side switch on-time in Figure 21(c) equals the decrease
in current during the high-side switch o-time (low-side switch on-time), i.e., using (8) with constant
voltages,
1
1
(VIN VOUT ) DT = VOUT (1 D)T
L
L
(29)
where T is the switching period, D (0, 1) is the high-side switch duty-cycle, DT is the high-side
switch on-time, and (1 D)T is the low-side switch on-time. Solving for the transfer function gives
DT
VOUT
=D
=
VIN
DT + (1 D)T
(30)
i.e., the duty-cycle of a buck converter is specied by the output to input voltage ratio. For example,
the generation of a 3.3V output from a 5V input supply using an idealized buck converter requires
a duty cycle of 66-percent.
Since the idealized buck converter circuit components are lossless, the steady-state output power
must equal the input power, i.e., VOUT IOUT = VIN IIN , so the current transfer function is
IOUT
1
= .
IIN
D
(31)
For D < 1, IOUT /IIN > 1, so the load current is higher than the input current.
The peak-to-peak output current is;
1
(VIN VOUT ) DT
L
T
= VIN D(1 D)
L

VOUT
VOUT
=
1
fL
VIN
IOUT =
(32)
where f = 1/T is the switching frequency. The peak-to-peak ripple current has a maximum when
D = 0.5. Equation 32 can be used to determine the output ripple current for a given an inductor
value, or the equation can be rearranged to determine the inductor size required to meet a ripple
current specication, i.e., for a given input voltage, output voltage, and switching frequency,

VOUT
VOUT
L=
1
(33)
f IOUT
VIN
23
CARMA Correlator
December 4, 2006
VIN
(a)
VSW (t)
t
VIN VOUT
(b)
VL(t)
VOUT
(c)
I L(t)
(d)
I HS(t)
(e)
I LS(t)
DI OUT
(f) V
(t)
COUT
I OUT
VOUT
DVOUT
Figure 21: Buck converter continuous-mode waveforms; (a) voltage at the switched node, (b) voltage
across the inductor, (c) current through the inductor, (d) current through the high-side switch from
the input supply, (e) current through the low-side switch, and (f) output voltage.
24
CARMA Correlator
December 4, 2006
A buck converter transistions from continuous-mode to discontinuous-mode when the average

load current drops to half the peak-to-peak current through the inductor, i.e., when IOUT =
IOUT /2, the current in Figure 21(c) would drop to the point that the minimum current reaches
zero. For lower load currents, the buck converter waveforms have sections where the inductor current
is zero, i.e., Figure 22(c). The transition occurs at the critical load current of;
1
IOUT
2
T
VOUT (1 D)
=
2L
ICRIT =
(34)
For discontinuous-mode operation, the modulation voltage is either VIN (HS on, LS o), or 0V
(HS o, LS on), or VOUT (HS o, LS o) as shown in Figure 22(a). Figure 22(b) shows that the
voltage across the inductor is then (VIN VOUT ) or VOUT , or 0V, leading to current owing through
the inductor as shown in Figure 22(c), i.e., there are three inductor current conditions; increasing,
decreasing, or none.
The transfer function, VOUT /VIN , for the steady-state discontinuous-mode can be found using
the same technique as for continuous mode. Given a high-side switch on-time of THS , with duty cycle
DHS = THS /T , a low-side switch on-time of TLS , with duty cycle DLS , the peak currents match;
1
1
(VIN VOUT ) THS = VOUT TLS ,
L
L
(35)
VOUT
THS
DHS
=
=
.
VIN
THS + TLS
DHS + DLS
(36)
so the transfer function is
The low-side switch duty cycle time, DLS , can be eliminated, by solving for the average output
current, i.e.,

1 1
1
1 1
(VIN VOUT ) THS THS + VOUT TLS TLS
IOUT =
T
2 L
2 L

VIN T
VOUT 2
2
2
DHS
=
(DHS DLS
)
2L
VIN
(37)

VIN T
DHS
2
=
DHS
(DHS + DLS )(DHS DLS )
2L
DHS + DLS
VIN T
=
DHS DLS
2L
which rearranged gives
DLS =
2LIOUT
VIN DHS T
(38)
giving a discontinuous-mode transfer function of

VOUT
=
VIN
D2
HS
.
2LIOUT
2
DHS +
VIN T
(39)
which is clearly more complicated than the continuous-mode! For a xed VIN , VOUT , inductor value,
and switching frequency, this equation can be rearranged to show how the switch duty cycle changes
with load current during discontinuous-mode operation (eg. p5-3 [49]). Because the closed-loop
gain of the converter is no longer a linear function, if a converter is to be operated at output loads
that cause it to operate in continuous and discontinuous modes, the converter stablity needs to be
conrmed for both modes [49].
25
CARMA Correlator
December 4, 2006
VIN
(a)
Both
switches off
VOUT
VSW (t)
t
VIN VOUT
(b)
VL(t)
VOUT
(c)
I L(t)
DI OUT
I OUT
(d)
I HS(t)
(e)
I LS(t)
(f) V
COUT(t)
DVOUT
VOUT
Figure 22: Buck converter discontinuous-mode waveforms; (a) voltage at the switched node, (b)
voltage across the inductor, (c) current through the inductor, (d) current through the high-side
switch from the input supply, (e) current through the low-side switch, and (f) output voltage.
26
CARMA Correlator
3.3
December 4, 2006
RMS current analysis
Power dissipation analysis for a buck converter operating in continuous mode requires the rootmean-squared (RMS) currents for the waveforms shown in Figure 21. Appendix A calculates the
mean, RMS, and variance for a trapezoidal current waveform. The following gives the RMS current
for each circuit component in steady-state.
Input capacitor current
The input capacitor current in steady-state consists of the AC component of the high-side switch
RMS current, i.e.,

2
2
ICIN RMS = IHS
RMS IHS MEAN

2
IOUT
2
2
=
D2
IOUT +
D IOUT
12

(40)
2
IOUT
2
= IOUT
1+
D
2
12IOUT

r2
= IOUT
1+
D D2
12
where the ripple current ratio, r, is dened as
r=
IOUT
IOUT
(41)
In some application notes and design guides, the input capacitor RMS current is approximated by

(42)
ICIN RMS IOUT D(1 D)
which is equivalent to the AC component of a high-side switch current waveform that is approximated
as a square-wave of amplitude IOUT and duty-cycle D, i.e., the mean is IOUT D, and the mean-squared
2
D.
is IOUT
High-side switch current
The high-side switch RMS current, in steady-state continuous conduction mode, consists of a
trapezoidal current pulse during the switch on-time, t (0, DT ), and no current during the switch
o-time, t (DT, T ), i.e.,

2
IOUT
2
IHS RMS =
IOUT +
D
12

(43)
r2
1+
D
= IOUT
12
IOUT D
27
CARMA Correlator
December 4, 2006
Low-side switch current

The low-side switch RMS current, in steady-state continuous conduction mode, consists of no
current during the switch o-time, t (0, DT ), and a trapezoidal current pulse during the switch
on-time, t (DT, T ), i.e.,

2
IOUT
2
+
ILS RMS =
IOUT
(1 D)
12

(44)
r2
= IOUT
1+
(1 D)
12

IOUT (1 D)
Inductor current
The inductor RMS current, in steady-state continuous conduction mode, is calculated from the
sum of the mean-squares of both MOSFET currents, i.e.,

2
2
IL RMS = IHS
RMS + ILS RMS

2
IOUT
2
= IOUT
+
(45)
12

r2
= IOUT
1+
12
i.e., the inductor current consists of a DC component IOUT and a ripple (AC) component IOUT / 12.
Output capacitor current
In steady-state, IOUT is delivered to the load, and the capacitor does not draw current, so the
capacitor RMS current is due to the ripple component only, i.e.,

ICOUT RMS = IL2 RMS IL2 MEAN
=
IOUT
12
(46)
r
= IOUT
12
The conductive power dissipation terms in a buck converter are, by denition, of the form
2
IRMS
R, i.e, mean-squared current times component resistance. The ripple current causes a
slight increase in conductive power dissipation that scales most power terms by (1 + r2 /12). The
recommended ripple current ratio of r = 0.3 [62], therefore scales the power terms by 1.0075, i.e.,
the power dissipation is increased by about 1-percent. Most of the conductive power terms are also
linearly proportional to the duty-cycle, so variation of the duty-cycle will also cause a variation in
the power dissipation, eg. a supply specied with an input voltage range of 10V to 12V, creating a
1.2V output supply, has a duty-cycle, and hence power dissipation variation of 2-percent.
The RMS currents in the input capacitor, high-side switch, and low-side switch are all duty-cycle
dependent. Figure 23 shows the duty-cycle dependence for a ripple current ratio of r = 0.3, and the
duty-cycle dependence ignoring ripple current (as presented by most application notes).
28
CARMA Correlator
December 4, 2006
Input capacitor RMS current
Normalized RMS current
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
Duty cycle
0.8
(a)
Lowside switch RMS current
1
0.8
0.8
Highside switch RMS current

1
0.6
0.4
0.2
0
0
0.6
0.4
0.2
0.2
0.4
0.6
Duty cycle
(b)
0.8
0
0
0.2
0.4
0.6
Duty cycle
0.8
(c)
Figure 23: RMS current versus duty cycle for; (a) the input capacitors (b) the high-side switch,
and (c) the low-side switch. The dashed (red) lines are the RMS calculations that include ripple
current, with a ripple current ratio of r = 0.3, while the solid (blue) lines are the approximate RMS
calculations that ignor the ripple current term.
29
CARMA Correlator
3.4
December 4, 2006
Synchronous buck operation
Synchronous buck converters are generally used for low-voltage, high-current, supplies such as those
used for CPU, DSP, or FPGA core voltages due to eciency considerations. The power dissipated
by the synchronous rectier (low-side) diode in a buck converter is [62]
PLS DIODE = IOUT VF (1 D)
(47)
where VF is the forward drop of the diode at an output current of IOUT , eg. around 0.35V for a
Schottky diode. The power dissiation of a MOSFET used for the synchronous rectier (low-side)
switch is
2
PLS MOSFET = ILS
RMS
2
RDS(on) IOUT
RDS(on) (1 D)
(48)
where RDS(on) is the on-resistance of the MOSFET, which is typically a few milli-ohms for a good
power MOSFET. The power dissipation of the synchronous rectifying switch using either a diode or
MOSFET, is linearly dependent on the duty cycle. For high-input to low-output voltage conversions,
the rectifying switch is on for most of the switching period, so its losses contribute to lowering
the eciency of the supply. For example, a 5V to 1.2V converter with a 5A load current, would
dissipate 1.3W using a Schottky diode, or 0.2W using a MOSFET with RDS(on) = 10mclearly
the synchronous buck design is more ecient.
Replacing the buck converter synchronous rectifying diode with a MOSFET brings a new set of
design issues;
The PWM controller now has to have complimentary outputs that have critical relative-timing
to prevent switch shoot-through (both switches on, also known as cross-conduction). To prevent
this, gate drive turn-on and turn-o deadtime delays are added [49].
The gate drive deadtime delays cause the body-diode of the synchronous rectier MOSFET
to conduct during the o-time.
Synchronous rectier MOSFET body-diode reverse recovery; the high-side switch has to supply
the reverse recovery charge, Qrr , of the low-side diode.
Synchronous rectier parasitic turn-on, i.e., dV /dt induced turn on (p5-6 [49]). A snubber
circuit at the switching node can be used to mitigate this issue.
If the converter operates in discontinuous mode, then depending on the controller, it can
potentially back-feed current into the input supply; the input capacitance must be capable of
absorbing this current (p5-4 [49]).
30
CARMA Correlator
3.5
December 4, 2006
Output capacitance selection
The output capacitance serves as an energy storage device (charge reservior); when the load current
increases, the capacitor supplies load current until the inductor current increases, and then when
the load current decreases, the capacitor absorbs the energy stored in the inductor. The output
capacitance also acts as a lter, absorbing the inductor AC ripple current.
The output ripple voltage is determined by the output capacitance value and the capacitor
equivalent series resistance (ESR). The ripple voltage for a given ripple current is

1
(49)
VOUT = IOUT RCOUT +
8f CCOUT
where RCOUT is the capacitor ESR. During load transients, the output current changes abruptly, so
output capacitor ESL will generate a voltage spike VESL = LCOUT dI/dt (eg. see p5-15 [49]). These
voltage spikes can be mitigated using high-frequency ceramic decoupling capacitance in parallel with
the bulk capacitance (p5-14 [49]).
The value of the output capacitor is determined by the energy it needs to store when the load
goes from maximum current, to no load. In steady-state with a load current of IOUT , the energy
stored in the inductor and output capacitor is

2
IOUT
1
1
2
+ COUT VOUT
(50)
E = L IOUT +
2
2
2
When the load current drops to zero, the energy stored in the inductor needs to be stored by the
output capacitor, so its voltage increases to (VOUT + VOUT ), where

2
1
1
IOUT
1
2
COUT (VOUT + VOUT )2 = L IOUT +
+ COUT VOUT
.
(51)
2
2
2
2
The voltage increase due to the absorption of the inductor current is

2
L
IOUT
2
VOUT =
+ VOUT
VOUT
IOUT +
COUT
2
(52)
(p48 [62] has a typographical error in this equation). Rearranging this equation to determine the
output capacitance value required for a specied voltage deviation gives

2
IOUT
L IOUT +
2
COUT =
(53)
2
(VOUT + VOUT )2 VOUT
Equation 49 can then be solved to determine the capacitor ESR, i.e.,
RCOUT =
VOUT
1
IOUT
8f COUT
(54)
The capacitance value required to satisfy the energy equation is generally large enough that the
current ripple integrated by the capacitor does not appreciably add to the output voltage ripple in
steady-state, so the required ESR is generally determined from
RCOUT
VOUT
IOUT
(55)
Reference [49], p5-11, contains a discussion that compares various capacitor types, their properties,
and their relative cost per Farad.
31
CARMA Correlator
3.6
December 4, 2006
Input capacitance selection
Input capacitors are selected based on the following priority; RMS current rating, ESR, equivalent
series inductance (ESL), and capacitance value. The RMS current through the input capacitors is
given by (40), or generally approximated by (42). The ripple current through the input capacitor
is the same as the ripple current in the high-side switch, as shown in Figure 21(d). The important dierence between the input capacitor current waveform versus the output capacitor current
waveform, which is the same as the inductor current waveform in Figure 21(c), is the sharp edges
in the current waveform; the ESL of the input capacitor reacts with these fast edges and creates
high-frequency voltage spikes of size VESL = LdI/dt.
The input capacitor current waveform has a peak-to-peak of (IOUT + IOUT /2), so the required
ESR to maintain a voltage ripple of less than VIN is approximately
VIN

RCIN
IOUT
IOUT +
2
(56)
The capacitance value required depends on the impedance of the power source. A rule of thumb is to
select a capacitance value of 10F to 20F per ampere of output current (p49 [62]). The minimum
amount of input capacitance can be determined by calculating the voltage ripple caused by the
input current removing charge o the input capacitance. Assuming the input current pulses are of
magnitude IOUT and duration t = D/f , where D is the duty-cycle and f is the switching frequency,
then the amount of charge removed by each pulse is Q = IOUT t, so the change in voltage on the
input capitance is VIN = Q/CIN , so the minimum amount of input capacitance to meet a ripple
voltage requirement is
CIN(MIN) =
IOUT D
VIN f
(57)
As an example, consider a 5V input supply used to create a 2.5V at 5A output supply with a ripple
current ratio of 0.3, input voltage ripple limit of 4-percent (100mV), and a switching
frequency of
500kHz. The input capacitance requires an RMS current rating of ICIN RMS IOUT D(1 D) =
2.5A. The minimum amount of input capacitance required based on capacitance ripple is 15F,
and from the rule-of-thumb approach (p49 [62]), the recommended amount is 50F to 100F. The
ESR induced ripple voltage requires a capacitor ESR of under RCIN = 100mV/5.75A = 17.4m
(or multiple paralleled capacitors to meet those requirements). If the capacitor ESL was 3nH, and
the controller switching time was 100ns, then the voltage spikes due to ESL would be 173mV, i.e.,
almost twice the ripple voltage. A faster controller edge switching rate will increase the size of
the ESL induced voltage spikes on the input. ESL induced voltage spikes are reduced by placing
high-frequency, small valued, ceramic capacitors near the MOSFET switches, as this minimizes the
current switching edge rates seen at the bulk input capacitance.
32
CARMA Correlator
3.7
December 4, 2006
MOSFET selection
The high-side and low-side MOSFETs in a buck converter are selected to minimize their power
dissipation for their specic application; the high-side MOSFET switches the input voltage at a
low duty-cycle, so is selected based on its switching power dissipation (at the expense of slightly
higher conductive power dissipation), while the low-side MOSFET switches near ground with a high
duty cycle, so is selected based on its conduction losses. In both cases once power dissipation is
estimated, the junction temperature of the MOSFET must be conrmed to be within acceptable
limits. Fairchilds Application Note AN-6005 [46] has an excellent description of MOSFET power
dissipation, and an associated spreadsheet for calculating synchronous buck converter power dissipation. References [9, 10, 49, 62] also provide details on MOSFET power dissipation and criteria for
MOSFET selection. Power MOSFET basics are covered in references [2, 48, 58, 63].
3.7.1
MOSFET and controller parameters
Table 1 summarizes the parameters of the controller needed to analyze the MOSFET power dissipation. Table 2 summarizes the MOSFET parameters. The MOSFET parameter subscripts are
prexed with HS or LS as required to avoid ambiguity.
3.7.2
Maximum junction temperature
The maximum junction temperature of a MOSFET can be estimated from

TJ(MAX) = TA(MAX) + JA PD
(58)
where TA(MAX) is the maximum ambient temperature, JA is the thermal resistance of the junctionto-ambient path, and PD is the power being dissipated by the device.
The maximum junction temperature stated in the datasheet of a power MOSFET is typically
150 C. However, the maximum recommended operating temperature is between 105 C and 120 C
(p90 [9], p50 [62]). Given a maximum ambient temperature, and an estimate of the junction-toambient thermal resistance (usually provided in the MOSFET datasheet), the maximum power
dissipation can be estimated as
PD(max) =
TJ(MAX) TA(MAX)
JA
(59)
eg. a device operating at TA(MAX) = 60 C, mounted such that JA = 40 C/W, will keep the junction
temperature below 120 C if it dissipates less than 1.5W.
If the junction temperature estimate for a design is too high, the thermal resistance to ambient,
JA , can be reduced by improving the MOSFET heatsink. MOSFET datasheets generally show
several JA estimates for dierent heatsinking options. If reducing JA is not possible, or does not
help, then a dierent MOSFET can be selected. In the case of the low-side MOSFET, devices can
be placed in parallel to reduce the on-resistance of the device. Using parallel high-side MOSFETs
does not usually help, as this increasing the gate capacitance and increases the switching loss. A
multi-phase buck converter reduces the current-handling requirements of individual MOSFETs, and
is the preferred topology for high-current designs.
33
CARMA Correlator
December 4, 2006
Table 1: Controller parameters used for MOSFET power analysis

Parameter
Description
VHS DRIVER
RHS DRIVER PULL UP
RHS DRIVER PULL DOWN
High-side gate-driver drive voltage

High-side gate-driver pull-up resistance
High-side gate-driver pull-down resistance
VLS DRIVER
RLS DRIVER PULL UP
RLS DRIVER PULL DOWN
Low-side gate-driver drive voltage

Low-side gate-driver pull-up resistance
Low-side gate-driver pull-down resistance
tDELAY(R)
tDELAY(L)
Dead-time delay for high-side turn-on

Dead-time delay for high-side turn-o
Table 2: MOSFET power analysis parameters

Parameter
Description
RDS(on) (25 C)
T
RGATE
VSP
VTH
CISS0
CISS
COSS
CRSS
QGS
QGD
QG(SW)
QG
On-resistance at 25 C
On-resistance temperature coecient
Gate resistance
Switching point voltage
Threshold voltage
Input capacitance at a gate voltage of 0V
Input capacitance
Output capacitance
Reverse transfer capacitance
Gate-to-source charge
Gate-to-drain charge
Gate switching charge
Total gate charge
VF
QRR
Diode forward voltage drop

Diode reverse recovery charge
JA
Junction-to-ambient thermal resistance
34
CARMA Correlator
3.7.3
December 4, 2006
On-resistance temperature dependence
The MOSFET on resistance changes approximately linearly with temperate over its normal operating range. A MOSFET datasheet contains a plot of junction temperature versus normalized
on-resistance, where the normalization occurs relative to the resistance at 25 C. The on-resistance
temperature dependence can be approximated by
RDS(on) (T ) = [1 + (T 25 C)T ] RDS(on) (25 C)
(60)
where T is the slope of the normalized on-resistance curve, in units of per-degree-Celcius ( C1 ),

and typically on the order of 0.005.
3.7.4
High-side MOSFET selection
The high-side MOSFET is selected based on its switching and conductive losses. The example
designs in Section 6 show that in high-eciency, high-current designs, these two power dissipation
terms contribute fairly evenly to the total power dissipation (Figure 9 on p5-9 of [49] also shows
this).
The high-side conduction loss is
2
PHS CONDUCTION = IHS
RMS RDS(on)
2
D IOUT
RDS(on) (T )
(61)
where RDS(on) (T ) is the resistance of the MOSFET in the on state, at the operating temperature,
T , of the junction. The value of the conduction loss can only be calculated once the dynamic loss is
known.
The high-side switching loss is
PHS SWITCHING
1
VIN IOUT f (tLH + tHL )
2
(62)
where f is the switching frequency, and tLH and tHL are the low-to-high and high-to-low switching
times of the MOSFET gate drive. The switching times are a function of both the MOSFET and
the gate driver circuit. Fairchild AN-6005 shows how these switching times are calculated [46], and
reference [9] uses a similar approach.
The gate drive current, and switching-times are
VHS DRIVER VHS SP
RHS DRIVER PULL UP + RHS GATE
VHS SP
=
RHS DRIVER PULL DOWN + RGATE
QHS G(SW)
=
IHS DRIVER LH
QHS G(SW)
=
IHS DRIVER HL
IHS DRIVER LH =
IHS DRIVER HL
tLH
tHL
(63)
where the high-side gate driver properties are; the gate drive voltage VHS DRIVER , the driver pullup resistance RHS DRIVER PULL UP , and the driver pull-down resistance RHS DRIVER PULL DOWN .
The high-side MOSFET properties are; switching point VHS SP , gate resistance RHS GATE , and
gate switching charge QHS G(SW) . The product of the gate switching charge and on resistance,
QG(SW) RDS(on) , can be used as a gure-of-merit (FOM) for high-side MOSFET selection [10].
There are several other smaller dynamic switching terms that contribute to the high-side power
dissiption [46]. The power to charge the gate
PHS GATE = QG VHS DRIVER f
(64)
35
CARMA Correlator
December 4, 2006
The power to charge the MOSFETs output capacitance

PHS OSS
1
2
COSS VIN
f
2
(65)
The reverse recover power for the low-side body diode recovery charge
PHS QRR = QLS QRR VIN f
(66)
The total dynamic power dissipation for the high-side MOSFET is

PHS DYNAMIC = PHS SWITCHING + PHS GATE + PHS OSS + PHS QRR
(67)
The total power dissipation is then

PHS TOTAL = PHS CONDUCTION + PHS DYNAMIC
(68)
Using (61), (60), (58) with PD = PHS TOTAL to calculate T = TJ(MAX) , and solving for PHS TOTAL
gives

2
D IOUT
1 + (TA(MAX) 25 C)T RDS(on) (25 C) + PHS DYNAMIC
PHS TOTAL =
2
1 D IOUT
JA T RDS(on) (25 C)
(69)
2
D IOUT RDS(on) (TA(MAX) ) + PHS DYNAMIC
=
2
1 D IOUT
JA T RDS(on) (25 C)
This equation accounts for the temperature dependence of the conductive term. Once the dynamic
power has been estimated, the total power can be determined, and then the conductive component
is simply
PHS CONDUCTION = PHS TOTAL PHS DYNAMIC
(70)
with the junction temperature given by (58), and the on-resistance at that temperature given by (60).
If the junction temperature is not within design limits, then a design iteration is required.
36
CARMA Correlator
3.7.5
December 4, 2006
Low-side MOSFET selection
The low-side MOSFET is selected primarily based on its conductive loss. However, switching loss
contributes to the total power dissipation, and hence operating junction temperature, so its contribution cannot be ignored.
The low-side conduction loss is
2
PLS CONDUCTION = ILS
RMS RDS(on)
2
(1 D) IOUT
RDS(on) (T )
(71)
Technically the duty cycle of the low-side switch, (1D), is (1Df tDEADTIME), where tDEADTIME
(discussed in more detail below) is the delay between the high-side and low-side gate drives (p59 [49]).
The low-side switching loss is
PLS SWITCHING

1
IOUT f 2(t2r + t2f )VF + (t3r + t3f )(VF + IOUT 1.1 RDS(on) (25 C))
2
(72)
where VF is the forward voltage of the low-side diode (either the MOSFET body diode, or a Schottky), t2 and t3 are segments of the switching time, and the r and f characters in the subscripts refer
to rising and falling edges; see AN-6005 [46] for complete details.
The gate switching times are calculated using the following equations (RC time-constants);
r = CLS ISS0 (RLS DRIVER PULL UP + RLS GATE )

VLS DRIVER
VLS DRIVER
log
k2r = log
VLS DRIVER VLS SP
VLS DRIVER VLS TH
t2r = k2r r

VLS DRIVER
VLS DRIVER
k3r = log
log
VLS DRIVER 0.9VLS SPEC
VLS DRIVER VLS SP
t3r = k3r r
f = CLS ISS0 (RLS DRIVER PULL DOWN + RLS GATE )

VLS SP
k2f = log
VLS TH
t2f = k2f f

0.9VLS SPEC
k3f = log
VLS SP
(73)
t2f = k3f f
where the low-side gate driver properties are; the gate drive voltage VLS DRIVER , the driver pull-up
resistance RLS DRIVER PULL UP , and the driver pull-down resistance RLS DRIVER PULL DOWN . The
low-side MOSFET properties are; switching point VLS SP , gate threshold voltage VLS TH , and the
gate voltage for the highest specied on-resistance, VLS SPEC .
The power required to charge the gate also contributes to the dynamic switching power, i.e.,
PLS GATE = QG VLS DRIVER f
(74)
If the converter uses a MOSFET with integrated Schottky diode, or allows the MOSFET body
diode to conduct during the high-side to low-side switch deadtime, then that power dissipation also
contributes to the dynamic power dissipation
PLS DIODE = IOUT VF tDEADTIME f
(75)
37
CARMA Correlator
December 4, 2006
where
tDEADTIME = tDELAY(R) + tDELAY(F) +
QLS GS (RLS DRIVER PULL UP + RLS GATE )

VLS DRIVER VLS TH /2
(76)
where tDELAY(R) is the controller high-side turn on deadtime delay, tDELAY(F) is the controller highside turn o deadtime delay, and the last term is the time taken for the gate driver to charge the
low-side MOSFETs gate to reach the threshold voltage [46].
The total dynamic power dissipation for the low-side MOSFET is
PLS DYNAMIC = PLS SWITCHING + PLS GATE + PLS DIODE
(77)
The total power dissipation is then

PLS TOTAL = PLS CONDUCTION + PLS DYNAMIC
(78)
Following a similar procedure as used for the high-side switch, the total power dissipation is
PLS TOTAL =
2
(1 D) IOUT
RDS(on) (TA(MAX) ) + PLS DYNAMIC
2
1 (1 D) IOUT
JA T RDS(on) (25 C)
(79)
which can be used to calculate the low-side MOSFET junction temperature and on-resistance.
The on resistance and hence power dissipation of the low-side MOSFET can be decreased by
using parallel MOSFETs. If NLS MOSFETs are used, the conduction losses will decrease by NLS ,
while the switching losses will increase by NLS . The power seen by an individual MOSFET will be
decreased, so its junction temperature will decrease, i.e.,
TJ(MAX) = TA(MAX) + JA
PLS TOTAL
NLS
(80)
The total low-side power dissipation for NLS MOSFETs is

PLS TOTAL
2
(1 D) IOUT
RDS(on) (TA(MAX) )/NLS + PLS DYNAMIC NLS
2
2
1 (1 D) IOUT
JA T RDS(on) (25 C)/NLS
(81)
Note that the power increase due to the temperature dedendence of the MOSFET on-resistance in
the denominator is reduced by a quadratic factor. This is due to the fact that both the power-perMOSFET, and the total resistance, hence total power, is reduced. So paralleling a pair of MOSFETs
in the low-side switch helps out more than one might expect. The dynamic dissipation is slightly
more complex than is shown, since the gate resistances of the MOSFETs are also in parallel. The
AN-2005 spreadsheet has the appropriate form, however, the approximation shown here is sucient
to show the reason why using parallel low-side MOSFETs is useful.
38
CARMA Correlator
3.8
December 4, 2006
Buck and synchronous buck design
TODO: COMPLETE THIS SECTION.

1. Inductor selection:
The general recommendation is to use (33) to select an inductor that produces a ripple current
of 10-percent to 30-percent of the full load current [49].
Reference [59], oers a slightly dierent criteria on p7, that is; given the full load current, select
the inductor such that the ripple current is slightly smaller than the critical current required
to keep the converter operating in continuous mode (p7 [59]), i.e., the ripple current is about
50-percent of the full load current.
The RMS inductor conduction loss due to the inductor winding resistance, RL , is (p5-7 [49])

r2
2
1+
(82)
PL RMS = IL2 RMS RL = IOUT
RL
12
2. high-side switch MOSFET selection:
3. Synchronous rectifier selection:
4. Input decoupling capacitance selection:
5. Input filter selection:
6. Output decoupling capacitance selection:
Given a voltage ripple specication for the output voltage, VOUT , determine the capacitance
value using (53), and the capacitor ESR using (54).
3.9
Multi-phase synchronous buck converters
TODO: COMPLETE THIS SECTION.

Multi-phase synchronous buck converter are essentially parallel copies of lower-rated single-phase
converters. The phasing of the converters reduces the input ripple currents by taking smaller pulses
of current more often. The output ripple current is reduced due to the summation of the waveforms.
TODO: put in references to the TI, LTC, and Intersil app notes. Add ripple current gures for
input and output capacitance.
Pentium processor Voltage Reference Modules (VRMs) ...
TI SLUP2006 Appendix D interleaved converter comments; reduced RMS input current by
1/N, since each of the N phases converts 1/N of the load current, eective duty cycle increased by
N. Improved transient response since each phase uses a smaller inductor.
LTC AN77 [3].
3.10
Eciency
PowerManagementDesignline article; In a synchronos buck converter, the MOSFETs are one of the
major sources of eciency loss
high-side (high-side) switch losses:
RMS current through the MOSFET on resistance
Gate driver gate capacitance charging
39
CARMA Correlator
December 4, 2006
Overlap of switching current and the drain-to-source voltage during turn on and o
Drain-to-source capacitance charging
Synchronous rectier (low-side) switch losses:
RMS current through the MOSFET on resistance
Gate driver gate capacitance charging
MOSFET body-diode conduction during converter dead-time
Drain-to-source capacitance charging
3.11
Reducing body-diode conduction loss
Fixed delay, adaptive delay, predictive delay gate drivers [51].
3.12
Load-dependent output voltage
The transient response of a buck converter can be improved by making the output voltage dependent
on the load; at light-load, the output voltage is at the high-end of the allowable range, while under
high-load, the voltage droops nearer the bottom-end of the allowable range. This technique is
referred to as active voltage positioning [70], or active droop [47].
40
CARMA Correlator
December 4, 2006
VIN
VRAMP
VOUT
L
RDCR
I OUT
PWM
COMPARATOR
COUT
R LOAD
RESR
ZFB
C7
R3
COMP
Z IN
C6
FB
R5
ERROR
AMP
C8
R1
VREF
R2
Figure 24: Buck converter voltage-mode compensation. The compensation network around the
error amplier is used to cancel the double-pole of the LC circuit and the zero caused by the output
capacitance ESR. The reference designators in the compensation network match those used in the
TI SWIFT tool.
3.13
Control loop compensation
The control loop of buck and synchronous buck converters contain feedback, and sometimes feedforward elements. The stability of the converter, and its transient response, are determined by the
control loop response. Buck converter controllers are generally either voltage-mode or current-mode
controlled [49, 57]. The following sections detail the two modes.
3.13.1
Voltage-mode control
Figure 24 shows the control loop of a synchronous buck converter. The PWM controller and MOSFET gain is typically modeled as
KPWM =
VIN
VRAMP
(83)
41
CARMA Correlator
December 4, 2006
The output inductor, output capacitance, and equivalent load resistance, RLOAD = VOUT /IOUT , is
called the power stage, and it has a gain (in Laplace format) of
KPOWER (s) =
RLOAD
RLOAD + RDCR

s2 LCOUT
RLOAD + RESR
RLOAD + RDCR
sRESR COUT + 1

RLOAD RDCR
+ s L + COUT RESR +
+1
RLOAD + RDCR
(84)
i.e., the power stage has a zero in the numerator due to the output capacitance ESR, and a doublepole in the denominator due to the inductor-capacitor on the output. If the eective load resistance
is ignored, then the power stage gain is
KPOWER (s)
sRESR COUT + 1
s2 LCOUT + s(RESR + RDCR )COUT + 1
(85)
and if the inductor DC-resistance is ignored, the gain is

KPOWER (s)
sRESR COUT + 1
s2 LCOUT + sRESR COUT + 1
(86)
This form of the power stage gain is the one generally seen in data sheets and application notes,
and is the form that compensation components are calculated for. However, its the full form of the
gain in (84) that should be used when checking the nal loop response (eg. in a graphical tool like
MATLAB). The power gain approximation in (86) has an inductor-capacitor double pole at LC ,
and output capacitance ESR zero at ESR , where
1
LC = 2fLC =
LCOUT
(87)
and
ESR = 2fESR =
1
RESR COUT
(88)
The compensation components shown around the error amplier in Figure 24 have a gain of
VCOMP
VOUT
ZFB
=
ZIN
KCOMP (s) =
1 s(R1 + R5 )C8 + 1
1

R1 (C6 + C7 ) s
sR5 C8 + 1
G1 (s/Z1 + 1)(s/Z2 + 1)
s (s/P1 + 1)(s/P2 + 1)
sR C + 1
3 6
C6 C7
sR3
+1
C6 + C7
(89)
42
CARMA Correlator
December 4, 2006
VIN
A
VREF
VOUT
Figure 25: Canonical form of a buck converter feedback control system.

where the gain at = 1 (integrator pole), the zeros, and poles are
G1 =
Z1 =
Z2 =
P1 =
P2 =
1
R1 (C6 + C7 )
1
(R1 + R5 )C8
1
R3 C6
1
R5 C8
1

C6 C7
R3
C6 + C7
(90)
The assignment of which pole or zero is designated 1 or 2 is arbitrary. The assignment here matches
that used by the TI SWIFT designer tool; in the Compensation Analysis GUI, the components that
aect the integrator pole, each zero, or each pole are highlighted (change to bold-face) as you move
the mouse pointer over each design parameter.
Figure 25 shows the control loop of Figure 24 in its canonical form (for background on feedback
and control systems theory, see p156 [6], Chapter 5, p75, [50], and [57]). The A-block represents the
foward-gain of the power-stage, and includes the PWM controller and output LC-lter, the -block
represents the feedback compensation, and the summing junction is the error amplier. The transfer
function of the system in Figure 25 is
VOUT
A
=
=
VIN
1 + A
1
A
+1
(91)
where for the condition A 1, the gain of the system is determined by the feedback network.
Stability of the control system is determined by the loop-gain, A. If as the loop gain approaches
unity, the phase approaches 180, then A = 1, and the denominator of the transfer function
approaches zero, so the gain of the system approaches innity. The condition for stability is that
as the loop-gain magnitude approaches |A| = 1 (or 0dB for a logarithmic plot), that the loop-gain
phase A < 180 , with a phase-margin of 60 being a general design target.
Voltage-mode compensation of a buck converter creates a stable control system by locating the
poles-and-zeros in the compensation network, so that they compensate for the power-stage inductorcapacitor double pole and capacitor ESR zero. The gain of the compensation network is used to
provide maximum closed-loop bandwidth, and hence the fastest settling time for load transients,
within the limits of the error amplier gain-bandwidth. Figure 26 is an asymptotic Bode plot
showing the power-stage response, the compensation response, and the error amplier gain.
43
CARMA Correlator
December 4, 2006
dB
GAMP
Error amplifier
Compensation
G1
Power-stage
ESR
w=1
wAMP
wZ1 wLC
wP1
wZ2
wESR
log10(w)
wP2
Figure 26: Bode plot for voltage-mode compensation. The plot shows the gain for the power-stage,
compensation network, and error amplier, along with the poles and zeros of each component.
The design procedure for the compensation network starts at the double pole frequency, LC in
Figure 26. The power-stage gain falls o after this point with a 1/ 2 -dependent, (-40dB/decade)
response, which is inherently unstable. Prior to the double pole frequency, the compensation response
has a pole at the origin, and two zeros. The rst zero is used to cancel the pole at the origin,
while the second zero is available to produce an -dependent (20dB/decade) response. Placing the
compensating 20dB/decade reponse on top of the -40dB/decade power-stage double pole, gives a
total loop-gain response of -20dB/decade, which is stable through unity-gain. If the compensation
gain is greater than unity between the two compensation zeros, then the total loop-gain becomes
greater than the power-stage gain, and the loop-gain cross-over frequency, and hence closed-loop
bandwidth of the converter is increased. The compensation response rst pole is then located at the
power-stage ESR zero, so that the total loop-gain response maintains its -20dB/decade response.
The compensation response second pole is then located such that it rolls o the compensation gain
before it exceeds the error amplier gain-bandwidth. The extent to which the compensation network
can increase the cross-over frequency is limited by the error amplier gain bandwith. For example,
with the TI TPS54610 SWIFT controller, the maximum compensation gain is about 1.4, or 3dB.
The design procedure for determining the Figure 24 compensation network values for R1 , R2 ,
R3 , R5 , C6 , C7 , and C8 are;
1. Set R1 = 10k.
2. The output voltage is

VOUT = VREF
R1 + R2
R2
(92)
44
CARMA Correlator
December 4, 2006
so given R1 and VOUT , select R2 via

R2 = R1
VREF
VOUT VREF
(93)
3. Select the compensation network gain at the zeros, eg.,

GZ1 = |KCOMP (Z1 )| = |KCOMP (Z2 )| = 1.4.
(94)
Since the response from KCOMP ( = 1) to KCOMP (Z1 ) follows a 1/-response,

G1 = |KCOMP ( = 1)| = GZ1 Z1
(95)
4. Set the rst zero to between 80% and 100% of the LC pole frequency, eg., Z1 = 0.8LC ,
5. Set the second zero to between 90% and 100% of the LC pole frequency, eg., Z2 = LC .
6. Set the rst pole to the ESR zero frequency, i.e., P1 = ESR .
The location of the rst pole must be inside the gain-bandwidth of the error amplier. The
error amplier gain has a single pole response, i.e.,
KAMP (s) =
GAMP
s/AMP + 1
(96)
where, as shown in Figure 24, GAMP is the DC-gain, and AMP = 2GBW/GAMP is the
pole location. The device data sheet provides the DC-gain (in units of decibels) and the gainbandwidth product, GBW, in units of Hertz. The minimum values for these parameters should
be used when designing the compensation network.
The response from the second zero to the rst pole follows an -response, so the maximum
rst pole location is when this response intersects with the error amplied gain-bandwidth,
i.e.,
GZ1
P1(MAX)
AMP
= GAMP
Z2
P1(MAX)
(97)
So the maximum pole frequency is

P1(MAX) =
GAMP
AMP Z2 .
GZ1
(98)
If the ESR zero is above the maximum pole frequency, then both poles are set to the maximum
pole frequency.
7. If the rst pole was within the error amplier gain-bandwidth, then set the second pole to half
the converter switching frequency, i.e., P2 = fSW .
The location of the second pole must also be within the error amplier gain-bandwidth. The
second pole response gain is the same as the rst pole response gain, so the maximum second
pole response is given by the remainder of the error amplier gain at the rst pole, i.e.,
P2(MAX) =
GAMP
GAMP
Z2
AMP =
AMP
GP1
GZ1
P1
(99)
where GP1 = GZ1 P1 /Z2 , is the gain at the rst pole.

45
CARMA Correlator
December 4, 2006
8. The remaining compensation component values are then determined by solving (90) for the
unknowns in terms of the knowns, i.e.,
R3 =
R5 =
C6 =
C7 =
C8 =
G1 R1 P2
Z2 (P2 Z2 )
R1 Z1
P1 Z1
P2 Z2
G1 R1 P2
Z2
G1 R1 P2
P1 Z1
R1 Z1 p1
(100)
Convert the calculated component values into standard resistor and capacitor values.
9. Plot the loop-gain, and determine the phase-margin. A phase margin of around 60 is desirable.
10. If required, improve the loop-gain response by changing the gain at the compensation zeros,
or adjusting the compensation pole and zero locations.
This compensation network design algorithm is applied to the TPS54610 voltage-mode SWIFT converter analyzed in Section 6.5.5. The algorithm produces similar compensation network parameters
to those produced by the SWIFT designer tool.
The design algorithm presented here is similar to that found in the data sheets for the TI
TPS54010 [38], the Fairchild FAN6520A [65]. the National Semiconductor LM2657 and LM2743 [67,
68], and the Intersil ISL6521 [45]. In those data sheets, the assignments of the which pole or zero
in (90) is 1 or 2 is swapped, and the approximations R5 R1 and C7 C6 are used to give
G1 =
GZ1 =
Z1 =
Z2 =
P1 =
P2 =
1
1
R1 (C6 + C7 )
R1 C6
R3
R3 C6
R1 (C6 + C7 )
R1
1
R3 C6
1
1
(R1 + R5 )C8
R1 C8
1
1

C6 C7
R3 C7
R3
C6 + C7
1
R5 C8
(101)
The algorithms start by selecting the gain at Z1 by setting the ratio R3 /R1 , and then proceed much
as decribed above.
46
CARMA Correlator
3.13.2
December 4, 2006
Current-mode control
Figure 27 shows the current-mode control loop of a synchronous buck converter. Current-mode
control senses the inductor current, and uses that information to modify the PWM ramp rate. The
closed-loop response of the current loop causes the power-stage to appear to the voltage-loop as a
voltage-controlled current-source, i.e., the power-stage response is modeled as Figure 28. The output
voltage of the power-stage for current-mode control is VOUT = ISRC ZOUT , where
sRESR COUT + 1
s(RLOAD + RESR )COUT + 1
(102)
1
1
(RLOAD + RESR )COUT

RLOAD COUT
(103)
1
.
RESR COUT
(104)
ZOUT (s) = RLOAD

which has a pole at
OUT =
and a zero at
ESR =
The power-stage pole is due to the eective load resistance and output capacitance, while the
zero is due to the output capacitor ESR. Figure 29 shows a Bode plot containing the power-stage,
compensation network, and error amplier response. The compensation network in Figure 27 has
the following response
KCOMP (s) =
1
1

R1 (C6 + C7 ) s
sR C + 1
3 6
C6 C7
sR3
+1
C6 + C7
(105)
G1 (s/Z + 1)
=
s (s/P + 1)
where the gain at = 1 (integrator pole), the zero, and pole are
1
R1 (C6 + C7 )
1
Z =
R3 C6
1
1

P =
C6 C7
R3 C7
R3
C6 + C7
G1 =
(106)
where the approximation is valid for C7 C6 .

The compensation network zero is used to cancel the power-stage pole, and the compensation
network pole is used to cancel the output capacitance ESR zero. With the power-stage pole and zero
cancelled, the closed-loop gain takes on a single-pole response (that of the integrator pole), with the
cross-over frequency of the loop being determined by the gain of the compensation network.
The design procedure for determining the Figure 27 compensation network values for R1 , R2 ,
R3 , C6 , and C7 are;
1. Set R1 = 10k.
2. The output voltage is

VOUT = VREF
R1 + R2
R2
(107)
47
CARMA Correlator
December 4, 2006
VIN
VRAMP
VOUT
L
RDCR
I OUT
PWM
COMPARATOR
COUT
R LOAD
RESR
CURRENT
SENSE
20kW
ZFB
C7
R3
Z IN
C6
FB
R1
COMP
ERROR
AMP
VREF
R2
Figure 27: Buck converter current-mode compensation. The inductor current is sensed, and used
to modify the PWM ramp rate. The closed-loop response of the current loop causes the inductor
to appear to the voltage-loop as a voltage-controlled current-source. The compensation network
around the error amplier is used to cancel the output-pole caused by the eective load resistance
and output capacitance, and the zero caused by the output capacitance ESR.
VOUT
I OUT
COUT
VE
R LOAD
RESR
Figure 28: Buck converter current-mode compensation current-source model.
48
CARMA Correlator
December 4, 2006
dB
GAMP
Error amplifier
Compensation
G1
Power-stage
LO
AD
R
VA
TI
IA
O
N
ESR
w=1
wAMP wZ wOUT
log10(w)
wP wESR
Figure 29: Bode plot for current-mode compensation. The plot shows the gain for the power-stage,
compensation network, and error amplier, along with the poles and zeros of each component.
so given R1 and VOUT , select R2 via
R2 = R1
VREF
VOUT VREF
(108)
3. Select the compensation network gain between the zero and the pole. The gain between the
zero and the pole is the same as the gain at the zero, i.e.,
GZ =
R3
G1
R3 C6
=
Z
R1 (C6 + C7 )
R1
(109)
where the approximation holds for C7 C6 .

The gain of the compensation network raises the gain of the closed-loop response, and hence
increases the cross-over frequency. The amount of gain required from the compensation network can be determined by calculating the power-stage gain at the desired cross-over frequency
(the gain in dB will typically be negative), and conguring the compensation network gain to
have sucient gain at the cross-over frequency.
4. Set the compensator zero to the power-stage pole frequency, i.e., Z = OUT .
5. Set the compensator pole to the power-stage ESR zero, i.e., P = ESR .
The location of the compensator pole must be inside the gain-bandwidth of the error amplier.
The gain at the compensator pole is the same as the gain at the zero, so the maximum pole
frequency is given by the remainder of the error amplier gain at the zero, i.e.,
P(MAX) =
GAMP
AMP .
GZ
(110)
49
CARMA Correlator
December 4, 2006
6. The remaining compensation component values are then determined by solving (106) for the
unknowns in terms of the knowns, i.e.,
G1 R1 P
Z (P Z )
P Z
C6 =
G1 R1 P
Z
C7 =
G1 R1 P
R3 =
(111)
Convert the calculated component values into standard resistor and capacitor values.
7. Plot the loop-gain, and determine the phase-margin. A phase margin of around 60 is desirable.
8. If required, improve the loop-gain response by changing the compensation gain, or by adjusting
the compensation pole and zero locations.
The compensation network design algorithm presented here is similar to that used in the TI TPS40090
data sheet (p14 [43]). The TPS40100 [37] also uses a similar algorithm; the cross-over frequency
is rst selected, then the compensating gain required to bring the power-stage response up to the
cross-over frequency is determined. The compensating zero is then placed a decade lower than the
cross-over, and since the power-stage has a -20dB/decade response, this location is the same as the
power-stage pole, i.e., the algorithm would place the compensating zero over the power-stage pole.
The compensation pole is then placed a decade above the cross-over frequency, without regard to the
power-stage ESR zero. The TPS40090 and TPS40100 evaluation boards contain an additional resistor and capacitor around the error amplier input, making their compensation networks identical
to the voltage-mode compensation network.
The current-mode current-source model in Figure 28 is an approximation to what actually occurs
in a current-mode controller. A more complete treatment of the controller characteristics is given
in references [11, 57], where they discuss the role of the current-sense voltage ramp in making the
approximate circuit in Figure 28 valid up to half the controller switching frequency.
50
CARMA Correlator
December 4, 2006
Table 3: CARMA Board Linear Regulator Requirements

Description
VIN
VOUT
IOUT
PD
JA (min)
System controller I/O
3.3V
1.5V
1.8V
500mA
900mW
83.3 C/W
DDR termination
2.5V
1.25V
1.25V
1.5A
1.9W
39.5 C/W
5V
5V
5V
3.3V
2.25V
1.8V
1.7V
2.75V
3.2V
600mA
250mA
150mA
1.0W
688mW
480mW
75.0 C/W
109.0 C/W
156.3 C/W
Digitizer section 3.3V

Linear regulators
Linear regulators are the ideal solution for low current, or noise sensitive, applications. The Digital
designers guide to linear voltage regulators and thermal management [27] discusses the selection
criteria when using linear regulators.
Table 3 shows the linear regulator requirements for the CARMA board (TA = 50 C, TJ(MAX) =
125 C). The general requirements for the linear regulators are;
Adequate junction-to-ambient thermal resistance.
Enable input.
Power-good output.
Monotonic power-on (soft-start).
The last two requirements are required on some of the regulators, but not all. However, if a single
regulator can be used that meets all of the requirements, then the bill-of-materials is simpler. The
DDR termination regulator has special requirements, and its selection is discussed in Section 5.
Linear regulators with the best junction-to-ambient thermal resistances typically have an exposed
pad that can be soldered to the PCB. Reference [27] (p8) compares the size and thermal performance
of Texas Instruments linear regulator packages, while [27] (p26) provides a selection guide of linear
regulators with their output current, available packaging, and features (eg. enable, power-good, and
soft-start).
The regulators that meet (or exceed) the CARMA Board requirements are the 1.5A TPS74201
and 3A TPS74401. These devices have low thermal resistance, enable, power-good, and soft-start.
The devices are packaged in QFN20 and DDPAK7. The TI web pages for the device indicate that
the QFN20 devices are in production. Digikey lists both devices as non-stock, while Mouser has the
TPS74201 in stock in 250-pack minimum buy quantities at $3.70 each device, the TPS74401 was
listed as non-stocked. The QFN20 package is 5.0mm5.0mm and has a JA = 36.5C/W.
Soft-start on linear regulators is a new feature. Texas Instruments author Je Falin wrote a nice
article on how to add soft-start to linear regulators without that feature [12]. Linear Technology
also has a nice article on minimizing switching regulator residue in the output of a linear regulator
by adding ferrite beads [81].
The system controller I/O and digitizer 3.3V supplies will use the TPS74201RGW (QFN). The
digitizer 2.25V and 1.8V supplies could use lower-rated regulators with enable and power-good,
eg. the 500mA TPS77601 or 1A TPS76801 in 6.4mm6.4mm HTSSOP-20 PowerPAD (JA =
42.6 C/W). Digikey lists these devices for $1.28 and $1.47 each per 100.
51
CARMA Correlator
December 4, 2006
DDR termination regulators
The CARMA board contains 512MB of double data-rate (DDR) SDRAM. An overview of DDR,
its power requirements, and design recommendations can be found in Micron device data sheets,
and technical notes [5256], in Freescale application note [19], and in JEDEC DDR and SSTL 2
specications [7, 8].
The CARMA board memory is congured and accessed using the MPC8349E/EA processor
integrated DDR SDRAM controller (Chapter 9 [17, 18]). Power for the CPU and memory is derived
from the cPCI 3.3V power supply. The memory is accessed via a 64-bit data bus plus 8-bit ECC
and operates at a clock-rate of 133MHz, hence, DDR rate of 266MHz. The DDR memory consists
of four 1Gbit-density, 16-bit width, Micron MT46V64M16P-6T devices [55]. The ECC byte also
uses a Micron MT46V64M16P-6T device, but uses only 8-bits of the data interface. The DDR
memory system requires four power supplies; the main supply, VDD (2.5V), the DQ bus supply,
VDDQ (2.5V), termination supply, VTT (1.25V), and receiver reference supply, VREF (1.25V). The
MPC8349E/EA DDR controller uses VDD, and VREF, the Micron 1Gb devices use VDD, VDDQ,
and VREF, and most bus signals terminate to VTT. The VDD and VDDQ power specications are
identical, and are implemented as a single power supply, VDD. On the memory devices, the DQ
power supply, VDDQ, is separated on the die for improved noise immunity (p11 [55]). Power must
be applied to VDD and VDDQ simultaneously, and then to VREF and VTT (p13, p77 [55]). The
following determines the power requirement for each of the DDR power supplies for the CARMA
board memory.
The typical power requirements of VDD can be estimated from the controller and memory
data sheets. The MPC8349E and MPC8934EA hardware specications indicates a typical power
dissipation of 0.66W, or 264mA, for 64-bit 266MHz (p8 [16], p11 [20]). The Micron MT46V64M16P6T data sheet indicates a worst-case IDD current of 535mA (IDD7 for 16-bit width, -6T speed grade,
p58 [55]), so for ve devices this is approximately 2.7A. The VDD supply sources the current that is
sunk by the VTT termination supply, so the worst-case VDD current will be at least the worst-case
VTT current.
SSTL 2 DDR signals have nominal drive currents of 15.2mA, and terminate to 1.25V VTT via
a nominal 25 termination, producing a voltage swing of 380mV relative to VTT, i.e., the nominal
input logic levels are 0.87V and 1.63V. For a 72-bit data bus, the current load for all bits driving
low or high would be 15.2mA 72 1.1A, where it is important to note that the VTT regulator
must be able to both source and sink current. The worst-case VTT current is quoted as being in
the 2.3A to 3.5A range (p17, p19 [19], p5 [56]). This is a transient worst-case load, and would be
dicult to sustain in a practical system via memory accesses [54]. National Semiconductor AN1254 [66] indicates a more conservative sustained current load of 200mA, while the NXP NE57811
data sheet states an average termination regulator power dissipation of between 0.8W and 1.5W,
i.e., termination current of between 0.6A and 1.2A (p7 [69]). So the requirement for the VTT
termination regulator is to deliver up to 1.2A for sustained loads, and up to 3A for transient loads.
The termination regulator options are; switch-mode buck/boost regulator (buck while sourcing,
boost-like while sinking), and linear regulators (packaged such that JA is sucient to handle the
power dissipation).
Terminator regulator options are (p21 [19], p4 [56]);
The MPC8349E-MDS-PB generates VDD using a Linear Technology LT1764EQ-2.5 2.5V linear regulator powered from 3.3V, and then generates VTT using a Fairchild FAN1655MTF
DDR termination linear regulator. The LT1764 is a 3A linear regulator with JA = 30 C/W
(Q package), and the FAN1655 is also a 3A linear regular with JA = 34 C/W. The LT1764
is under-rated in both current and thermal performance for this application.
The MPC8349EA-MDS-PB generates 2.5V VDD and 1.25V VTT using a Texas Instruments
TPS51116PWP switched-mode regulator and linear regulator combo. The switched-mode
52
CARMA Correlator
December 4, 2006
regulator is powered from 5V and generates 2.5V using external N-channel MOSFETs so
can operate with loads of 10A. The linear regulator is powered from the 2.5V switch-mode
output, and can deliver up to 3A. The PowerPAD (PWP) packaging has a thermal resistance
of JA = 39.5 C/W, so the device maximum power rating for an ambient temperature of
TA = 50 C, and maximum junction temperature of TJ(MAX) = 125 C, is 1.9W. If all of this
was dissipated due to the 1.25V linear regulator, then its maximum sustained current would
be 1.5A. This circuit is appropriately rated for the application.
Texas Instruments TPS54x72-series (TPS54372, TPS54672, TPS54872, TPS54972) 3A to 9A
switch-mode termination voltage converters (designed to both source and sink current). These
are high-eciency converters with integrated MOSFETs, and would maintain lower junction
temperatures relative to a linear regulator, however they require more space for layout than a
linear solution.
Texas Instruments TPS51100; 3A DDR termination linear regulator. The device requires both
a 5V input, and a 2.5V VDD input. The device has a junction resistance of JA = 57.8 C/W,
so the device maximum power rating for TA = 50 C, TJ(MAX) = 125 C, is 1.3W, so the
maximum sustained 1.25V current from the 2.5V source supply is approximately 1A.
National Semiconductor LP2994, LP2995, LP2996, and LP2997; 1.5A continuous current, 3A
transient current linear regulators. The LP2994 comes in an SO8 package, with a nominal
junction resistance of 151 C/W. The LP2995 and LP2996 come in SO-8, PSOP-8 (43 C/W),
and LLP-16 (51 C/W). The LPP2997 comes in SO-8 and PSOP-8. The PSOP-8 maximum
power rating for TA = 50 C, TJ(MAX) = 125C, is 1.7W, so the maximum sustained 1.25V
current from a 2.5V source supply is approximately 1.4A.
Fairchild FAN1655; 2.1A continuous current, 3A transient current linear regulator. The device
package options include; eTSSOP-16 (40 C/W), SOIC-14 (88 C/W), and MLP-8 (34 C/W).
The MLP-8 maximum power rating for TA = 50 C, TJ(MAX) = 125 C, is 2.2W, so the maximum sustained 1.25V current from a 2.5V source supply is approximately 1.8A.
Fairchild FAN6555; 2A continuous current, 3A transient current monolithic switch-mode regulator. The device is packaged in an SOIC-16 (88 C/W). The SIOC-16 maximum power rating
for TA = 50 C, TJ(MAX) = 125 C, is 852mW, so assuming an eciency of 80%, the maximum
output power is 3.4W, and the maximum output current is 2.7A.
NXP Semiconductor (formerly Philips) NE57811, NE57814. The NE57811 is packaged in an
SOT756, the data sheet states a thermal resistance of 16.5 C/W, however, this is for a fairly
large area 4-layer PCB. The junction resistance for a smaller area is closer to 35 C/W. The
NE57814 is packaged in an SOT786-2, with a thermal resistance of 38.5 C/W. The maximum
power rating for TA = 50 C, TJ(MAX) = 125 C, and JA = 38.5 C is 1.9W, so the maximum
sustained 1.25V current from a 2.5V source supply is approximately 1.5A.
The CARMA Board will use a Texas Instruments TPS54x10-series (6A, 8A, or 9A) switch-mode
regulator powered from 3.3V for the 2.5V VDD supply, and a 3A linear-regulator powered from the
2.5V VDD supply for 1.25V VTT supply. The linear regulator will be selected from (in order of
preference); NE57811, NE57814, or FAN1655. The order is based on the VTT load regulation plots.
Device pricing (November 6, 2006);
NE57811S-T (Digikey 568-2331-1-ND) $0.98 each per 100.
NE57814DD-T (Digikey 568-2332-1-ND) $0.78 each per 100.
FAN1655 MLP-8, eTSSOP-16 (Mouser) $1.20 each per 100.
53
CARMA Correlator
December 4, 2006
Design examples
The following sections contain example designs. Some of the example designs are analyzed using
simulation only, while others are analyzed using both simulation and board-level measurement.
6.1
Linear Technology LTC1624 buck converter; 12V to 5V at 3A
Figure 30 shows an example circuit for a Linear Technology LTC1624 buck converter. The circuit
is from Linears SwitcherCAD simulation software. The circuit can be accessed in SwitcherCAD by
clicking on File, Demo SMPS Circuits, and then scrolling down to, and selecting, the LT1624.app
High Eciency SO-8 N-Channel Switching example design. The design operates with an input
supply of 12V, and produces an output of 5V at 3A.
The design in Figure 30 is now analyzed using the LTC1624 data sheet design procedure, along
with the design equations in this document. First we need a design specication;
VIN = 12V
VOUT = 5.0V 125mV, i.e., VOUT = 250mV (5%)
IOUT = 3A (maximum operating current)
f = 200kHz (the LTC1624 uses a xed frequency)
The LTC1624 5V supply design procedure is (p13 [71]);
1. Select the sense resistor;
RSENSE =
100mV
= 33m
3A
(112)
2. Select the inductor and ripple current;

The example schematic uses a 10H inductor (as does the data sheet design example), which
will produce a ripple current of (p13 [71])

VIN VOUT VOUT + VF
IOUT =
fL
VIN + VF

5V + 0.5V
12V 5V
(113)
=
200kHz 10H 12V + 0.5V
= 1.54A
i.e., the ripple current is 51%.
3. Select the high-side MOSFET;
The example schematic uses a Silconix (Vishay) Si4412DY for the high-side MOSFET. The
Si4412DY has an RDS(on) = 29m (typical) and a total gate charge Qg = 16nC. According
to Figure 30, the power dissipation with a 3A load is 174mW. Assuming the MOSFET is
mounted with JA = 50 C/W, and an ambient operating temperature of TA = 50 C, the
junction temperature of the device will be TJ = 59 C.
4. Select the rectier diode;
The example schematic uses an MBRS340 Schottky Power Rectier Diode (available from both
Fairchild and OnSemiconductor). The diode maximum forward voltage, VF = 0.5V, however,
for the 3A buck converter pulses, the typical forward voltage is closer to 0.4V (TA > 25 C)
(see the gures in the OnSemiconductor data sheet). The diode current rating is sucient
54
CARMA Correlator
December 4, 2006
for this converter design. Figure 30 shows the power dissipation with a 3A load is 751mW.
Assuming the diode is mounted with JA = 50 C/W, and an ambient operating temperature
of TA = 50 C, the junction temperature of the device will be TJ = 88 C.
5. Select the input capacitors;
With a duty cycle ofD = (VOUT + VF )/(VIN + VF ) = 0.44, the input capacitor RMS current is
ICIN RMS IOUT D(1 D) = 1.49A. A practical application of this design would need to
use an input capacitor, or multiple input capacitors, that could handle this RMS current. For
example, the pair of 22F input capacitors shown in Figure 30, would need an RMS rating of
at least 0.8A each.
6. Select the output capacitors;
Figure 30 shows two 100F output capacitors, each with an ESR of 50m.
The ripple current in the output capacitors is the due to theripple current in the inductor, the
RMS of which is given by (46), i.e., ICOUT RMS = IOUT / 12 = 0.44A, so the RMS current
through each of the output capacitors is 0.22A.
The output voltage ripple is dominated by the inductor ripple current in the output capacitor
ESR, i.e., VOUT = 1.54A 50m/2 = 39mV.
The voltage transient response for a load current increase is dominated by the output capacitor
ESR, and for a 3A load step will create a dip in the 5V output voltage of VOUT = 3A
50m/2 = 75mV, i.e., a 1.5% decrease.
The voltage transient response for a load current decrease is determined by the load capacitance
value, i.e.,

2
10H
1.54A
+ 52 5 = 71mV
(114)
VOUT =
3A +
200F
2
i.e., a 1.4% increase.
The worst-case output voltage deviation is the sum of the ESR-induced ripple voltage and the
load-current transient voltage, i.e., 114mV or 110mV. The output capacitance is adequate for
this supply.
This design analysis shows that the supply meets the design specications.
Figure 30 indicates that the eciency of the supply is 92.2% for the 5V output at 3A. The bulk
of the power dissipation comes from the rectier diode, MOSFET, and component conduction (I 2 R)
losses. Figures 31 and 32 show the power dissipation of the high-side MOSFET and low-side diode.
The MOSFET dissipates power during the turn-on and turn-o switching edges, and dissipates
power due to conduction losses when the switch is on. The diode dissipates power during highside switch o-time. The power dissipated is proportional to the forward voltage drop of the diode
and the output current. This power dissipation becomes excessive for high-current, and low-output
voltage supplies, so in the synchronous buck converter topology, the low-side diode is replaced with
a low-side MOSFET. The next section analyzes the LTC1625 synchronous buck converter.
55
CARMA Correlator
December 4, 2006
IN
R1
0.033
U1
Vin
6.8K
C4
C2
Boost
C8
22
22
V1
12
C3
M1
VC
ITH
470p
TG
.1
Si4412DY
LTC1624
FB
100p
C1
1000p
SNS
SenseR2
C7
SW
L1
SW
10
GND
D2
MBRS340
OUT
C5
100p
R3
35.7K
R4
11K
Iload
C6
C9
100
100
3000mA
--- Efficiency Report --Efficiency: 92.2%

Input: 16.4W @ 12V
Output: 15.1W @ 5.04V
Ref.
C1
C2
C3
C4
C5
C6
C7
C8
C9
D2
L1
M1
R1
R2
R3
R4
U1
Irms
452mA
0mA
56mA
0mA
0mA
221mA
2mA
452mA
221mA
2226mA
3031mA
2047mA
2047mA
0mA
0mA
0mA
56mA
Ipeak Dissipation
2014mA
0mW
0mA
0mW
1483mA
0mW
0mA
0mW
0mA
0mW
392mA
2mW
170mA
0mW
2014mA
0mW
392mA
2mW
3770mA 751mW
3785mA 184mW
4051mA 174mW
4052mA 138mW
0mA
0W
0mA 416W
0mA 128W
1483mA
29mW
Figure 30: Linear Technology LTC1624 buck converter SwitcherCAD simulation schematic and
eciency report.
56
CARMA Correlator
December 4, 2006
V(SW)
13V
11V
Volts
9V
7V
5V
3V
1V
-1V
V(SNS)-V(SW)
Id(M1)
4.5A
10V
3.5A
8V
2.5A
6V
1.5A
Amps
Volts
12V
4V
0.5A
2V
-0.5A
0V
Id(M1)*(V(SNS)-V(SW))
39W
Watts
29W
19W
9W
-1W
9.0s
9.5s
10.0s
10.5s
11.0s
11.5s
12.0s
12.5s
13.0s
13.5s
14.0s
Figure 31: Linear Technology LTC1624 buck converter high-side MOSFET power dissipation. The
top plot show the switching node voltage, the second shows the voltage across and current through
the MOSFET, and the bottom shows the power dissipation.
V(SW)
1.0V
Volts
0.5V
0.0V
-0.5V
-1.0V
I(D2)
4A
Amps
3A
2A
1A
0A
-1A
abs(I(D2)*V(SW))
2.0W
Watts
1.5W
1.0W
0.5W
0.0W
11.5s
12.0s
12.5s
13.0s
13.5s
14.0s
14.5s
15.0s
15.5s
16.0s
16.5s
Figure 32: Linear Technology LTC1624 buck converter low-side rectier diode power dissipation. The
top plot show the switching node voltage (i.e, the forward voltage drop of the diode below ground),
the second shows the current through the diode, and the bottom shows the power dissipation.
57
CARMA Correlator
6.2
December 4, 2006
Linear Technology LTC1625 synchronous buck converter; 12V to 5V

at 3A
Figure 33 shows an example circuit for a Linear Technology LTC1625 synchronous buck converter.
The circuit is from Linears SwitcherCAD simulation software. The circuit can be accessed in
SwitcherCAD by clicking on File, Switch Selector Guide, and then entering the following requirements (to match the LTC1624 design);
Input specication:
Voltage (Nom): 12V
Voltage (Min): 10V
Voltage (Max): 14V
Output specication:
Voltage: 5V
Maximum current: 3A
Then select the LTC1625 design from the list of controllers. The SwitcherCAD software does not
appear to scale the inductor in the design to the user-specied current rating. The design that is
generated contains a 7.1H inductor, which is appropriate for 30% ripple in a design with a 10A
maximum load current (which is what the list of controllers indicates it is rated for). In Figure 33 the
inductor value is increased to 12.6H to produce a 51% ripple current, to match the ripple current
in the LTC1624 example, and the FCB pin was tied to ground to force continuous mode operation.
The design in Figure 33 is now analyzed using the LTC1625 data sheet design procedure, along
with the design equations in this document. First we need a design specication;
VIN = 12V
f = 150kHz (LTC1625 default frequency)
The LTC1625 5V supply design procedure is [72];
1. Determine the maximum RDS(ON) (sense resistance) and select the MOSFETs (p9, p17 [72]);
RDS(ON)(MAX) =
120mV
= 31m
3A 1.3
(115)
The LTC1625 data sheet provides a gure for selecting Silconix (Vishay) MOSFETs on p9 [72].
The Silconix Si4410 is shown as being appropriate for a 3A design. The Si4410BDY (an
available part number) has an RDS(on) = 16.5m (typical), and a total gate charge Qg = 13nC.
According to Figure 33, the power dissipation for the high-side MOSFET is 119mW, and for
the low-side MOSFET is 74mW. Assuming the MOSFETs are mounted with JA = 50 C/W,
and an ambient operating temperature of TA = 50 C, the junction temperature of the highside MOSFET will be TJ = 56 C, and the junction temperature of the low-side MOSFET will
be TJ = 54 C.
58
CARMA Correlator
December 4, 2006

The ripple current is selected to be 1.54A to match the LTC1624 example, so the inductor
value is

VOUT
VOUT
L=
1
f IOUT
VIN

5V
5V
(116)
=
1
150kHz 1.54A
12V
= 12.6H
3. Select the dead-time rectier diode;
The example schematic uses an 1N5818 Schottky diode (available from OnSemiconductor) to
conduct during the dead-time between high-side and low-side switch-over. Since the diode
conducts only during the dead-time, it only needs to be rated for pulsed operation at the
maximum load current. Figure 33 shows the power dissipation of the diode is 57mW. Assuming
the diode is mounted with JA = 50 C/W, and an ambient operating temperature of TA =
50 C, the junction temperature of the device will be TJ = 53 C.
With a
duty cycle of D = VOUT /VIN = 0.42, the input capacitor RMS current is ICIN RMS
IOUT D(1 D) = 1.48A. A practical application of this design would need to use an input
capacitor, or multiple input capacitors, that could handle this RMS current. For example, the
100F input capacitor shown in Figure 33, would need an RMS rating of at least 1.5A.
Figure 33 shows a 500F output capacitor, with an ESR of 50m.
The ripple current in the output capacitor is given in (46), i.e., ICOUT RMS = IOUT / 12 =
0.44A. The RMS rating of the output capacitor would need to be at least this.
ESR, i.e., VOUT = 1.54A 50m = 77mV.
ESR, and for a 3A load step will create a dip in the 5V output voltage of VOUT = 3A50m =
150mV, i.e., a 3% decrease.
value, i.e.,

2
1.54A
12.6H
VOUT =
+ 52 5 = 36mV
(117)
3A +
500F
2
i.e., a less than 1% increase.
The worst-case output voltage deviation is the sum of the ESR-induced ripple voltage and the
load-current transient voltage, i.e., 227mV or 113mV. The output capacitance is adequate for
this supply. However, using two parallel 100F capacitors each with an ESR of 50m would
improve the regulation (see the LTC1624 example).
This design analysis shows that the supply meets the design specications.
Comparison of the eciency report for the LTC1624 buck converter in Figure 30 with the synchronous buck converter in Figure 33 shows that the replacing the LTC1624 diode with a low-side
MOSFET plus diode reduces that power dissipation component from 751mW to 131mW, i.e., a
59
CARMA Correlator
December 4, 2006
IN
Vin
Vin
C6
100
12
TK
EXTVcc
U1
M1
Run/SS
TG
FCB
SW
Si4410DY
C3
.01
L1
SW
OUT
12.6
C4
Ith
3A
Boost
D1
R1
10K
C2
Iload
500
.22
VC
C1
LTC1625
1N5818
Vprog
INTVcc
C5
2200p
4.7
Vosense
BG
SGND
D2
M2
Si4410DY
1N5818
PGND

Input: 15.5W @ 12V
Output: 15W @ 5V
Ref.
C1
C2
C3
C4
C5
C6
D1
D2
L1
M1
M2
R1
U1
Irms
444mA
0mA
0mA
61mA
55mA
1149mA
36mA
569mA
3031mA
1990mA
2206mA
0mA
67mA
Ipeak Dissipation
794mA
10mW
0mA
0mW
0mA
0mW
1043mA
0mW
914mA
0mW
5924mA
0mW
589mA
2mW
3573mA
57mW
3792mA 114mW
5999mA 119mW
3718mA
74mW
0mA
0W
928mA
77mW
Figure 33: Linear Technology LTC1625 synchronous buck converter SwitcherCAD simulation
schematic and eciency report.
saving of 620mW. The total power dissipated by the LTC1624 circuit is 1.3W, while the total power
dissipated by the LTC1625 is 0.5W, so the improvement in power dissipation in the LTC1625 circuit
is mainly due to the use of a low-side MOSFET.
Figures 34, 35, and 36 show the power dissipation of the LTC1625 circuit high-side MOSFET,
low-side Schottky diode, and low-side MOSFET. Camparison of the LTC1625 Figures 34 and 35 to
the LTC1624 Figures 31 and 32 shows how the low-side MOSFET reduces the low-side diode power
dissipation. In Figure 32 the switching node voltage (top trace) during the high-side o-time is due
to the forward voltage drop of the Schottky diode, whereas in Figure 35 the switching node voltage
near the high-side to low-side switch-over is given by the diode, but during the low-side on time, the
voltage is due to low-side MOSFET conduction, i.e., RDS(ON) IOUT .
60
CARMA Correlator
December 4, 2006
V(SW)
13V
11V
Volts
9V
7V
5V
3V
1V
-1V
V(IN)-V(SW)
Id(M1)
6.5A
12V
5.5A
4.5A
8V
3.5A
6V
2.5A
4V
1.5A
2V
0.5A
0V
-0.5A
Amps
Volts
10V
Id(M1)*(V(IN)-V(SW))
65W
55W
Watts
45W
35W
25W
15W
5W
-5W
6.0s
6.5s
7.0s
7.5s
8.0s
8.5s
9.0s
9.5s
10.0s
10.5s
Figure 34: Linear Technology LTC1625 synchronous buck converter high-side MOSFET power dissipation. The top plot show the switching node voltage, the second shows the voltage across and
current through the MOSFET, and the bottom shows the power dissipation.
V(SW)
Volts
1V
0V
-1V
I(D2)
3.5A
Amps
2.5A
1.5A
0.5A
-0.5A
abs(I(D2)*V(SW))
Watts
2W
1W
0W
8.7s
9.2s
9.7s
10.2s
10.7s
11.2s
11.7s
12.2s
12.7s
13.2s
13.7s
14.2s
Figure 35: Linear Technology LTC1625 synchronous buck converter low-side Schottky diode power
dissipation. The top plot show the switching node voltage, the second shows the current through
the diode, and the bottom shows the power dissipation.
61
CARMA Correlator
December 4, 2006
V(SW)
Volts
1V
0V
-1V
Id(M2)
3.5A
2.5A
Amps
1.5A
0.5A
-0.5A
-1.5A
-2.5A
-3.5A
Watts
-4.5A
10W
9W
8W
7W
6W
5W
4W
3W
2W
1W
0W
8.7s
abs(Id(M2)*V(SW))
9.2s
9.7s
10.2s
10.7s
11.2s
11.7s
12.2s
12.7s
13.2s
13.7s
14.2s
Figure 36: Linear Technology LTC1625 synchronous buck converter low-side MOSFET power dissipation. The top plot show the switching node voltage, the second shows the current through the
MOSFET, and the bottom shows the power dissipation.
62
CARMA Correlator
6.3
December 4, 2006
Fairchild (AN-6005) FAN5069 synchronous buck; 12V to 1.4V at 25A
Fairchild application note AN-6005 [46] contains a detailed analysis of MOSFET loss calculations,
and provides a spreadsheet to use when analysing MOSFETs for use in synchronous buck converter designs. The spreadsheet contains additional gures that explain how to interpret MOSFET
datasheets. The default design used in the spreadsheet is based on the FAN5069 synchronous buck
controller [64], with the following supply specications;
VIN = 12V nominal, 10V to 15V range
f = 200kHz
Note that the output voltage ripple specication was added here, as the intended use of the AN-6005
spreadsheet is for MOSFET selection, so it does not generate capacitor requirements.
The FAN5069 1.4V supply design procedure is;
1. Select the operating frequency;
The minimum clock frequency of 200kHz is selected by leaving the R(T) pin disconnected
(p11 [64]).
2. Select the R(RAMP) resistor (p11 [64]);
RRAMP (k) =
VIN 1.8
= 810k
6.3 108 f
(118)

The inductor required for 30% ripple current is;
L=
1.4V
200kHz 0.3 25A

1.4V
1
= 0.8H
12V
(119)
which gives a ripple current of 7.73A.

4. Select the high-side and low-side MOSFETs;
The AN-6005 spreadsheet selects a Fairchild FDD3706 MOSFET for the high-side switch, and
two FDD8896 MOSFETs for the low-side switch. The eciency of the converter with this
selection of MOSFETs, and other options, is analyzed shortly.
The FAN5069 controller uses adaptive deadtime control, which minimizes body-diode conduction during high-side to low-side switch-over, so an external Schottky diode is not required
(p11 [64]).
5. Select the current limit resistor (p12 [64]);
The FDD8896 has RDS(ON) = 5.7m (typical), so the on-resistance of the pair of low-side
MOSFETs will be half this. The current limit resistor required is then;

1.6
1.8
VOUT 33.32 1011
IOUT RDS(ON) 103 + 1
RILIM (k) = 128 +

1.43
VIN
f RRAMP

1.8
1.4V
33.32 1011
= 128 + 1.12 25A 2.9m 103 + 1
12V
200kHZ 810k
(120)
= 234k
63
CARMA Correlator
December 4, 2006

With a duty
cycle of D = VOUT /VIN = 0.12, the input capacitor RMS current is ICIN RMS
IOUT D(1 D) = 8.1A. A practical application of this design would need to use multiple
input capacitors to handle this level of RMS current.
A multi-phase buck converter has lower input and output RMS currents relative to an equivalently rated single-phase design, so a multi-phase converter may be a better solution for a
supply requiring 25A output current.
The ripple current in the output capacitor is given by (46), i.e., ICOUT RMS = IOUT / 12 =
2.23A. The output capacitor(s) must be rated to handle this level of RMS current.
ESR. To maintain a ripple voltage of 50mV, the output capacitance ESR would need to be
RCOUT = 50mV/7.73A = 6.5m.
ESR, and for a 25A load step will create a dip in the 1.4V output voltage of VOUT =
25A 6.5m = 163mV, i.e., a 12% decrease.
The worst-case voltage dip is the sum of half the ripple voltage plus the transient voltage. To
keep the worst-case voltage dip within the 50mV specication, the ESR needs to be RCOUT =
50mV/28.9A = 1.7m; the ripple voltage contribution is then 13mV.
The capacitance value required to keep the voltage transient response due to a load current
decrease below 50mV is

2
7.73A
0.8H 25A +
2
COUT =
= 6350F
(121)
(1.4V + 50mV 13mV)2 1.4V2
This supply would require ten 680F output capacitors each with an ESR of 17m, and a
current rating of 0.3A, or seven 1000F capacitors with an ESR of 12m, and a current rating
of 0.4A. Sanyo TPE-series POSCAP capacitors would be appropriate for this design.
The FAN5069 data sheet discusses the MOSFET selection criteria on p14 [64], and refers the
reader to Fairchild AN-6005 [46]. The FAN5069 data sheet also has a good section on switching-node
snubber circuit design and component selection (p15 [64]).
The AN-6005 [46] analysis equations were implemented using a MATLAB script. The AN-6005
equations do not include scaling for multiple high-side and low-side MOSFETs, whereas the spreadsheet does. The spreadsheet was consulted to add support in the MATLAB script for multiple
low-side MOSFETs, and was consulted to resolve any ambiguities in the AN-6005 equations (eg.
whether an equation needed to use a high-side or low-side MOSFET parameter). The MATLAB
script uses a main structure, a design, that contains the design requirements and three structure members that are themselves structures; a controller structure, and highside and lowside
mosfet structures. The design structure is passed as an argument to the various power calculation
functions. Dierent controllers are analyzed by changing the design.controller setting, while
dierent MOSFETs are analyzed by changing the design.highside and design.lowside settings
to dierent mosfet structures. Tables 1 and 2 show the controller and MOSFET structure member
parameters.
The FAN5069 controller, FDD3706 high-side MOSFET, and FDD8896 low-side MOSFET parameters are shown in Tables 4 and 5. The parameters in the two tables match the parameters
in the AN-6005 spreadsheet, and in the device data sheets (if a dierence was found, the AN-6005
64
CARMA Correlator
December 4, 2006
spreadsheet value was used to assist in comparing the MATLAB output to the spreadsheet output).
Table 5 also shows the parameters for high-side and low-side MOSFETs from International Rectier.
Figure 37 shows an eciency plot of the FAN5069 with an FDD3706 high-side MOSFET, and
pair of FDD8896 MOSFETs for the low-side. The plot can be compared to that generated by the
AN-6005 spreadsheet; the spreadsheet has a few minor errors relative to the AN-6005 equations, but
after they are corrected, the plots match. Note that the eciency plot does not include conduction
losses in the inductor, capacitors, or controller. For example, a 25A inductor such as the 0.62H
TDK SPM-series (SPM12550T-R62M300) (used on the TI TPS40090EVM-001 board) has a DCR
of 1.75m, so its conduction loss is approximately 1.1W. The 1.4V at 25A supply has an output
power of 35W, so at 90% eciency with respect to the MOSFETs only, it dissipates 3.9W. Adding
the inductor conduction dissipation decreases the eciency to 87.7%. Adding other conduction
components reduces the eciency further still. The point of this comment, is that the AN-6005
spreadsheet is intended for comparing the MOSFET dissipation, and its eciency plots do not
reect the nal power supply eciency.
Figure 38 shows an eciency plot for the FAN5069 with an IRF6617 high-side MOSFET, and
an IRF6618 low-side MOSFET. The plot looks virtually identical to Figure 37. Figure 39 overlays
the eciency plots of the two designs to show that using the IRF MOSFETs gives a slight eciency
improvement at higher loads. Table 6 gives a more detailed break-down of the power dissipation
components (the MATLAB script outputs this information, as does the AN-6005 spreadsheet). From
the table its clear that the high-side MOSFET performance is comparable (38mW dierence in total
high-side power dissipation), and that the eciency gain of the design that uses the IRF MOSFETs
comes from the smaller low-side dissipation.
Table 6 also contains estimates of the MOSFET junction temperatures. The dierence between
the temperatures estimated for each design is due to; power dissipation, junction-to-ambient resistance (JA in Table 5), and the number of low-side MOSFETs. The JA of each MOSFET can be
improved by heatsinking, so the results of Table 6 help to select the MOSFET, and then whether it
needs an improved heat-sink method, eg., the IRF MOSFET data sheets indicate that a minimum
footprint with clip-on heatsink has a JA = 20 C/W.
65
CARMA Correlator
December 4, 2006
Table 4: FAN5069 controller parameters

Parameter
Value
Name
VHS DRIVER
RHS DRIVER PULL UP
RHS DRIVER PULL DOWN
FAN5069
4.8V
1.8
1.8
VLS DRIVER
RLS DRIVER PULL UP
RLS DRIVER PULL DOWN
5V
1.8
1.2
tDELAY(R)
tDELAY(L)
25ns
10ns
Table 5: FAN5069 external MOSFET parameters

Parameter
Name
RDS(on) (25 C)
T
RGATE
VSP
VTH
CISS0
CISS
COSS
CRSS
QGS
QGD
QG(SW)
QG
MOSFET
FDD3706
8.0m
0.004
1.5
1.8V
0.9V
2300pF
1882pF
430pF
201pF
3.7nC
4.0nC
5.0nC
16nC
FDD8896
5.7m
0.004
2.1
2.6V
1.7V
3200pF
2525pF
490pF
300pF
6.9nC
9.8nC
13.3nC
24nC
IRF6617
7.9m
0.0043
1.0
3.0V
1.83V
1500pF
1300pF
430pF
160pF
4.1nC
4.0nC
5.0nC
11nC
IRF6618
2.2m
0.0035
1.0
2.8V
1.64V
6100pF
5640pF
1260pF
570pF
16.0nC
15.0nC
19.0nC
43nC
VF
QRR
0.8V
18nC
0.8V
14nC
0.78V
46nC
0.81V
46nC
JA
40 C/W
40 C/W
58 C/W
45 C/W
66
CARMA Correlator
December 4, 2006
Efficiency for Vout = 1.4V at f = 200kHz
100
95
Efficiency
90
85
80
Vin=10V
Vin=12V
75
70
0
Vin=14V
10
15
Output current
20
25
Figure 37: FAN5069 eciency with an FDD3706 high-side MOSFET, and pair of FDD8896 MOSFETs for the low-side. Note that the plot does not include conduction losses in the inductor,
capacitors, or controller.
100
95
Efficiency
90
85
80
Vin=10V
Vin=12V
75
70
0
Vin=14V
10
15
Output current
20
25
Figure 38: FAN5069 eciency with an IRF6617 high-side MOSFET, and an IRF6618 low-side
MOSFET.
67
CARMA Correlator
December 4, 2006

100
95
Efficiency
90
85
80
75
70
0
10
15
Output current
20
25
Figure 39: FAN5069 eciency of the three FDD MOSFETs versus the two IRF MOSFETs at 12V
input supply; the IRF MOSFETs show a 1% improvement in eciency under high loads.
68
CARMA Correlator
December 4, 2006
Table 6: FAN5069 design power dissipation

Parameter
Design
FDD MOSFETs IRF MOSFETs
Design parameters
Input voltage
Output voltage
Output current
Switching frequency
12.0V
1.4V
25.0A
200.0kHz
12.0V
1.4V
25.0A
200.0kHz
High-side power dissipation

High-side FET type
High-side switching
High-side output capacitance
High-side diode reverse recovery
High-side gate charging
High-side total switching
High-side conduction
High-side total
FDD3706
0.440W
0.006W
0.067W
0.015W
0.529W
0.762W
1.291W
IRF6617
0.373W
0.006W
0.110W
0.011W
0.500W
0.829W
1.329W
High-side junction temperature

High-side on-resistance
101.6C
10.5m
127.1C
11.4m
Low-side power dissipation

Low-side FET type
Low-side switching
Low-side gate charging
Low-side diode deadtime
Low-side total switching
Low-side conduction
Low-side total
FDD8896
0.103W
0.048W
0.159W
0.310W
2.008W
2.319W
IRF6618
0.097W
0.043W
0.157W
0.297W
1.683W
1.980W
Low-side dissipation per FET

Low-side junction temperature
Low-side on-resistance
1.159W
96.4C
7.3m
139.1C
3.1
Total MOSFET dissipation

Total power
Eciency
3.609W
35.000W
90.7%
3.309W
35.000W
91.4%
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6.4
December 4, 2006
Altera Stratix II DSP Kit
The Altera DSP Development Kit, Stratix II Edition (DSP-DEVKIT-2S60) contains a Stratix II
EP2S60 FPGA. The board contains four supplies that are generated using buck converters; 1.2V,
3.3V, 5V, and 8V. The 1.2V, 3.3V, and 5V supplies use Linear LTC1778 synchronous buck converters
[73], while the 8V supply uses a National Semiconductor LM2678 buck converter. The FPGA core
supply is 1.2V, and the FPGA I/O banks are all powered from 3.3V. The 3.3V, 5V, and 8V supplies
are used for powering the peripherals on the DSP kit. Information on the DSP kit can be found
online at;
http://www.altera.com/products/devkits/kit-dev_platforms.jsp
http://www.altera.com/products/devkits/altera/kit-dsp-2S60.html
The second link contains links to the board data sheet, user guide, schematics (PDF), and PCB
(gerber) les. The CD-ROM delivered with the kit also contains the schematic in OrCAD Capture
format. The OrCAD Capture components are dened with the part numbers of the capacitors, and
inductors, making it possible to simulate the parasitic components of these devices, i.e., the ESR of
the capacitors, and the DCR of the inductors.
The following subsections analyze the 1.2V supply in detail, and comment on the implementation
dierences between that supply and the similarly congured LTC1778s used for the 3.3V and 5V
supplies. The 1.2V supply analysis includes; (1) following the design procedure outlined in the
LTC1778 datasheet, augmented with the design equations in this document, (2) power eciency
analysis as per Fairchild AN-6005, (3) SwitcherCAD simulation, and (4) board-level measurements.
6.4.1
LTC1778 1.2V supply: Design; 16V to 1.2V at 8A
The design specication for the Stratix II EP2S60 1.2V core supply are;
VIN = 16V
VOUT = 1.20V 50mV, i.e., VOUT = 100mV
f = 120kHz
The LTC1778 1.2V design procedure is;
1. Set the operating frequency;
The RON resistor sets the operating frequency (p17 [73]);
RON =
1.2V
= 1.4M
0.7V 120kHz 10pF
(122)
The DSP kit uses a 1.4M resistor.

2. Select the inductor for 40% ripple current;
1.2V
L=
120kHz 0.4 8A

1.2V
1
= 2.9H
16V
(123)
The DSP kit uses a 2.8H inductor.

3. MOSFET selection;
The DSP kit uses Fairchild FDS6680A MOSFETs for both the high-side and low-side switches.
The devices have an RDS(on) = 13m at VGS = 4.5V, and a gate charge of Qg = 16nC (typical).
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December 4, 2006
4. Current limit setting;

The nominal voltage drop across the low-side MOSFET at full load current, assuming a 30%
increase in on-resistance, is
VSNS(NOM) = 8A 1.3 13m = 135mV
(124)
The DSP kit ties the VRNG pin to IN T VCC , so the nominal sense voltage is 140mV, with
current limit occurring at 186mV, i.e., 11A.
5. Input capacitance selection/analysis;
The DSP kit has one 68uF capacitor on each of the 1.2V, 3.3V, and 5V supply schematic
blocks. Each capacitor is a Kemet T495-series capacitor (T495X686K025ASE200), with an
ESR of 200m, and a ripple current rating of 0.8A (85 C). The input capacitors are in parallel,
so the total input capacitance is 204F and the eective ESR is 67m.

The AC ripple current through the input capacitance is ICIN RMS IOUT D(1 D) = 2.1A,
so the RMS current through each of the input capacitors is 0.7A. Since the input capacitors
need to handle the RMS current from all three supplies, they are under-rated for full-load
conditions.
The current through the input capacitors has a peak-to-peak value of IOUT , so the ripple
voltage due to the input capacitor ESR has a peak-to-peak voltage of VIN = 533mV.
6. Output capacitance selection/analysis;
The DSP kit has four 100F capacitors on the output of the 1.2V supply. Each capacitor is
an AVX TPS series capacitor (TPSD107K010R0065), with an ESR of 65, a ripple current
rating of 1.3A (85 C), and a voltage ripple rating of 90mV (85 C).
The ripple current in the output capacitors is given by (46), i.e., ICOUT RMS = IOUT / 12 =
0.92A, so the RMS current through each of the output capacitors is 0.23A.
ESR, i.e., VOUT = 0.4 8A 65m/4 = 52mV.
ESR, and for an 8A load step will create a dip in the 1.2V output voltage of VOUT =
8A 65m/4 = 130mV, i.e., an 11% decrease to 1.07V. This decrease exceeds the 1.15V
minimum operating rating of VCCINT.
value, i.e.,

2
2.8H
3.2A
+ 1.22 1.2 = 244mV
(125)
VOUT =
8A +
400F
2
The load current decrease causes the output voltage to increase by 20% to 1.44V. Note that
this exceeds the 1.25V maximum operating rating of VCCINT, and is a large fraction of the
50% over-voltage needed to reach the 1.80V absolute maximum rating of VCCINT.
Note that the output ripple voltage and the transient voltages are cumulative, so the worstcase deviation during a transient is as large as the worst-case ripple voltage plus the transient
voltage.
This analysis shows that the selection of output capacitance has excessive ESR, and has insufcent capacitance value. A total ESR of 6m, and total capacitance of 2100F is required to
maintain the output voltage within 1.20V 50mV during 8A load transients. If the DSP kit
output capacitance was replaced with capacitors from the AVX TPS series, in a compatible
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December 4, 2006
package (D or E), the lowest ESR option is the 4V, 680F, 60m, 1.2A (85 C) RMS current.
Four of these capacitors in parallel, give an ESR of 15, a total capacitance of 2720F, a load
current increase transient voltage dip of 120mV, and load current decrease transient voltage
increase of 39mV. So the dip is not within specication, but at least its smaller. Additional
paralleled capacitors would be required to meet the voltage regulation specication.
6.4.2
LTC1778 1.2V supply: Simulation
Figure 40 shows a schematic of the DSP kit 1.2V supply drawn using Linear Technologys SwitcherCAD SPICE simulator. The gure also shows the eciency report generated for the circuit. The
DSP kit allows the LTC1778 to operate in discontinuous mode (the FCB pin is tied to INTVCC),
whereas the SPICE circuit in Figure 40 forces the LTC1778 to operate in continuous mode (FCB
tied to ground). This modication was required, as the LTC1778 SPICE model does not operate
correctly in discontinuous mode.
The constant load current (I1) in Figure 40 was replaced with a piecewise linear (PWL) load
current that was congured to draw no current until 3ms, then draw 8A for 1ms, and then no
current. This models the nominal turn-on of the supply under light load, followed by a transient due
to FPGA operation. Figure 41 shows the transient response of the circuit, while Figure 42 shows a
magnied view of the load transients; the PWL current transient edges were timed to coincide with
the ripple current minimum or maximum, to create worst-case transients. Figure 41 shows that the
1.2V supply ramps up in 200s, so meets the FPGA turn-on rate of between 100s and 100ms. The
output ripple voltage is 58mV, which matches the expected ripple based on output capacitor ESR.
The 8A transient causes a 195mV voltage dip and a 270mV voltage peak. Both of these values
exceed the theoretical calculation of the peak-to-peak transient, since the value measured from the
simulation is the sum of both ripple voltage and voltage transient. The theoretical values for the
worst-case transients, including the ripple voltage, are a 182mV voltage dip, and a 296mV voltage
peak. Hence, the calculated values match closely with the simulated values.
The conclusion drawn from the simulation is that the circuit operation matches the theoretical
calculations, and conrms that the transient response of the circuit does not meet the VCCINT
supply requirement.
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December 4, 2006
Altera Stratix II DSP Kit (EP2S60) 1.2V VCCINT Supply

.tran 5m steady startup
IN
R8
1.4Meg
R2
2Meg
R1
4.7
C10
RUN
EXTVcc
TG
FCB
SW
LTC1778
Ith
C5
470p
68p
Pgood
R5
100K
SW
L1
OUT
2.8
D1
CMDSH2-3
INTVcc
Vrng
Q1
FDS6680A
C1
.22
Boost
Run/SS
R4
C4 10K
.1
Vin
Ion
C3
0.01F
200
C9
U1
V1
Rser=0.1
16V
Q2
FDS6680A
D2
MBRS340
R7
1K
C11
C6
3300p
400
I1
8A
load
BG
FB
R6
2K
PGND
GND
C2
4.7

Input: 11.6W @ 15.9V
Output: 9.6W @ 1.2V
Ref.
C1
C2
C3
C4
C5
C6
C9
C10
C11
D1
D2
L1
Q1
Q2
R1
R2
R4
R5
R6
R7
R8
U1
Irms
64mA
74mA
0mA
0mA
0mA
905mA
15mA
1356mA
0mA
51mA
707mA
8051mA
2429mA
7627mA
18mA
0mA
0mA
0mA
0mA
0mA
0mA
69mA
Ipeak Dissipation
714mA
0mW
1372mA
0mW
0mA
0mW
0mA
0mW
0mA
0mW
1611mA
14mW
65mA
0mW
5088mA 129mW
0mA
0mW
715mA
3mW
7991mA
47mW
9611mA 292mW
9475mA 752mW
9569mA 700mW
59mA
1mW
0mA
94W
0mA
3W
0mA
0W
0mA 320W
0mA 160W
0mA 166W
989mA 106mW
Figure 40: Altera Stratix II DSP Kit 1.2V supply SwitcherCAD schematic and eciency report.
73
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December 4, 2006
V(OUT)
1.4V
1.2V
1.0V
Volts
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
I(I1)
9A
8A
7A
Amps
6A
5A
4A
3A
2A
1A
0A
0.0ms
0.5ms
1.0ms
1.5ms
2.0ms
2.5ms
3.0ms
3.5ms
4.0ms
4.5ms
5.0ms
Figure 41: Altera Stratix II DSP Kit 1.2V supply transient response. The supply ramps up in 200s,
and has an output ripple voltage of 58mV. During an 8A load transient, the peak-to-peak transient
when the load increases is 195mV, and when it decreases is 270mV.
V(OUT)
1.30V
1.25V
Volts
1.20V
1.15V
1.10V
1.05V
1.00V
2.90ms
2.92ms
2.94ms
2.96ms
2.98ms
3.00ms
3.02ms
3.04ms
3.06ms
3.08ms
3.10ms
4.02ms
4.04ms
4.06ms
4.08ms
4.10ms
V(OUT)
1.5V
Volts
1.4V
1.3V
1.2V
1.1V
3.90ms
3.92ms
3.94ms
3.96ms
3.98ms
4.00ms
Figure 42: Altera Stratix II DSP Kit 1.2V supply transient response; magnied view of the 195mV
and 270mV transients.
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December 4, 2006
Table 7: LTC1778 SwitcherCAD and Fairchild AN-6005 power analysis

Component
SwitcherCAD
AN-6005
192mW
14mW
292mW
752mW
700mW
47mW
106mW
2.10W
9.60W
11.70W
336mW
14mW
292mW
339mW
762mW
63mW
5mW
1.81W
9.60W
11.41W
82.1%
84.1%
Input capacitor
Output capacitor
Inductor
High-side MOSFET
Low-side MOSFET
Schottky diode
Controller
Total Dissipation
Output Power
Total Power
Eciency
6.4.3
Note
ESR = 70m
ESR = 17m
DCR = 4.5m
LTC1778 1.2V supply: Power Analysis
Table 7 shows the power dissipation of the components in the 1.2V supply as determined by the
eciency report in Figure 40 versus the theoretical calculations in this document, and in Fairchild
AN-6005. Comments on the simulation versus calculations are;
Input capacitor; the power dissipation is due to conduction (I 2 R) losses in the capacitor ESR.
The calculation is larger than the simulation, since the calculation assumes the full RMS
current is sourced by the input capacitors, whereas in the simulation some of the RMS is
sourced from the input supply.
Output capacitor; conduction (I 2 R) losses.
Inductor; conduction (I 2 R) losses.
High-side MOSFET; the dierence between the simulation and calculation is discussed shortly.
Low-side MOSFET; the low-side calculation includes gate-switching losses (16nC switch with
5V at 120kHz, 48mW), so the calculation excluding that loss is 714mW, which is close to the
simulation result.
Schottky diode; the dierence is due to the deadtime estimate verus the simulation model.
Controller; the simulation includes the gate drive current with the controller dissipation, i.e.,
about 96mW for both drivers, whereas the calculation is just the quiescent power of the device.
The largest dierence between the simulation and calculation occurs with the high-side MOSFET
power dissipation estimate. The power dissipation of the MOSFET consists of switching losses and
conduction losses. At a total power dissipation of say 700mW, with JA = 50 C/W, TA = 50 C
and RDS(on) = 9.9m, the junction temperate would be TJ = 85 C, and the conduction loss would
2
D 1.24 RDS(on) = 59mW, so 641mW would be due to switching losses, i.e., for this
be IOUT
particular design, switching losses dominate the high-side switch power dissipation.
Figure 43 shows the high-side switching waveform with an 8A load. The top plot shows the
voltage on the switching node, the middle plot shows the high-side MOSFET drain current and
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December 4, 2006
V(SW)
18V
Volts
14V
10V
6V
2V
V(IN)-V(SW)
18V
Id(Q1)
10A
9A
8A
7A
6A
5A
4A
3A
2A
1A
0A
-1A
Volts
14V
10V
6V
2V
-2V
Amps
-2V
Id(Q1)*(V(IN)-V(SW))
130W
110W
Watts
90W
70W
50W
30W
10W
-10W
3.2070ms
3.2072ms
3.2074ms
3.2076ms
3.2078ms
3.2080ms
3.2082ms
3.2084ms
Figure 43: Altera Stratix II DSP kit 1.2V supply simulated switching waveforms. The top plot shows
the voltage on the switching node, the middle plot shows the high-side MOSFET drain current and
drain-to-source voltage, and the bottom plot shows the power dissipated in the MOSFET.
drain-to-source voltage, and the bottom plot shows the power dissipated in the MOSFET. Note
how the power dissipation occurs in triangular spikes during each switching edge. The peak of the
spikes is approximated IOUT VIN = 128W, the extent of the base of each spike is about 40ns, so the
average power dissipation in each 7.3s switching period (the simulation switching period is 137kHz)
is 128W 40ns/7.3s = 701mW, i.e., close to the simulation value. The AN-6005 calculations for
the switching times are 17ns and 10ns respectively, and the switching frequency was 120kHz (8.3s
period), so the calculation result is closer to 128W27ns/7.3s = 416mW, than it is to the simulation
value. Measurement on the DSP kit of the switching node waveform indicated a switching time of
10ns and 20ns for the rising and falling edges respectively, i.e., they were closer to the AN-6005
calculations than to the simulation values.
If the worst-case dissipation of the top and bottom MOSFETs is considered to be 760mW, then
assuming a JA = 50 C/W, the junction temperature of each device would reach about 88 C. If the
maximum desired junction temperature was 105 C, then JA would need to be less than 72 C/W.
The FDS6680A data sheet indicates that JA = 50 C/W when the device is mounted on 1in2 of 2oz
copper, and JA = 105 C/W when the device is mounted on a minimum sized footprint of 0.04in2
of 2oz copper. The DSP kit mounts the FDS6680A devices on minimal sized footprints, and does
not appear to contain additional vias to internal planes to improve thermal dissipation. Its likely
that under high-load conditions the DSP kit MOSFETs would get hot.
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6.4.4
December 4, 2006
LTC1778 1.2V supply: Measurements
Figure 44 shows the DSP kit 1.2V power-on waveform. The waveform violates the Stratix II
datasheet requirement of a monotonic power-on waveform, the ramp-up time violates the 100s
minimum ramp-time, the overshoot to 1.75V violates the VCCINT maximum of 1.25V, and the
overshoot is close to the VCCINT absolute maximum rating of 1.80V. These problems were caused
by the DSP kit wiring of its three terminal on/o switch. The center contact of the switch connects
to the schematic POWER_ON signal that in turn connects to the three LTC1778 RUN/SS pins. The
POWER_ON signal has a 2M pull-up to the input supply. The switch o-position shorts the center
terminal, i.e., POWER_ON, to ground, which disables the supplies. The switch on-position connects
the center terminal to the soft-start capacitor. However, by the time the user slides the mechanical switch from the o-position to the on-position, connecting the POWER_ON net to the soft-start,
POWER_ON has already been pulled up, and the supplies enabled! Figure 45 shows the simulated
transient response without a soft-start capacitor. The solution on the DSP kit is to short the switch
center terminal to the on-terminalpermanently connecting the soft-start capacitor to the POWER_ON
signal. When the switch is in the o position, the POWER_ON signal is grounded (the terminals of
the soft-start capacitor are both shorted to ground), and when the switch is moved away from the
o position, the POWER_ON signal starts to rise with an RC time-constant determined by the pull-up
resistor and soft-start capacitor. With the soft-start capacitor connected to the POWER_ON net, the
1.2V, 3.3V, and 5V power supplies ramp-up monotonically, with ramp times of 120s, 200s, and
250s respectively.
Figure 46 shows the 1.2V supply gate driver waveforms. The high-side gate drive pulse amplitude
is about 20V (16V input supply plus 5V boosted gate drive), while the low-side gate drive pulse
amplitude is 5V. The high-side gate is on for about 0.9s, the low-side gate is on for about 7.8s,
the period of the waveform is about 33s (30kHz switching frequency), so the gates are both o for
about 24.3s. The ringing observed on the high-side gate drive, when the low-side switches o, is
due to the ringing on the switching-node; the high-side gate drive signal is boosted relative to the
switching-node. The switching-node ringing is due to the RLC tank circuit created by the output
inductor and the MOSFET capacitances. This is a typical feature of a buck converter operating in
discontinous-mode.
Figure 47 shows the 1.2V supply gate driver waveforms when the supply was loaded with an
additional 2A resistive load. The additional load forces the buck controller to operate in continuous
mode. Figure 47 was captured with the same 5s timebase setting as Figure 46 to emphasise that
the LTC1778 operating frequency depends on operating conditions. The high-side pulse width is
0.7s, the low-side pulse width is 7.4s, the period is 8.2s (121kHz). Figures 48 and 49 show
zoomed views of the gate drive transitions. During the delays between the gate drive signals, the
external Schottky diode conducts. Probing the switching node relative to the high-side gate drive
showed about 40ns of conduction during the low-side to high-side transition, and an imperceptable
amount during the high-side to low-side transition (imperceptable relative to the voltage drop due
to RDS(on) at that time). The low frequency of operation, and low delays between gate drives means
that power dissipation due to Schottky diode conduction is small.
Figures 50 and 51 show the 1.2V output ripple voltage for minimal load (the default FPGA
conguration), and for a 2A load (resistive). The trace is centered on the 1.2V nominal output.
Under light-load conditions, the supply ripple is +50mV to -20mV, i.e., the supply barely meets the
regulation requirements of the FPGA. A load transient caused by the transition to full load, or from
full load back to an idle state would cause an output voltage outside of the Stratix II specication.
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December 4, 2006
Figure 44: Altera Stratix II DSP kit 1.2V supply power-on waveform.
V(OUT)
1.6V
1.4V
1.2V
Volts
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
0s
50s
100s
150s
200s
250s
300s
350s
400s
450s
500s
Figure 45: Altera Stratix II DSP Kit 1.2V supply power-on simulation, with no soft-start capacitor.
Note that the simulation is operating in continuous mode, so the ripple voltage frequency is higher
than on the DSP kit.
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December 4, 2006
Figure 46: Altera Stratix II DSP kit 1.2V high-side and low-side gate drive waveforms for the default
conguration (minimal load current). The buck controller is operating in discontinuous mode.
Figure 47: Altera Stratix II DSP kit 1.2V high-side and low-side gate drive waveforms for the default
conguration plus a 2A resistive load. The buck controller is operating in continuous mode.
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December 4, 2006
Figure 48: Altera Stratix II DSP kit 1.2V high-side and low-side gate drive waveforms (2A load);
low-side o to high-side on transistion showing a 50ns delay.
Figure 49: Altera Stratix II DSP kit 1.2V high-side and low-side gate drive waveforms (2A load);
high-side o to low-side on transistion showing a 25ns delay.
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Figure 50: Altera Stratix II DSP kit 1.2V output ripple (minimal load).
Figure 51: Altera Stratix II DSP kit 1.2V output ripple (2A load).
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December 4, 2006
Figures 52 and 53 show the input ripple voltage measured on an input voltage pin on the highside MOSFET (Q5 pin 8) of the 1.2V supply for minimal load (the default FPGA conguration),
and for a 2A load (resistive). The top trace in each gure is the switching-node waveform, while the
bottom trace is the input ripple. Because the DSP kit has three LTC1778 generating 1.2V, 3.3V,
and 5V, there are multiple input voltage dips associated with high-side driver on-time. The voltage
dips are about 100mV to 200mV each. The DSP kit uses three Kemet T495-series 68F capacitors
with 200m ESR each (so RCIN 67), with a 2A output load, the input voltage ripple should be
approximately V = IOUT RCIN = 133mV, which is slightly smaller than the voltage dips seen in
Figure 53.
The voltage spikes seen on the input ripple traces, are due to scope pickup, and to high current
edge rates in parasitic inductances causing voltage spikes (proportional to Ldi/dt). High-frequency
ceramic decoupling capacitors should always be placed near the switching input node of a buck
converter. The DSP kit layout for the input bulk and high-frequency decoupling is incorrect; the
capacitors are connected to the high-side MOSFET using vias, and internal traces. The capactors
should all have been located on a low-inductance wide copper pour with all components on the same
side of the PCB.
TODO: Load transient test. Come up with an FPGA conguration that consumes at lot of VCCINT, eg. a shift-register that starts loaded with 0x55555555, and shifts on every clock. Create N
of these and wire them as a big serial shift register so they dont get synthesized away, i.e., in one
mode theyre N 32-bit shift registers, in another mode theyre one 32N-bit shift register.
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Figure 52: Altera Stratix II DSP kit 1.2V switching-node and input ripple (minimal load).
Figure 53: Altera Stratix II DSP kit 1.2V switching-node and input ripple (2A load).
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6.4.5
December 4, 2006
LTC1778 3.3V and 5V supplies
The components used in the 3.3V and 5V supplies are virtually identical to the 1.2V supply components; the dierence being the voltage-set resistors, and a lter resistor on the 5V supply. Identical
components were probably selected to reduce the bill-of-materials.
The (possible) design specication for the DSP kit 3.3V and 5V supplies are;
VIN = 16V
V3.3V = 3.3V 165mV, i.e., V3.3V = 330mV (Stratix II VCCIO requirement)
V5V = 5.0V 250mV, i.e., V5V = 500mV (10%)
The LTC1778 3.3V and 5V supply design procedure is;
The DSP kit uses RON = 1.4M for each of the 1.2V, 3.3V, and 5V supplies. The use of the
xed RON value results in supply operating frequencies that are linearly proportional to the
output voltage via
f = VOUT 102kHz.
(126)
i.e., f (1.2V) = 122kHz, f (3.3V) = 337kHz, and f (5V) = 510kHz.

2. Select the inductor for 40% ripple current;
The 3.3V and 5V supplies both use the same 2.8H inductor as was used in the 1.2V supply.
Since the three supplies use the same component values, the ripple current in each supply
diers only by the duty cycle of the supply via

VOUT
VOUT
VOUT
IOUT =
= 3.5A 1
.
(127)
1
fL
VIN
VIN
i.e., IOUT (1.2V) = 3.2A, IOUT (3.3V) = 2.8A, IOUT (5V) = 2.4A, So assuming the 3.3V
and 5V supplies were designed for 4A loads, the ripple current in the 3.3V supply is 70%, and
in the 5V supply is 60%.
3. MOSFET selection;
The DSP kit uses Fairchild FDS6680A MOSFETs for both the high-side and low-side switches.
The devices have an RDS(on) = 13m at VGS = 4.5V, and a gate charge of Qg = 16nC (typical).
4. Current limit setting;
The current limit is setup the same as the 1.2V supply, i.e., 11A. However, its unlikely that
the 3.3V and 5V supplies were intended to be operated at this load, so the current limit is
eectively disabled.
5. Input capacitance selection/analysis;
See the discussion on input capacitance for the 1.2V design; the RMS current rating on the
input capacitance is insucient.
6. Output capacitance selection/analysis;
The 3.3V and 5V supplies each use four 100F capacitors, as used on the 1.2V supply. Per
the 1.2V analysis, the ripple current rating of the output capacitors is sucient for the 0.81A
and 0.69A ripple current in the 3.3V and 5V supplies.
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December 4, 2006
ESR, i.e., V3.3V = 2.8A 65m/4 = 46mV, and V5V = 2.4A 65m/4 = 39mV.
The voltage transient response for a 4A load current increase will create a dip in the output
voltage of V3.3V/5V = 4A 65m/4 = 65mV, i.e., a dips of less than 2% on the 3.3V and
5V supplies.
The transient response for a load current decrease is determined by the load capacitance value,
i.e.,

2
2.8H
2.8A
V3.3V =
+ 3.32 3.3 = 31mV
(128)
4A +
400F
2
and

V5V =
2.8H
400F

2
2.4A
+ 52 5 = 19mV
4A +
2
(129)
The sum of the ripple current and the transient voltages is within specication for both supplies.
SwitcherCAD simulation of the two supplies gave voltage and current ripple results close to the
theoretical calculations. The 3.3V at 4A supply had an eciency of 89.2% while the 5V at 4A
supply had an eciency of 89.9%. With a 0.01F soft-start capacitor the ramp-up time of the 3.3V
supply was 400s, and the ramp-up time of the 5V supply was 600s. With a 0.1F soft-start
capacitor the ramp-up time of the 3.3V supply was 800s, and the ramp-up time of the 5V supply
was 1200s. The DSP kit uses a 0.1F soft-start capacitor.
Figure 54 shows the 3.3V power-on waveform. The 200s ramp-up waveform satises the Altera
Stratix II power-on requirements of monotonicity, regulation, and turn-on time. Figure 55 shows
the 3.3V supply gate driver waveforms. The high-side gate is on for about 0.9s, the low-side gate
is on for about 2.5s, the period of the waveform is about 4s (250kHz switching frequency), so the
gates are both o for about 0.6s, i.e., the converter is close to operating in continuous-mode.
Figure 56 shows the 5V power-on waveform. The 250s ramp-up waveform satises the Altera
Stratix II power-on requirements of monotonicity, regulation, and turn-on time. Figure 57 shows
the 5V supply gate driver waveforms. The high-side gate is on for about 0.9s, the low-side gate is
on for about 1.3s, the period of the waveform is about 50s (20kHz switching frequency), so the
gates are both o for about 48s. The 5V supply is operating at a much lower frequency than the
510kHz design frequency, since the converter is operating in discontinous mode (which is obvious
from the high-side gate driver ringing in the top trace of Figure 57).
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December 4, 2006
Figure 54: Altera Stratix II DSP kit 3.3V power-on waveform.
Figure 55: Altera Stratix II DSP kit 3.3V high-side and low-side gate drive waveforms. The buck
controller is operating in discontinuous mode.
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December 4, 2006
Figure 56: Altera Stratix II DSP kit 5.0V power-on waveform.
Figure 57: Altera Stratix II DSP kit 5.0V high-side and low-side gate drive waveforms. The buck
controller is operating in discontinuous mode.
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6.5
December 4, 2006
Monolithic converters (integrated MOSFETs)
A common power supply requirement is to convert power from a 5V or 3.3V input power supply
to lower voltages, such as 2.5V and 1.25V for DDR SDRAM voltages, or 1.2V for CPU, DSP, or
FPGA core voltage. These applications often have load current requirements of less than 10A. Power
supply manufacturers oer monolithic converters that meet these power supply requirements, i.e.,
synchronous buck converter components that include the high-side and low-side MOSFETs. The
advantage of these parts is simple user and low board real-estate, but the disadvantage is their
limited design exibility.
The following sections analyze a selection of converters from Linear Technology and from Texas
Instruments, for load currents in the 3 to 10A range.
6.5.1
Linear Technology converters
Linear Technologys range of step-down converters can be accessed by starting at the Linear Technology home page www.linear.com, and then selecting the following menu and sub-menus; Power
Management, Switching Regulators, and Step-down Converters. Then under the title View All Products click the View Table link to see a list of Linear Technology step-down converters. Setting
Monolithic = yes and updating the table limits the list to the monolithic converters. A selection of
converters capable of load currents from 1A to 8A are; LTC3411 (1.25A), LTC3412 (2.5A), LTC3414
(4A), LTC3415 (7A), LTC3418 (8A).
The list of Linear Technology step-down converters contains a column of the available package
types. The list of 1A to 8A converters just mentioned all appear to come from a LTC34xx series,
however, the devices do not use a common package, or subset of packages, so upgrading a part to a
higher current device would not always be possible.
6.5.2
Linear Technology LTC3414; 3.3V to 1.2V at 4A
The LTC3414 is a 4A, monolithic synchonous buck converter, that operates with a xed frequency
of up to 4MHz, and uses a current-mode control loop [74]. The LTC3414 can be used to generate
the 1.2V core supply for a processor such as the Freescale PowerQUICC II Pro (MPC8349E), or an
FPGA such as an Altera Stratix II.
The design specication for the 1.2V supply is;
VIN = 3.3V
Allowable input ripple; VIN = 100mV (3.3%)
VOUT = 1.20V 50mV, i.e., VOUT = 100mV (8.3%)
IOUT = 3A
f = 500kHz
The 1.2V supply design procedure is;
1. Select the operating frequency (p8 [74]);
The LTC3414 has a minimum on-time of tON(MIN) = 110ns (p8 [74]), so at a duty cycle of
D = 1.2V/3.3V = 0.36, the maximum operating frequency is fMAX = D/tON(MIN) = 3.3MHz,
so 500kHz is an acceptable operating frequency.
An operating frequency of 500kHz requires a resistor on the RT pin of
ROSC (k) =
3.08 108
10 = 606k
f
(130)
A 604k standard value can be used.

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December 4, 2006

The LTC3414 data sheet recommends selecting the inductor based on a ripple current of 40%,
i.e.,
1.2V
L=
500kHz 0.4 4A

1.2V
1
= 0.95H
3.3V
(131)
Using a 1.0H inductor results in a ripple current of 1.53A (38%).

3. Select the input capacitance;
With
a duty cycle of D = 0.36, the ripple current in the input capacitance is ICIN
IOUT D(1 D) = 1.9A.
RMS
The current pulses from the input to the high-side switch are approximately IOUT in magnitude,
so the input ripple voltage specication of 100mV, gives the ESR requirement of the input
capacitance as RCIN VIN /IOUT = 100V/4A = 25m.
The voltage rating, RMS current, and ESR requirements can met by a single Sanyo OS-CON,
or POSCAP capacitor, eg. a 68F TPE-series POSCAP (10TPE68M; 10V, 25m, 2.4A).
4. Select the output capacitance;
The RMS current in the output capacitance is given by (46), i.e., ICOUT RMS = 0.44A.
The ESR required to keep a transient voltage dip below 50mV is RCOUT = 50mV/(4A +
1.53A/2) = 10.5m. The ripple voltage due to this ESR will have a peak-to-peak amplitude
of 16mV.
The capacitance value required to keep a transient voltage peak below 50mV is
COUT

2
1.53A
1.0H 4A +
2
=
= 221F
(1.2V + 50mV 16mV/2)2 1.2V2
(132)
A single Sanyo TPE-series 220F (2R5TPE220M9; 2.5V, 9m, 3.9A) would meet these requirements, while a single 330F (2R5TPE330M9; 2.5V, 9m, 3.9A) would have a lower voltage
peak transient. Using a pair of either of these capacitors would exceed the requirements. Using
a pair of lower capacitance value TPE-series capacitors would not help to reduce ESR, since
the lower value capacitors have ESRs of 18m or more.
5. Check the junction temperature;
The eciency plots on p4 of the LTC3414 data sheet [74] indicate an eciency of 87% for the
maximum load current of 4A. For a 1.2V supply at 4A, the output power is 4.8W, and at an
eciency of 87%, the total power dissipated would be 0.72W. The LTC3414 data sheet gives
the package thermal resistance as JA = 38 C/W (p2 [74]). For a power dissipation of 0.72W,
the temperature rise of the junction would be 27 C, so at an ambient temperature of 50 C,
the junction temperature would be 77 C.
The MOSFETs can be used to check this eciency analysis. The gures on p3 of the data
sheet [74] show that at an input voltage of 3.3V, and an ambient temperature of 25 C, the
high-side on resistance is RHS DS(ON) = 70m, the low-side resistance is RLS DS(ON) = 52m,
and the temperature coecient for both MOSFETs is T = 0.0035.
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December 4, 2006
Assuming the total power dissipation is due to conduction losses alone, the total power can be
approximated as;
P = PHS + PLS

2
= IOUT
RHS DS(ON) (TJ )D + RLS DS(ON) (TJ )(1 D)
2
= IOUT
[1 + (TJ 25 C)T ]

RHS DS(ON) (25 C)D + RLS DS(ON) (25 C)(1 D)
Then using TJ = TA + JA P , solving for the total power gives;

2
IOUT
[1 + (TA 25 C)T ] RHS DS(ON) (25 C)D + RLS DS(ON) (25 C)(1 D)

P =
2
1 IOUT
JA T RHS DS(ON) (25 C)D + RLS DS(ON) (25 C)(1 D)
(133)
(134)
At duty-cycle D = 1.2V/3.3V = 0.36, and ambient temperature of 50 C, the total power

dissipated due to conduction losses in the high-side and low-side MOSFETs is 1.2W, so the
eciency of the converter for 1.2V 4A operation is less than 80%. The junction temperature
of the device will be at least 96 C, or about 20 higher than the data sheet eciency plots
predict. The data sheet eciency plots were generated for an output voltage of 2.5V, however,
using D = 2.5V/3.3V = 0.76 in (134) gives a total power of 1.3W, and hence an eciency of
less than 79%. The data sheet eciency plots are inconsistent with the data sheet MOSFET
characteristics.
Figure 58 shows a SwitcherCAD circuit of the LTC3414 design, along with an eciency analysis.
The simulation conrmed the input ripple voltage of 100mV (given a input supply impedance of
50m), output ripple current of 1.5A, and ouput ripple voltage of 14mV. Transient simulation of
the design conrmed a monotonic power supply turn-on ramp of 400s, and a 4A load transient dip
of 50mV, and peak of 50mV.
The eciency report indicates a device power dissipation of 1.044W. At an ambient temperature
of 25 C, the junction temperature will be 65 C, the high-side on-resistance will be 80m, the lowside on-resistance will be 59m, so the conduction dissipation of the MOSFETs is 4A2 (80m
0.36 + 59m 0.64) = 1.065W. So the simulation power dissipation estimate is conservative.
The 3.3V to 1.2V at 4A supply conservatively operates at a full-load eciency of 80%, and
dissipates 1.2W. The junction temperature at full-load current, at an ambient temperature of 50 C,
is 96 C . The supply voltage regulation requirements are all met by the design.
The LTC3414EFE (TSSOP-20 package) is available from Linear Technologys online store for
$6.07 each. Digikey lists the part in 2500 quantity lots for about $5.27 each.
90
CARMA Correlator
December 4, 2006
LTC3414 Example Design: 3.3V to 1.2V at 4A

(forced continuous mode)
.tran 0 5ms 0ms steady startup
IN
C1
R6
2200K
R1
100K
PGOOD
Pgood
C4
1000pF
V1
3.3V
Rser=0.05
68F
RUN
SVin
PVin
L1
Run/SS
SW
1.0H
U1
R2
Ith
FB
100K
R5
12.1K
470pF
C2
Rt
Mode
I1
220F
LTC3414
SGND
C5
OUT
R3
200K
4A
load
PGND
R4
604K

Input: 5.95W @ 3.21V
Output: 4.8W @ 1.2V
Ref.
C1
C2
C4
C5
L1
R1
R2
R3
R4
R5
R6
U1
Irms
1344mA
418mA
0mA
0mA
4022mA
0mA
0mA
0mA
0mA
0mA
0mA
4022mA
Ipeak Dissipation
1791mA
45mW
745mA
2mW
0mA
0mW
0mA
0mW
4745mA
57mW
0mA
0W
0mA
2W
0mA
3W
0mA
1W
0mA
0W
0mA
1W
4745mA 1044mW
Figure 58: LTC3414 3.3V to 1.2V at 4A SwitcherCAD schematic and eciency report.
91
CARMA Correlator
6.5.3
December 4, 2006
Linear Technology LTC3418; 3.3V to 1.2V at 8A
The LTC3414 is an 8A, monolithic synchonous buck converter, that operates with a xed frequency
of up to 4MHz, and uses a current-mode control loop [76]. The part is essentially a higher current
version of the LTC3414 (its MOSFETs have lower on-resistance), with an important caveat; the
packages are not compatible.
Using the same design specication as used for the LTC3414, with an 8A maximum output
current, the 1.2V supply design procedure is;
1. Select the operating frequency (p8 [76]);
The LTC3418 has a minimum on-time of tON(MIN) = 80ns (p9 [76]), so at a duty cycle of
D = 1.2V/3.3V = 0.36, the maximum operating frequency is fMAX = D/tON(MIN) = 4.5MHz,
so 500kHz is an acceptable operating frequency.
An operating frequency of 500kHz requires a resistor on the RT pin of
ROSC (k) =
7.3 107
2.5 = 143.5k
f
(135)
A 143k standard value can be used.

The LTC3418 data sheet recommends selecting the inductor based on a ripple current of 40%,
i.e.,

1.2V
1.2V
L=
1
= 0.48H
(136)
500kHz 0.4 8A
3.3V
Using a standard 0.47H (Vishay/Dale IHLP-series) inductor results in a ripple current of
3.27A (41%).
With
a duty cycle of D = 0.36, the ripple current in the input capacitance is ICIN
IOUT D(1 D) = 3.8A.
RMS
The current pulses from the input to the high-side switch are approximately IOUT in magnitude,
so the input ripple voltage specication of 100mV, gives the ESR requirement of the input
The voltage rating, RMS current, and ESR requirements can met by a single Sanyo OS-CON
capacitor, eg. 560F 4SVP560M (4V, 13m, 4.5A), or by POSCAP capacitors, eg. a single
680F 4TPE680MF (4V, 15m, 3.9A), or a pair of 68F 10TPE68M (10V, 25m, 2.4A).
The RMS current in the output capacitance is given by (46), i.e., ICOUT RMS = 0.94A.
The ESR required to keep a transient voltage dip below 50mV is RCOUT = 50mV/(8A +
3.27A/2) = 5.2m. The ripple voltage due to this ESR will have a peak-to-peak amplitude of
17mV.
The capacitance value required to keep a transient voltage peak below 50mV is

2
3.27A
0.47H 8A +
2
COUT =
= 431F
(1.2V + 50mV 17mV/2)2 1.2V2
(137)
A pair of Sanyo TPE-series 220F (2R5TPE220M9; 2.5V, 9m, 3.9A) would meet these
requirements.
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CARMA Correlator
December 4, 2006
5. Check the junction temperature;

The eciency plots on p4 of the LTC3418 data sheet [76] indicate an eciency of 84% for the
maximum load current of 8A. For a 1.2V supply at 8A, the output power is 9.6W, and at an
eciency of 84%, the total power dissipated would be 1.82W. The LTC3418 data sheet gives
the package thermal resistance as JA = 34 C/W (p2 [76]). For a power dissipation of 1.83W,
the temperature rise of the junction would be 62 C, so at an ambient temperature of 50 C,
the junction temperature would be 112 C.
The MOSFETs can be used to check this eciency analysis. The gures on p3 of the data
sheet [76] show that at an input voltage of 3.3V, and an ambient temperature of 25 C, the
high-side on resistance is RHS DS(ON) = 35m, the low-side resistance is RLS DS(ON) = 26m,
and the temperature coecient for both MOSFETs is T = 0.0035. The LTC3418 MOSFET
on-resistances are half those of the LTC3414 MOSFETs.
Assuming the total power dissipation is due to conduction losses alone, the total power dissipation can be approximated using (134). At duty-cycle D = 1.2V/3.3V = 0.36, and ambient
temperature of 50 C, the total power dissipated due to conduction losses in the high-side and
low-side MOSFETs is 2.6W, so the eciency of the converter for 1.2V 8A operation is less than
79%. The junction temperature of the device will be at least 138 C. Continuous operation of
the device at this junction temperature would not be recommended.
Figure 59 shows a SwitcherCAD circuit of the LTC3418 design, along with an eciency analysis.
The simulation conrmed the input ripple voltage of 100mV (given a input supply impedance of
50m), output ripple current of 3.1A, and ouput ripple voltage of 14mV. Transient simulation of
the design conrmed a monotonic power supply turn-on ramp of 350s, and an 8A load transient
dip of 50mV, and peak of 50mV.
The eciency report indicates a device power dissipation of 2.277W. At an ambient temperature
of 25 C, the junction temperature will be 102C, the high-side on-resistance will be 44m, the lowside on-resistance will be 33m, so the conduction dissipation of the MOSFETs is 8A2 (44m
0.36 + 33m 0.64) = 2.365W. So the simulation power dissipation estimate is conservative.
The 3.3V to 1.2V at 8A supply conservatively operates at a full-load eciency of 79%, and
dissipates 2.6W. The junction temperature at full-load current, at an ambient temperature of 50 C,
is 138 C . The supply voltage regulation requirements are all met by the design, however, operation
at such a high junction temperature is not recommended. The maximum operating current of the
design should be limited to 7.3A, so that the maximum power dissipated is 2.2W, and the maximum
junction temperature is 125 C.
The LTC3418EUHF (QFN-38 package) is available from Linear Technologys online store for
$8.19 each.
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CARMA Correlator
December 4, 2006
LTC3418 Example Design: 3.3V to 1.2V at 8A

(forced continuous mode)
.tran 0 5ms 0ms steady startup
IN
R1
100K
R6
2200K
SVin
C1
C2
68F
68F
V1
3.3V
Rser=0.05
PVin
Pgood
Track
PGOOD
U2
C5
1000pF
RUN
L1
0.47H
R2
Ith
FB
100K
LTC3418
R5
10K
Rt
SGND
C6
820pF
OUT
SW
Run/SS
Mode
PGND
R3
200K
C3
C4
I1
220F 220F
8A
load
R4
143K

Input: 12.1W @ 3.1V
Output: 9.59W @ 1.2V
Ref.
C1
C2
C3
C4
C5
C6
L1
R1
R2
R3
R4
R5
R6
U2
Irms
1623mA
1623mA
433mA
433mA
0mA
0mA
8048mA
0mA
0mA
0mA
0mA
0mA
0mA
8048mA
Ipeak Dissipation
2158mA
66mW
2158mA
66mW
779mA
2mW
779mA
2mW
0mA
0mW
0mA
0mW
9558mA 130mW
0mA
0W
0mA
2W
0mA
3W
0mA
4W
0mA
0W
0mA
1W
9558mA 2277mW
Figure 59: LTC3418 3.3V to 1.2V at 8A SwitcherCAD schematic and eciency report.
94
CARMA Correlator
6.5.4
December 4, 2006
Texas Instruments converters
Texas Instruments range of step-down converters can be accessed by starting at the Texas Instruments home page www.ti.com, and then selecting the following menu and sub-menus; under the
Find products list, click on Power Management, then under the product tree list click on DC/DC
Converters (Integrated Switch), and then click on Step-down Regulators (click on the Show All Results link to see a single-page listing of all the converters). Filtering the list of converters to those
capable of delivering an output current of 3 to 14A results in a table of converters with part numbers
of the form TPS54xxx, eg. TPS54310 (3A), TPS54610 (6A), TPS54810 (8A), TPS54910 (9A), and
TPS54010 (14A).
The TPS54xxx devices are part of the Switcher with Integrated FETs (SWIFT) family;
www.ti.com/swift will take you to the TI Power Management page. The Power Management
Selection Guide [42] can be downloaded from that page, and pages 30 to 34 provide details on
the SWIFT devices (p32 has a list of relevant TI application notes). The SWIFT design software
can also be downloaded from the Power Management page. Evaluation boards for the SWIFT
converters are available at TIs online store at prices ranging from $10 (TPS54610/810/910EVM),
to $49 (TPS54010EVM).
The SWIFT family of converters is designed with common packaging for subsets of devices [36],
so they allow migration to higher current devices; with some limitations, eg. there are two styles of
packages, and not all devices have the same input voltage range. The device are packaged in TIs
PowerPAD 20- and 28-pin HTSSOP packages. These packages have junction-to-ambient resistances
as low as 14.4C/W [41] and 18.2 C/W [39, 40]. Reference [35] contains a detailed thermal analysis
of the SWIFT devices in the 28-pin HTSSOP package, while reference [25] analyzes layouts for
optimal thermal performance.
The following sections analyze the 3.3V to 1.2V at 4A, and 3.3V to 1.2V at 8A supply designs
using SWIFT devices. The TPS54610 and TPS54910 can both operate with an input voltage of
3.3V, and they can operate with load currents of up to 6A and 9A respectively. The devices both
come in the 28-pin HTSSOP package, and the 14A TPS54010 [38] can be used as an upgrade device.
References [23, 24] detail the SWIFT power supply design procedure.
The Digikey prices for the 3.3V input voltage parts are (November 1, 2006);
TPS54610PWP (296-12123-5-ND) $4.52 each (100 quantity) and $4.18 each (1000 quantity).
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CARMA Correlator
December 4, 2006
Vin
U1
R4
100 k
28
24
RT
VIN
Thru
27
SYNC
C5
0.068 uF
26
C4
0.10 uF
25
C1
100 uF
TPS54610
14
PH
VBIAS
Thru
PWRGD
150 pF
COMP
C6
R3
3300 pF
6
Vo
5
BOOT
19
VSENSE
PGND
Thru
R5
442
1
AGND
R2
R1
10.0 k
28.7 k
L1
4.7 uH
PH
3
12.7 k
47 uF
VIN
SS/ENA
4
C7
C9
20
C3
0.047 uF
C2
330 uF
15
PGND
PowerPad
C8
4700 pF
Figure 60: TPS54610 3.3V to 1.2V at 4A SWIFT designer circuit.

6.5.5
Texas Instruments TPS54610; 1.2V at 4A
Figure 60 shows the circuit generated by TIs SWIFT designer software given the following parameters;
From the Choose Your Application pull-down select: Standard 3.0 to 6.0 Vin, or Std - Adj
Only 3.0 to 6.0 Vin
Vout (V): 1.2
Iout (A): 4.0
Min Vin (V): 3.25
Max Vin (V): 3.35
Design for size
Surface mount only
Any type of output capacitor
Vo Ripple (mVp-p): 10
Sw Freq (kHz): 500
Input Ripple (mVp-p): 100
Once those parameters are entered, click on the GO button to analyze the design.
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CARMA Correlator
December 4, 2006
The SWIFT tool generates several analysis pages that include an analysis of the design, device
stress ratings, loop response, eciency plot, and a bill-of-materials. The parameters of interest for
the Figure 60 design are; VIN = 16mV, VOUT = 3mV, IOUT = 0.4A, = 72.9% (at 4A load),
PU1 = 1.145W, TJ = 70.8C (TA = 50 C, JA = 18.2 C/W).
The following compares these numbers to a theoretical analysis;
1. Inductor ripple current;
The 4.7H inductor is a Vishay/Dale IHLP-2525CZ-01 (5.5A, 40m). The inductor ripple
current should be approximately;

1.2V
1.2V
1
= 0.32A
(138)
IOUT =
500kHz 4.7H
3.3V
i.e., about 8% of IOUT . The SWIFT analysis gives an output ripple current of 0.4A (10%).
2. Input capacitance;
The input capacitance consists of a 47F muRata GRM31CR60J476ME19L (Ceramic X5R,
6.3V, 10m, 3A) in parallel with a 100F muRata GRM32ER60J107ME20L (Ceramic X5R,
6.3V, 10m, 3A). With input ripple current pulses of magnitude IOUT , the ripple voltage
should be about 20mV.
3. Output capacitance;
The output capacitance consists of a 330F Panasonic EEFSE0E331R (Polymer Al, 2.5V,
5m, 4A). With an inductor peak-to-peak ripple current of 0.4A, the peak to peak ripple
voltage should be about 2mV.
The voltage dip due to a load current increase would be approximately VOUT = 5m 4A =
20mV.
The voltage peak due to a load current decrease would be

2
4.7H
0.4A
VOUT =
+ 1.2V2 1.2V = 100mV
4A +
330F
2
(139)
From this analysis, its clear that the SWIFT tool does not account for transient voltages.
4. Power dissipation;
The TPS54610 [39] data sheet p5 states that the high-side and low-side MOSFETs have
matched on-resistances, and p8 has a plot of the on-resistance versus temperature (for 3.3V
input voltage, 6A load current). The on-resistance at a junction temperature of 70 C is 40m,
so conductive losses for a 4A load would be 640mW. The SWIFT power estimate of 1.145W
does not appear to be too conservative.
The transient voltage response of this supply would not meet the requirements of a 1.2V 50mV
supply. The load current decrease voltage transient is the problem; the energy from the inductor
has to be stored on the output capacitance. The transient can be reduced by increasing the output
capacitance or by reducing the inductance. In this design, the ripple current is low, so reducing the
inductor is reasonable. Figure 61 shows the SWIFT circuit result after changing the inductor to a
Vishay/Dale IHLP-2525CZ-01 1.5H (9A, 15m). The SWIFT estimate for inductor ripple current
was 1.2A (30%), so the transient voltage peak for this circuit would be 39mV. The SWIFT analysis
results did not change appreciably from the original design; the eciency did go up to 77.5% due
to the lower inductor DCR, but the converter power dissipation was about the same, resulting a
junction temperature of 71.0 C.
97
CARMA Correlator
December 4, 2006
Vin
R4
100 k
28
24
RT
VIN
Thru
27
SYNC
C5
0.068 uF
26
C4
0.10 uF
25
C1
100 uF
TPS54610
U1
14
PH
VBIAS
Thru
PWRGD
100 pF
C6
R3
COMP
2200 pF
6
Vo
5
BOOT
19
VSENSE
PGND
Thru
R5
511
1
AGND
R1
10.0 k
R2
28.7 k
L1
1.5 uH
PH
3
11.3 k
47 uF
VIN
SS/ENA
4
C7
C9
20
C3
0.047 uF
C2
330 uF
15
PGND
PowerPad
C8
2200 pF
Figure 61: TPS54610 3.3V to 1.2V at 4A SWIFT designer circuit (with 1.5H inductor).
Table 8 shows the 1.2V supply compensation values calculated by the SWIFT designer, and by the
design algorithm presented in Section 3.13, implemented using MATLAB. The MATLAB program
calculates the compensation values to arbitrary values, and then converts them to standard resistor
and capacitor values. Note how for the 4.7H inductor supply the component rounding causes the
locations of the two poles to exchange (they were nominally set to the same values, since they were
located at the gain-bandwidth limit of the amplier). This exchange of poles is of no concern, since
the original assignments were arbitrary.
Table 8 shows that for the 4.7H inductor supply, the compensation components calculated by
the SWIFT tool and the MATLAB program (with Z1 = 0.8fLC and Z1 = 0.9fLC ) are almost
identical; R3 and R5 are the only dierences. Figures 62 and 63 show the closed-loop response as
calculated by the SWIFT tool and the MATLAB program respectively.
Table 8 shows that for the 1.5H inductor supply, the compensation components calculated by
the SWIFT tool and MATLAB script are quite dierent. The compensation components calculated
by the MATLAB program give a phase margin closer to the target of 60 . Figures 64 and 65 show
the closed-loop response as calculated by the SWIFT tool and the MATLAB program respectively.
98
CARMA Correlator
December 4, 2006
Table 8: TPS54610 1.2V supply compensation components

Component or
Parameter
Supply Design
4.7H
1.5H
SWIFT MATLAB
SWIFT MATLAB
R1
R2
R3
R5
10k
28.7k
12.7
442
10k
28.7k
13k
383
10k
28.7k
11.3k
511
10k
28.7k
13k
634
C6
C7
C8
3300pF
150pF
4700pF
3300pF
150pF
4700pF
2200pF
100pF
2200pF
1800pF
91pF
2700pF
L
RDCR
COUT
RESR
fLC
fESR
4.7H
40m
330F
5m
4130Hz
96.5kHz
4.7H
40m
330F
5m
4130Hz
96.5kHz
1.5H
15m
330F
5m
7154Hz
96.5kHz
1.5H
15m
330F
5m
7154Hz
96.5kHz
G1
GZ1
GP1
fZ1
fZ2
fP1
fP2
89.2dB
3.1dB
29.2dB
3243Hz
3798Hz
76.6kHz
87.3kHz
89.2dB
3.0dB
30.6dB
3261Hz
3710Hz
88.4kHz
85.3kHz
92.8dB
0.0dB
26.9dB
6883Hz
6402Hz
141.6kHz
147.2kHz
94.5dB
3.6dB
26.3dB
5543Hz
6802Hz
93.0kHz
141kHz
fCLOSEDLOOP
MARGIN
28.6kHz
63.0
21.1kHz
61.9
38.5kHz
76.0
38.3kHz
59.8
99
CARMA Correlator
December 4, 2006
60
50
40
Gain
30
20
10
0
-10
-20
10
100
1K
10 K
100 K
28.6 kHz.
1M
Frequency - Hz
(a)
270
225
180
Phase
135
90
63
45
0
-45
-90
10
100
1K
10 K
100 K
28.6 kHz.
1M
Frequency - Hz
(b)
Figure 62: TPS54610 1.2V (4.7H) supply SWIFT loop-response; (a) gain and (b) phase.
100
CARMA Correlator
December 4, 2006
60
50
40
Gain
30
20
10
0
10
20 1
10
10
10
10
Frequency (Hz)
10
10
(a)
250
Phase (degrees)
200
150
100
50
0
50
1
10
10
10
10
Frequency (Hz)
10
10
(b)
Figure 63: TPS54610 1.2V (4.7H) supply MATLAB loop-response; (a) gain and (b) phase.
101
CARMA Correlator
December 4, 2006
60
50
40
Gain
30
20
10
0
-10
-20
10
100
1K
10 K
100 K
38.5 kHz
1M
Frequency - Hz
(a)
270
225
180
Phase
135
90
76
45
0
-45
-90
10
100
1K
10 K
100 K
38.5 kHz
1M
Frequency - Hz
(b)
Figure 64: TPS54610 1.2V (1.5H) supply SWIFT loop-response; (a) gain and (b) phase.
102
CARMA Correlator
December 4, 2006
60
50
40
Gain
30
20
10
0
10
20 1
10
10
10
10
Frequency (Hz)
10
10
(a)
250
Phase (degrees)
200
150
100
50
0
50
1
10
10
10
10
Frequency (Hz)
10
10
(b)
Figure 65: TPS54610 1.2V (1.5H) supply MATLAB loop-response; (a) gain and (b) phase.
103
CARMA Correlator
December 4, 2006
Vin
R4
100 k
28
24
RT
VIN
Thru
27
SYNC
C5
0.068 uF
26
C4
0.10 uF
25
C1
180 uF
TPS54910
U1
14
PH
VBIAS
Thru
PWRGD
220 pF
C6
R3
COMP
0.010 uF
6
Vo
5
BOOT
19
VSENSE
PGND
Thru
R5
232
1
AGND
R1
10.0 k
R2
28.7 k
L1
5.6 uH
PH
3
6.98 k
68 uF
VIN
SS/ENA
4
C7
C9
20
C3
0.047 uF
C2
2 x 100 uF
15
PGND
PowerPad
C8
6800 pF

6.5.6
Texas Instruments TPS54910; 1.2V at 8A
Figure 66 shows the circuit generated by TIs SWIFT designer software given the following parameters;
From the Choose Your Application pull-down select: Standard 3.0 to 6.0 Vin, or Std - Adj
Only 3.0 to 6.0 Vin
Vout (V): 1.2
Iout (A): 8.0
Min Vin (V): 3.25
Max Vin (V): 3.35
Design for size
Surface mount only
Any type of output capacitor
Vo Ripple (mVp-p): 10
Sw Freq (kHz): 500
Input Ripple (mVp-p): 100
Once those parameters are entered, click on the GO button to analyze the design.
The SWIFT tool generated the following parameters of interest; VIN = 20mV, VOUT = 1mV,
IOUT = 0.33A, = 77.3% (at 8A load), PU1 = 2.098W, TJ = 88.2 C (TA = 50 C, JA =
18.2 C/W).
104
CARMA Correlator
December 4, 2006
The following compares these numbers to a theoretical analysis;

1. Inductor ripple current;
The 5.6H inductor is a Sumida CEP125-H-5R6 (8.8A, 11m). The inductor ripple current
should be approximately;

1.2V
1.2V
1
= 0.27A
(140)
IOUT =
500kHz 5.6H
3.3V
i.e., about 3.4% of IOUT . The SWIFT analysis gives an output ripple current of 0.33A (4.1%).
2. Input capacitance;
The input capacitance consists of a 68F TDK C5750X5R1A686M (Ceramic X5R, 10V, 2m,
4.4A) in parallel with a 180F Panasonic EEFSE0J181R (Polymer Al, 6.3V, 5m, 4A). With
input ripple current pulses of magnitude IOUT , the ripple voltage should be about 20mV.
3. Output capacitance;
The output capacitance consists of a pair of 100F TDK C3225X5R0J107M (Ceramic X5R,
6.3V, 2m, 3.2A) With an inductor peak-to-peak ripple current of 0.33A, the peak to peak
ripple voltage should be less than 1mV.
The voltage dip due to a load current increase would be approximately VOUT = 2m 8A =
16mV.
The voltage peak due to a load current decrease would be

2
5.6H
0.33A
VOUT =
+ 1.2V2 1.2V = 618mV
8A +
200F
2
(141)
i.e., a 51.5% transient overshoot. If this was the core supply to a Stratix II FPGA, the
overshoot to 1.818V would exceed the absolute maximum rating of the VCCINT supply.
4. Power dissipation;
The TPS54910 [41] data sheet p4 states that the high-side and low-side MOSFETs have
matched on-resistances, and p7 has a plot of the on-resistance versus temperature (for 3.0V
and 3.6V input voltage, 9A load current). The on-resistance at a junction temperature of 70 C
is 18m, so conductive losses for an 8A load would be 1.152W. The SWIFT power estimate
of 2.098W does not appear to be too conservative.
The transient voltage response of this supply would not meet the requirements of a 1.2V 50mV
supply. Figure 67 shows the SWIFT circuit result after changing the inductor to a Vishay/Dale
IHLP-2525CZ-01 1.5H (9A, 15m), and changing the output capacitors to a pair of 470F Panasonic EEFUE0D471R (Polymer Al, 2.5V, 12m, 3.3A). The SWIFT estimate for inductor ripple
current was 1.2A (15%), so the transient voltage peak for this circuit would be 48mV. The SWIFT
analysis results did not change appreciably from the original design; the ripple voltages were higher
(but well within requirement), the eciency did go down to 75.7% due to the higher inductor DCR,
but the converter power dissipation was about the same, resulting a junction temperature of 88.3 C.
Figure 68 shows a higher-current (12A) upgrade to the circuit in Figure 67. Relative to Figure 67,
there are component value changes, an additional input capacitor, and the inductor rating required a
larger package type (Vishay IHLP-5050CE-01 1.5H). If an upgrade path from the 8A to 12A design
is desired, then a set of common packaging for the design component values would be required, and
the schematic and PCB should contain the number of components as shown in the 12A design. The
PCB can then be loaded as appropriate for 8A or 12A maximum load current. The controller in the
12A design dissipates 3.28W, and its junction temperature is 97.3 C.
105
CARMA Correlator
December 4, 2006
Vin
U1
100 k
R4
24
28
RT
VIN
Thru
27
SYNC
C5
0.068 uF
26
C4
0.10 uF
25
C1
470 uF
TPS54910
C9
20
100 uF
VIN
SS/ENA
14
PH
VBIAS
L1
1.5 uH
Thru
4
PWRGD
100 pF
C7
9.31 k
C6
R3
Vo
PH
3
COMP
4700 pF
5
C3
0.047 uF
BOOT
19
VSENSE
C2
2 x 470 uF
PGND
Thru
681
R5
1
AGND
R1
10.0 k
R2
28.7 k
15
PGND
PowerPad
C8
4700 pF
Figure 67: TPS54910 3.3V to 1.2V at 8A SWIFT designer circuit (with 1.5H inductor).
Vin
R4
100 k
28
24
RT
VIN
Thru
27
SYNC
C5
0.068 uF
26
C4
0.10 uF
25
C1
470 uF
TPS54010
U1
SS/ENA
14
VBIAS
Thru
PWRGD
150 pF
C6
R3
COMP
0.010 uF
6
Vo
5
BOOT
19
2
VSENSE
PGND
Thru
R5
487
1
AGND
R1
10.0 k
R2
28.7 k
L1
1.5 uH
PH
3
8.87 k
2x47 uF
PH
4
C7
C9
20
PVIN
C3
0.047 uF
C2
2 x 1000 uF
15
PGND
PowerPad
C8
0.010 uF
106
CARMA Correlator
December 4, 2006
Figure 69: TPS54610 evaluation board (TPS54610EVM-192); 5V to 3.3V at 6A.

6.5.7
Texas Instruments TPS54610EVM-192; 5V to 3.3V at 6A measurements
Figure 69 shows a photo of the TPS54610EVM-192 evaluation board. The TPS54610 can also be
evaluated using the TPS54610EVM-213, which is an evaluation board that can be loaded with the
TPS54610, TPS54810, and TPS54910. The next section analyzes the TPS54910 version of the board.
Figure 70 shows a SWIFT schematic of the evaluation board (p4-2 [22]). Figure 71 shows
the SWIFT eciency report for the circuit, which matches well with the measurement results on
p2-3 [22]. The SWIFT generated parameters of interest are; VIN = 20mV, VOUT = 12mV,
IOUT = 0.50A (8.3% of 6A), = 90.9% (at 6A load), PU1 = 1.481W, TJ = 77.0 C (TA = 50 C,
JA = 18.2 C/W). The EVM guide [22] has measurements of the board junction temperatures
relative to an ambient temperature of 25 , and measured JA = 15.5 C/W on the evaluation board.
The schematic and SWIFT simulation use two Sanyo 470F POSCAP capacitors (4TPB470M;
4V, 40m, 3A) for the output capacitors. The SWIFT report indicates an output ripple current of
0.50A peak-to-peak, which gives an RMS output current of 0.14A, so the capacitor current rating
is sucient. The peak-to-peak voltage ripple on the output would be 20m 0.5A = 10mV.
The voltage dip due to transient current load increase would be approximately 20m (6A +
0.5A/2) = 125mV. The transient voltage peak due to load current decrease would be 29mV. For a
3.3V supply with a specication of 3.3V 165mV, VOUT = 330mV (10%), these voltage transients
are acceptable.
Figure 72 shows the power-on waveforms for the EVM. The waveforms were identical with no
load, and with a 6A resistive load (the load was created using parallel 10 1W resistors, and the load
current was measured with a clamp-on ammeter). Figures 73 and 74 show the input voltage ripple
under no load and 6A load conditions. The input ripple voltage under the 6A load, is consistent
with an input capacitance ESR of RCIN = 240mV/6A = 40m. Figures 75 and 76 show the output
voltage ripple under no load and 6A load conditions. These measurements match those shown in
Sections 2.8, 2.9, and 2.10 in the EVM users guide (pp2-8 to 2-10 [22]).
107
CARMA Correlator
December 4, 2006
Vin
U1
28
24
RT
VIN
Thru
27
SYNC
C5
0.033 uF
26
C4
0.10 uF
25
C1
220 uF
TPS54610
C9
20
10.0 uF
VIN
SS/ENA
14
PH
VBIAS
L1
4.7 uH
Thru
4
PWRGD
68 pF
C7
9.76 k
C6
R3
Vo
PH
3
COMP
BOOT
6800 pF
19
VSENSE
C3
0.047 uF
PGND
Thru
R5
1.18 k
15
AGND
R1
10.0 k
R2
3.74 k
C2
2 x 470 uF
PGND
PowerPad
C8
0.012 uF
Figure 70: TPS54610EVM 5V to 3.3V at 6A schematic implemented as a SWIFT designer circuit.

100%
90%
80%
70%
60%
50%
40%
30%
20%
0%
0
20%
40%
60%
80%
1.2
2.4
3.6
4.8
100%
6
Output Current - % Full Load(Top)/Amps(Bottom)
Figure 71: TPS54610EVM 5V to 3.3V at 6A SWIFT eciency report.
108
CARMA Correlator
December 4, 2006
Figure 72: TPS54610EVM power-on waveform. The traces are; 5V from a lab supply, the 3.3V
output, and the power-good signal. The waveforms were identical for power-on into no load, and
power-on into a 6A resistive load.
109
CARMA Correlator
December 4, 2006
Figure 73: TPS54610EVM input capacitor (C9) voltage ripple with no load (top-trace, the second
trace is the switching-node).
Figure 74: TPS54610EVM input capacitor (C9) voltage ripple with 6A load.
110
CARMA Correlator
December 4, 2006
Figure 75: TPS54610EVM output (J3) ripple voltage with no load (top-trace, the second trace is
the switching-node).
Figure 76: TPS54610EVM output (J3) ripple voltage with 6A load.

111
CARMA Correlator
December 4, 2006
Figure 77: TPS54910 evaluation board (TPS54910EVM-067); 3.3V to 1.8V at 9A.

6.5.8
Texas Instruments TPS54910EVM-213; 3.3V to 1.8V at 9A measurements
Figure 77 shows a photo of the TPS54910EVM-213 evaluation board. The TPS54910EVM-213 has
been optimized for size, it contains an inductor rated to 12A, and uses only ceramic input and
output decoupling capacitors. Figure 78 shows a SWIFT schematic of the evaluation board (p42 [26]). Figure 79 shows the SWIFT eciency report for the circuit, which matches well with the
measurement results on p2-3 [26]. The SWIFT generated parameters of interest are; VIN = 180mV,
VOUT = 9mV, IOUT = 1.98A (22% of 9A), = 88.9% (at 9A load), PU1 = 1.828W, TJ = 83.3 C
(TA = 50 C, JA = 18.2 C/W).
The schematic and SWIFT simulation use two Taiyo Yuden 22F capacitors (JMK325BJ226MM;
ceramic X5R, 6.3V, 12m, 2A) for the output capacitors. The SWIFT report indicates an output
ripple current of 1.98A peak-to-peak, which gives an RMS output current of 0.57A, so the capacitor
current rating is sucient. The peak-to-peak voltage ripple on the output would be 6m 1.98A =
12mV. The voltage dip due to transient current load increase would be approximately 6m (9A +
1.98A/2) = 60mV. The transient voltage peak due to load current decrease would be 346mV. The
load peaking would be excessive for most application, and would need to be reduced using additional
bulk capacitance; 330F would reduce the peaking to 50mV.
load, and with a 9A resistive load. Figures 81 and 82 show the input voltage ripple under no load
and 9A load conditions. The input ripple voltage under the 9A load, is consistent with an input
capacitance ESR of RCIN = 160mV/9A = 18m. Figures 83 and 84 show the output voltage ripple
under no load and 9A load conditions. These measurements match those shown in Sections 2.7, 2.8,
and 2.9 in the EVM users guide (pp2-10 to 2-14 [26]).
112
CARMA Correlator
December 4, 2006
Vin
U1
71.5 k
R4
28
24
RT
VIN
Thru
27
SYNC
C5
0.047 uF
26
C4
0.10 uF
25
C1
Open
TPS54910
C9
20
2x10.0 uF
VIN
SS/ENA
14
PH
VBIAS
L1
0.60 uH
Thru
4
PWRGD
12 pF
C7
10.0 k
C6
R3
Vo
PH
3
COMP
BOOT
470 pF
19
VSENSE
C3
0.047 uF
PGND
Thru
R5
301
15
AGND
R1
10.0 k
R2
9.76 k
C2
3 x 22 uF
PGND
PowerPad
C8
470 pF
Figure 78: TPS54910EVM 3.3V to 1.8V at 9A schematic implemented as a SWIFT designer circuit.
100%
90%
80%
70%
60%
50%
40%
30%
20%
0%
0
20%
40%
60%
80%
1.8
3.6
5.4
7.2
100%
9
Figure 79: TPS54910EVM 3.3V to 1.8V at 9A SWIFT eciency report.
113
CARMA Correlator
December 4, 2006
Figure 80: TPS54910EVM power-on waveform. The traces are; 3.3V from a lab supply, the 1.8V
114
CARMA Correlator
December 4, 2006
115
CARMA Correlator
December 4, 2006

116
CARMA Correlator
December 4, 2006
Figure 85: TPS54010 evaluation board (TPS54010EVM-067); 3.3V to 1.5V at 13A.

6.5.9
Texas Instruments TPS54010EVM-067; 3.3V to 1.5V at 13A measurements
Figure 85 shows a photo of the TPS54010EVM-067 evaluation board. The TPS54010EVM-067

evaluation board specication (p1-3 [32]) indicates that it can be operated at up to 14A, however,
the SWIFT designer tool will not allow the design to be created and will issue the following error;
peak output current exceeds internal power switch current limit. The issue is that with a 3.3V input
supply, a 1.5V output supply, a 700kHz switching frequency and a 0.68H inductor, the peak-to-peak
inductor ripple current is approximately 1.72A, so the peak current through the internal MOSFETs
at a load current of 14A would be 14.86A, however p4 of the data sheet [38] states that the device
minimum current limit is 14.5A. Reducing the maximum load current entered into the SWIFT design
tool to 13A allows the design to be created as per the evaluation board. The evaluation board design
is compact, but yet is capable of delivering high load currents. A key component of the design is
the Vishay/Dale IHLP-2525CZ-01 0.68H inductor, which is rated to 15.5A.
Figure 86 shows a SWIFT schematic of the evaluation board (p4-2 [32]). Figure 87 shows
the SWIFT eciency report for the circuit, which matches well at high load currents with the
measurement results on p2-3 [32]. At lower load currents, the measurements on p2-3 [32] show
higher eciency than the SWIFT estimate. The SWIFT generated parameters of interest are;
VIN = 18mV, VOUT = 9mV, IOUT = 1.75A (13% of 13A), = 79.5% (at 13A load), PU1 =
4.112W, TJ = 109.2 C (TA = 50 C, JA = 14.4C/W).
The evaluation board uses a single 100F output decoupling capacitor. The output voltage
peaking of this circuit for a 13A load current decrease will be 386mV. Two 470F would reduce the
output peaking to below 50mV.
load, and with a 13A resistive load. Figures 89 and 90 show the input voltage ripple under no load
and 13A load conditions. The input ripple voltage under the 13A load, is consistent with an input
capacitance ESR of RCIN = 260mV/13A = 20m. Figures 91 and 92 show the output voltage ripple
under no load and 13A load conditions. These measurements match those shown in Sections 2.6,
2.7, and 2.8 in the EVM users guide (pp2-8 to 2-10 [32]).
117
CARMA Correlator
December 4, 2006
Vin
U1
28
71.5 k
R4
24
RT
VIN
Thru
27
SYNC
C5
0.068 uF
26
C4
0.10 uF
25
C1
330 uF
TPS54010
C9
20
2x10.0 uF
PVIN
SS/ENA
14
PH
VBIAS
L1
0.68 uH
Thru
4
PWRGD
C7
120 pF
4.64 k
C6
R3
Vo
PH
3
COMP
3300 pF
BOOT
19
2
VSENSE
C3
0.047 uF
C2
100 uF
PGND
Thru
R5
422
15
AGND
R1
10.0 k
R2
14.7 k
PGND
PowerPad
C8
1500 pF
Figure 86: TPS54010EVM 3.3V to 1.5V at 13A schematic implemented as a SWIFT designer circuit.
100%
90%
80%
70%
60%
50%
40%
30%
20%
0%
0
20%
40%
60%
80%
2.6
5.2
7.8
10.4
100%
13
Figure 87: TPS54010EVM 3.3V to 1.5V at 13A SWIFT eciency report.
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December 4, 2006
Figure 88: TPS54010EVM power-on waveform. The traces are; 3.3V from a lab supply, the 1.5V
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6.5.10
December 4, 2006
Texas Instruments TPS54xxx; external synchronization
The input RMS current from multiple supplies can be minimized by operating the controllers at
slightly dierent operating frequencies, or by operating the devices at the same frequency with
dierent phase shifts, much like a multi-phase converter.
TODO: get some transient response plots, where the transient edges are fast. I wonder whether
the voltage-mode control loops deal with fast edges ok, and thats why the eval manuals only show
slow rates.
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6.6
December 4, 2006
Texas Instruments TPS40090 multi-phase buck converter
The Texas Instruments TPS40090 is a high-frequency multi-phase buck controller [43]. The TPS40090
outputs logic-level PWM control signals that can be used to control MOSFET gate drivers such as
the UCC27221 used on the TPS40090EVM-001 [33], or the TPS2834 used on the TPS40090EVM002 [34]. The TPS40090 can be congured for two-, three-, or four-phase operation, with a switching
frequency of up to 1MHz per phase. The controller can use resistive or inductor DCR current sensing.
The following sections analyze the TPS40090EVM-001 evaluation board. The rst section analyzes a hypothetical single-phase controller equivalent to one-quarter of the evaluation board, the
second section analyzes the four-phase implementation, and the last section contains measurements
from the evaluation board.
6.6.1
Single-phase 12V to 1.5V at 25A
The design specication for the hypothetical single-phase 1.5V supply is;
VIN = 12V
VIN = 200mV (1.7%)
VOUT = 1.50V
VOUT RIPPLE = 10mV (0.7%)
VOUT TRANSIENT DIP = 160mV (10.7%)
VOUT TRANSIENT PEAK = 200mV (13.3%)
IOUT = 25A
f = 420kHz
The interesting thing to note about the TPS40090EVM-001 specication (p5 [33]) is that it provides
separate specications for the ripple voltage, and transient voltages. Unfortunately, FPGA data
sheets are not so detailed, and often provide only the minimum and maximum operating range for
a core supply, eg. 1.50V 50mV.
The 1.5V supply design procedure is;
The timing resistor for a four-phase controller operating at 420kHz is (p12 [43], p8 [33]);
1.041
7)
RRT (k) = KPH (39.2 103 fPH
= 1 (39.2 103 4201.041 7)
(142)
= 65.9k
where KPH = 1 for a four-phase controller, and fPH is the single-phase frequency in kHz. The
evaluation kit uses a standard resistance value of 64.9k for the frequency set resistor, so the
nominal frequency of a single-phase is 425.4kHz.
2. Select the inductor and ripple current (p9 [33]);
The evaluation board uses a 0.62H, 30A, 1.75m inductor (TDK SPM12550-R62M300),
which results in a ripple current of

1.5V
1.5V
IOUT =
1
= 5.0A
(143)
420kHz 0.62H
12V
i.e., a ripple current of 20%.
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December 4, 2006

With a duty cycleof D = 1.5V/12V = 0.125, the ripple current in the input capacitance is
ICIN RMS IOUT D(1 D) = 2.73A.
The input ripple voltage specication of 200mV, gives the ESR requirement of the input
The evaluation board uses two 68F input capacitors (Sanyo OS-CON 20SVP68M; 20V, 40m,
2.4ARMS ). Two of these capacitors meet the RMS current requirement, but with an ESR of
20m, the input ripple would be approximately 500mV.
The evaluation board contains eight 220F capacitors (Sanyo POSCAP 2R5TPE220MF; 2.5V,
15m, 3.1ARMS ), so the total output capacitance is 1760F, the total ESR is about 2m, and
the current rating is over 20ARMS .
The ripple current in the output capacitors is given by (46), i.e., ICOUT RMS = 1.44A.
The 10mV ripple specication requires an ESR of RCOUT = 10mV/5A = 2m.
The 160mV transient voltage dip specication requires an ESR of RCOUT = 160mV/25A =
6.4m.
The 200mV transient voltage peak specication requires an output capacitance value of at least
COUT

2
5A
0.62H 25A +
2
=
= 733F
(1.5V + 200mV)2 1.5V2
(144)
The eight POSCAP capacitors would generate a ripple voltage of about 10mV, a transient dip
of about 50mV, and a transient peak of about 90mV.
5. Select the MOSFETs (p12 [33]);
The duty cycle, D = 0.125, of the design is low, so the high-side MOSFET selection is based
on switching losses, while the low-side MOSFET is selected based on conduction losses.
The evaluation board uses a single Silconix (Vishay) Si7860DP (N-channel, 30V 18A, 8m) for
the high-side MOSFET and a pair of Si7880DP (N-channel, 30V, 29A, 3m) for the low-side
MOSFETs.
So how hot can these MOSFETs get? The four-phase controller eciency at full load is about
86.5% (p15 [33]), so about 23.5W is dissipated. For one-quarter of this design, the dissipation
would be 5.9W. The inductor DCR of 1.75m will dissipate 1.1W, the capacitors will not
dissipate much, so the rest of the power dissipation will be gate drivers and MOSFETs. If the
high-side dissipates 2W, and the low-side pair another 2W, with JA = 50 C/W, the device
junction temperature estimates are 150 C for the high-side, and 100C for each low-side.
If the FAN5069 analysis in Section 6.3 (1.4V at 25A design) is re-run using an Si7860DP for
the high-side, and a pair of Si7880DPs for the low-side, the high-side junction temperature at
full load is 147 C, and the low-side junction temperature is 91 C. The evaluation board uses
multiple copper planes for heatsinking the MOSFETs, so the JA of the MOSFETs mounted
on the evaluation board is likely better than the 50 C/W used to estimate their temperatures.
6. Select the current sense components (p12 [33]);
The evaluation board uses inductor DCR current sensing. The basic current sense circuit is
an RC circuit that matches the time constant of the inductor, i.e., RSNS CSNS = L/RL , where
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December 4, 2006
RSNS and CSNS are the sensing circuit components, and L and RL are the inductor and inductor DCR. The recommended circuit for current sensing involves a temperature compensating
network consisting of two resistors and a negative temperature coecient resistor (p17 [43]).
The evaluation board uses the recommended circuit; see p7 for the schematic (which adds an
additional resistor) and pp12-13 for the component values [33].
6.6.2
Four-phase 12V to 1.5V at 100A
The design specication for the four-phase 1.5V supply is;

VIN = 12V
VIN = 200mV (1.7%)
VOUT = 1.50V
VOUT RIPPLE = 10mV (0.7%)
VOUT TRANSIENT DIP = 160mV (10.7%)
VOUT TRANSIENT PEAK = 200mV (13.3%)
IOUT = 100A
f = 420kHz
The design procedure for a multi-phase converter starts by dividing the required output current
by the number of phases, to determine the per-current phase, i.e., IOUT PH = 25A per phase.
The inductance per phase is then determined using the same procedure as used for a single-phase
converter. The main dierence between the single-phase design procedure and the multi-phase design
comes at the output and input capacitance requirements. The switching currents from the multiple
phases are phase-shifted such that they sum together to reduce the amplitude of the switching
currents. This reduction in switching current amplitude occurs at both the input and output. The
design procedure for determining the capacitance requirements is then
The magnitude of the current pulses in a multi-phase converter are reduced by the number
of phases, i.e., instead of 100A pulses, the pulses are 25A in height. However, rather than
occurring at a switching rate of 420kHz, the pulses occur at four times the rate, i.e., 1680kHz.
So the ripple voltage on the input for a given ESR would be reduced by a factor of four, but
the ripple frequency is four times higher. The tradeo is that the capacitance characteristics
at the new higher frequency need to be used (or the lower frequency data sheet values need
to be conservatively derated for use at higher frequency), and radiated energy now occurs at
a higher frequency.
The coherent summing of the input currents reduces the RMS requirements as shown in Figure XXXX. For a duty cycle of D = 0.125, the RMS input ripple current is 3.18A (p10 [33]).
The two 68F capacitors are rated for 2.4ARMS for frequencies 100kHz to 500kHz, but the
OS-CON data sheet does not have a derating value for frequencies above 500kHz. The 4.8A
rating of the two capacitors should be sucient for the 3.18A expected.
The input ripple voltage specication of 200mV, gives the ESR requirement of the input
capacitance as RCIN VIN /IOUT PH = 200V/25A = 8m. So as with the single-phase
hypothetical design, the ripple voltage in the two 40m OS-CON capacitors will actually be
closer to 500mV. (The evaluation board uses the wrong current in their calculation of input
ripple voltage on p10 [33]).
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CARMA Correlator
December 4, 2006

The trapeziodal waveforms from each inductor in a multi-phase converter add together to create
a higher-frequency ripple waveform, with a lower amplitude. For a duty cycle of D = 0.125, the
RMS output ripple current is ICOUT RMS = 3.41A (p11 [33]). Compare this to a 100A singlephase converter, with 20% inductor ripple current, hence output capacitance RMS current of
5.77A, and the multi-phase converter has 40% less RMS current. The RMS current rating of
the eight POSCAP capacitors is more than sucient for the output current.
The
will create an output ripple voltage of VOUT = IOUT RCOUT
output ripple current
12ICOUT RMS RCOUT = 12 3.41A 1.9m = 22mV. This exceeds the 10mV ripple
specication.
The 160mV transient voltage dip specication requires an ESR of RCOUT = 160mV/100A =
1.6m, but since the ESR is 1.9m the dip will be closer to 190mV.
The transient voltage peak in a multi-phase converter is caused when the load current drops to
zero, and the output capacitance is required to store the energy from the multiple inductors.
With a total output capacitance of 1760F, and the maximum energy stored in four 0.62H
inductors, the voltage peak would be

2
4L
IOUT PP PH
2
VOUT =
+ VOUT
VOUT
IOUT PH +
COUT
2

2
(145)
4 0.62H
5A
=
+ 1.5V2 1.5V
25A +
1760F
2
= 321mV
which exceeds the 200mV specication requirement (the energy relation used on p12 [33] is
incorrect). The amount of output capacitance required is 2930F, eg., using TPE series capacitors, the two options are to use either; eight 330F (2R5TPE330MF) capacitors with a total
capacitance of 2640F, or eight 470F (2R5TPE470MF) capacitors with a total capacitance
of 3760F, and this total capacitance would reduce the voltage peak to 160mV.
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CARMA Correlator
6.6.3
December 4, 2006
TPS40090EVM-001 measurements
Figure 93 shows the power-up waveforms; EN/SYNC, VOUT, and PGOOD. The output voltage
has a nice monotonic rise, no over-shoot, and reaches regulation in about 1.5ms, with power-good
asserting about 0.5ms later.
Figure 94 shows the high-side and low-side gate drive voltages. The low-side swings from ground
to 6.5V, while the high-side swings from 12V to 18.5V. Both gate drivers produce a gate-to-source
voltage of 6.5V due to the use of the UCC27221 gate drivers [28]. The gate drivers are powered from
the input supply and contain a 6.5V regulator. The advantage of increasing the gate drive voltage is
that it lowers the on-resistance of the MOSFETs. For example, the low-side Si7880DP on-resistance
at 4.5V is 3.5m, and at 6.5V is about 2.8m, a decrease in resistance of 0.7m (20%), which for
a 25A per-phase load current is a decrease in power dissipation of 438mW per phase.
Figures 95 and 96 show the high-side gate drive, and switching-node voltage with no load and
a 10A load respectively. Under the 10A load, the gate-driver falling edge and switching node edge
are faster, and the ringing on the rising edge is more pronounced. A snubber circuit exists on each
phase on the board for reducing this oscillation.
The UCC272221 gate drivers use predictive gate drive to minimize body-diode conduction losses,
and eliminate the need for a parallel Schottky diode. Figure 96 shows no body diode conduction
near the rising edge of the gate driver waveform, and about 25ns of body diode conduction on the
falling edge. Figure 97 is a zoomed view of the falling edge waveform, and body-diode conduction
voltage dip.
The TPS40090EVM-001 has a convenient output voltage transient generator built onto the board.
The generator is basically a square-wave generator driving a MOSFET that shorts the output voltage
to a low resistance. The resistance on the board is three 50m resistors switched on/o by a
Si7858DP MOSFET with an on-resitance of about 3m. The resistance across the 1.5V supply
when the MOSFET is on is about 20m, so the load current step is about 75A. Figure 98 shows the
transient generator gate drive, and the switching-node voltage. Figures 99 and 100 show zoomed
views of the rising and falling edge waveforms. Note how when the transient occurs (rising edge)
the switching-node voltage is on for longer than normal, to increase the inductor current. Then,
when the transient load is removed (falling edge), the switching-node voltage stays at zero, i.e., the
inductor energy is dumped into the output capacitance, and the gate driver stays o until the load
current and voltage indicates the drivers need to come on again.
Figure 101 shows the output voltage transients during the 75A load increase and decrease. The
200mV voltage dip on the rising edge indicates that the output ESR is approximately 2.6m, so
the resistance of one each of the eight capacitors is close to 21m, not the 15m stated in the
EVM BOM description (p27 [33]). The part number in the BOM, i.e., 2R5TPE220M refers to the
25m part, whereas the 15m part is the 2R5TPE220MF. A load dump of 75A into 1760F would
generate a voltage transient of

2
4 0.62H 75A 5A
+
+ 1.5V2 1.5V
VOUT =
(146)
1760F
4
2
= 199mV
The observed voltage peak is about 230mV, so the output capacitance is likely smaller than 1760F.
For example, given that the capacitance tolerance is 20%, using the minimum capacitance value
predicts a voltage peak of 245mV.
Figure 102 shows the output ripple voltage of about 20mV. Dividing this by the 2.6m ESR
estimated from the voltage transient dip indicates a peak-to-peak output ripple current of approximately 7.7A, or an RMS current of approximately 2.2A. The estimate of the RMS current is lower
than the theoretical value of 3.4A.
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December 4, 2006
Figure 93: TPS40090EVM-001 EN/SYNC, VOUT, and PGOOD.
Figure 94: TPS40090EVM-001 high-side and low-side gate drive voltages. The low-side swings from
ground to 6.5V, while the high-side swings from 12V to 18.5V.
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December 4, 2006
Figure 95: TPS40090EVM-001 high-side gate drive and VSW with no load.
Figure 96: TPS40090EVM-001 high-side gate drive and VSW with a 10A load.
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December 4, 2006
Figure 97: TPS40090EVM-001 high-side gate drive and VSW with a 10A load; expanded view of
the body-diode conduction.
Figure 98: TPS40090EVM-001 transient generator gate drive and VSW.

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December 4, 2006
Figure 99: TPS40090EVM-001 transient generator gate drive rising edge and VSW.
Figure 100: TPS40090EVM-001 transient generator gate drive falling edge and VSW.
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December 4, 2006
Figure 101: TPS40090EVM-001 transient generator gate drive and output voltage.
Figure 102: TPS40090EVM-001 output voltage ripple.
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December 4, 2006
30
35
40
Gain (dB)
45
50
55
60
65
70
75
80 0
10
10
10
Frequency (Hz)
10
10
Figure 103: TPS40090EVM output impedance. The EVM output contains 8 220F capacitors
(15m ESR) in parallel with 4 10F capacitors (1m ESR), in parallel with the load. The
impedance starts with a pole due to the load resistance and output capacitance, and is followed by
the 220F ESR zero, a pole, and the 10F ESR zero.
6.6.4
TPS40090EVM-001 compensation network
The TPS40090 uses current-mode control. The compensation network on the EVM has footprints
for an additional input capacitor and resistor (as used in voltage-mode compensation), however, the
components are not stued. The board output capacitance consists of 8 220F POSCAP 15m
(or 25m), and four 10F ceramic capacitors. The total capacitance is 1800F.
The eective load impedance in parallel with the output capacitors creates a power-stage output
impedance of

ZPOWER (s) =
1
RLOAD
+8
sCOUT2
sCOUT1
+4
sROUT1 COUT1 + 1
sROUT2 COUT2 + 1
1
(147)
which has zeros at Z1 = 1/(ROUT1 COUT1 ) and Z2 = 1/(ROUT2 COUT2 ) due to the output capacitance ESR, and a pair of poles with more complicated expressions. Figure 103 shows a plot of the
impedance; the two zeros are marked with and +, while the two poles are marked with and .
The low-frequency pole is dominated by the load resistance and the output capacitance and is given
approximately by P1 1/(RLOAD (8COUT1 + 4COUT2 )) (shown as the red virtually on top of the
rst pole, while the other pole is located between the two capacitance zeros. The vertical dashed
lines in the gure are the EVM compensation zero (near the rst pole), and the compensation pole
(between the ESR zeros).
At an output voltage of 1.5V, and the maximum load current of 100A, the minimum eective load
resistance is RLOAD = 15m, so the maximum frequency of the power-stage pole is 5.89kHz. Lower
load currents will have higher eective load resistances, so the pole will move to lower frequencies.
The evaluation board compensation network zero is located at fZ = 1/(2 40.2k 1000pF) =
3.96kHz, as shown by the left vertical line in Figure 103. The frequency of the compensating zero
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CARMA Correlator
December 4, 2006
is equivalent to the frequency of the power-stage pole for a load resistance of 22m (load current
of 67A). The placement of the compensation zero is consistent with the current-mode compenation
algorithm.
The evaluation board compensating pole is placed at fP = 354kHz, which the EVM Users
Guide (p14 [33]) states is the location of the ESR zero. However, as shown in Figure 103 there
are two ESR zeros, and neither is near 354kHz. The most likely explaination is the location of the
zero was estimated from the calculation 1/(2 1800F 0.25m) = 354kHz, i.e., the paralleled
output capacitance was treated as being a single capacitor with the total capacitance of the parallel
capacitors, and the total ESR of the parallel resistances. The dashed line in Figure 103 shows the
single pole and zero response of this equivalent capacitance in parallel with the load resistance; the
two curves in the gure match at low frequencies, but diverge due to the zero-pole-zero caused by
the parallel capacitances. The closed-loop gain and phase plots on p16 of the EVM Users Guide [33]
show that with the compensation zero located at 354kHz the closed-loop response is ne.
The TPS40090EVM-001 uses a switching frequency of 420kHz, and the closed-loop gain plots
on p16 [33] show a closed-loop bandwidth of 89kHz, i.e., the closed-loop bandwidth is slightly
higher than fSW /5 = 84kHz. The compensator gain at the cross-over frequency is approximately
20 log10 (R3 /R1 ) = 12dB, so the power-stage gain at 89kHz must be -12dB. Given the 100A powerstage pole at 5.89kHz, and that the drop-o from 5.89kHz to 89kHz follows a -20dB/decade slope,
the gain at the power-stage pole must have been 20 log10 (89kHz/5.89kHz) 12dB = 11.5dB, i.e.,
the modulator gain was about 3.8.
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CARMA Correlator
6.7
December 4, 2006
Notes
There are several other supplies I have access to that I can test, and add to this results section; an
Intersil ISL6535 1.2V at 10A board, and an AMCC Yosemite evaluation board.
The AMCC Yosemite board is an evalation board for AMCCs 440EP PowerPC processor. The
board uses an input supply of 5V, and then uses switch-mode (buck and boost) and linear supplies
to generate the board-level supplies. The following are the buck and linear regulators used;
LTC3736 Synchronous buck, dual output, 2-phase, no sense resistor (uses MOSFETs), currentmode (LTC opti-loop) compensation, externally synchronizable up to 750kHz; 5V to 1.5V and
2.5V.
LTC3413 Synchronous buck, 3A, 2MHz, monolithic, 85m MOSFETs, current-mode (LTC
opti-loop) compensation; 2.5V to 1.25V DDR termination
LTC3770 Synchronous buck, tracking, voltage margining, no sense resistor (uses MOSFETs),
current-mode (LTC opti-loop) compensation, PLL; 5V to 3.3V
LT1962 Linear regulator; 3.3V to 1.8V
135
CARMA Correlator
December 4, 2006
Table 9: cPCI power specication.
Power rail
Tolerance
3.3V
5V
12V
-12V
0.3V
5%
5%
10%
Maximum Current
Specication Pin Rating
7.6A
5A
500mA
100mA
10A
8A
1A
1A
Note
25W on 3.3V, no 5V power

25W on 5V, no 3.3V power
CARMA Board Power Supplies
The following sections summarize the power supplies for the CARMA board.
7.1
CPU and System Controller Supplies
The CPU and System Controller FPGA power supplies are all generated using the 3.3V cPCI power
supply as the input supply.
7.1.1
LTC4245 hot-swap controller
The LTC4245 hot-swap controller is for use in hot-swap compact PCI (cPCI) applications [78]. The
controller supports insertion into a live compact PCI backplane, it safely ramps the 3.3V, 5V, 12V,
and -12V cPCI supplies, provides a 1V pre-charge output for pre-charging PCI bus signals as detailed
in the cPCI Hot Swap Specication [61] and provides an I2C interface for monitoring voltage and
currents, i.e., board power consumption.
The PCI Local Bus Specication provides details on the power supply design for PCI systems [21].
The Compact PCI Specication augments the PCI Local Bus specication [60]. The PCI and cPCI
power specications are identical;
Power rails are; 5V, 3.3V, +12V, and -12V (p137 [21]).
There is a per board power limit of 25W (p150 [21]).
A board may optionally draw its 25W limit from either the 5V rail (5A current), or from the
3.3V rail (7.6A) current.
The cPCI J1 connector carries power. The pins in the 2mm hard-metric connector have a current
rating of 1A/pin, which derates to 0.8A/pin if a power pin is assigned next to another power pin.
The J1 connector contains 85V pins, 103.3V pins, 112V pin, and 1-12V pin. The pins are
typically located near signalling pins, so the 1A/pin rating can be used. Table 9 provides a summary
of the cPCI power specication (p137 [21]).
The CARMA board uses the LTC4245 to hot-swap the 3.3V, 5V, and 12V cPCI supples. The
-12V supply is not used. The 3.3V supply is used to power the CPU and system controller logic,
the 5V supply is used to power the digitizer linear regulators and FPGA 3.3V pre-driver linear
regulator, and the 12V supply is available as an optional gate driver voltage for the FPGA switchedmode supplies. Table 10 shows the basic requirements, and nominal levels of capacitance on each
supply. Note that the cPCI Hot Swap Specication lists the maximum inrush current for 3.3V and
5V as 1.5A/ms, and for 12V and -12V as 150mA/ms (p61 [61]).
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December 4, 2006
Table 10: CARMA board cPCI power supply requirements.

Supply Voltage
Maximum Current
Maximum Inrush
dI/dt
Load Capacitance
3.3V
5V
12V
7.6A
5A
500mA
1A/ms
1A/ms
100mA/ms
2500F
1000F
100F
Table 11: CARMA board sense resistor selection.

Supply Voltage
RSENSE(MIN)
RSENSE
ITRIP(MIN)
ITRIP(MAX)
PSENSE(MAX)
3.3V
5V
12V
3.0m
4.5m
90m
3.0m
4.0m
90m
7.4A
5.6A
500mA
9.3A
6.9A
611mA
260mW
190mW
34mW
The following is the design procedure for the CARMA board LTC4245;
1. Disable -12V (VEE) sequencing.
Sequencing and monitoring of -12V is disabled by leaving the CFG pin oating (no-connect),
and grounding the VEEIN, VEEOUT, VEEGATE, and VEESENSE pins (see p10, p11, p13,
p18 [78]). This disables the VEE under-voltage lockout, start-up foldback, and power-bad
functions.
2. Select the sense resistors.
The minimum sense resistor value is selected based on the minimum circuit-breaker threshold
voltage and the maximum load current, i.e.,
RSENSE(MIN) =
VCB(MIN)
ILOAD
(148)
The resistor values are then converted to the nearest standard value (or a pair of parallel
resistors). The selected resistance is then used along with the minimum and maximum circuitbreaker threshold voltages to determine the minimum and maximum trip currents. Table 11
shows the results of the calculations for the CARMA board. The resistance values selected,
in the RSENSE column, are available in the Vishay WSL-2010, 1%, 0.5W and WSL-1206, 1%,
0.25W series of current-sense resistors (available from Digikey).
3. Select the soft-start capacitor.
The soft-start capacitor sets the rate of the rise of the inrush current for all the supplies. The
inrush current rate requirements for the CARMA board are shown in Table 10. The LTC4245
inrush current rate is (p16 [78])
dIINRUSH
GSS
ISS
= IINRUSH =
dt
RSENSE CSS
(149)
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December 4, 2006
The soft-start capacitance required by each supply to meet its inrush requirement can then be
determined from
CSS =
GSS
ISS
RSENSE IINRUSH
(150)
where IINRUSH is given in Table 10, ISS = 20A, GSS = 23mV/V for the 3.3V and 5V supplies,
and GSS = 46mV/V for the 12V supply (p4 [78]). The soft-start capacitance values are; 153nF
for 3.3V, 115nF for 5V, and 102nF for 12V. Using the standard value CSS = 150nF meets all
the supply inrush rate requirements. The inrush rates are; 1.0A/ms for the 3.3V, 720mA/ms
for 5V, 70mA/ms for 12V.
The amount of time required for the supply output current to ramp up and reach the currentlimit is
tLIMIT =
ILIMIT
IINRUSH
(151)
The amount of charge transferred to the output capacitance during this time is (the area under
the current versus time plot)
1
ILIMIT tLIMIT
2
(152)
2
ILIMIT
QLIMIT
=
.
V
2V IINRUSH
(153)
QLIMIT =
which is suent to charge a capacitance
CLIMIT =
If the output supply capacitance is larger than this value, then the voltage on the output
capacitance will increase quadratically until the current limit is reached, at which point the
voltage will increase linearly until the capacitance is charged. The capacitance limits for the
supplies are; 8751F for 3.3V, 3472F for 5V, and 148F for 12V. Table 10 shows the nominal
amount of capacitance loading each supply. From this table and the previous calculation, it
can be seen that all of the supplies will complete charging while inrush current rate limited.
During inrush current rate limited operation, the voltage on a supply will rise with a quadratic
shape according to
V =
1
C

0
1
IINRUSH d =
IINRUSH t2
2C
(154)
Since all of the supplies complete charging while inrush current rate limited, the time taken
to charge their capacitance is

tCHARGE =
2CV
IINRUSH
(155)
i.e., 4.1ms for 3.3V, 3.7ms for 5V, and 5.6ms for 12V. The maximum currents reached while
charging are then 4.1A for 3.3V, 2.7A for 5V, and 400mA for 12V.
4. Select the timer capacitor.
A 2.2F capacitor is used, giving a 50ms start-up time.
138
CARMA Correlator
December 4, 2006
5. Select the MOSFETs.

The 3.3V and 5V MOSFETs are International Recier IRF6618 (which are also used for the
FPGA supply hot-swap, and the FPGA switch-mode supply low-side synchronous recitiers).
The 12V MOSFET is an IRF7413 (as used in the example design on p14 of the LTC4245 data
sheet [78]).
The charging times and maximum currents calculated during the soft-start capacitor discussion
are used to check the safe-operating-area (SOA) of the MOSFETs during power-on. The 3.3V
supply ramps up in 4.1ms, reaching a maximum current of 4.1A. While charging the output
load, the current increases linearly, while the drain-to-source voltage decreases quadratically.
The power dissipation during this time is approximately 3.3V4.1A/4 = 3.4W. An alternative
way to estimate the power dissipation is to determine the average power required to charge the
output capacitance, i.e., CV 2 /(2tCHARGE = 3.3W. The SOA chart for the IRF6618 indicates
that this is safe. The 5V supply MOSFET start-up power dissipation is approximately 3.4W,
which is also safe. The 12V supply MOSFET start-up power dissipation is approximately
1.2W, which is safe.
6. Select the I2C address.
The CARMA Boards will be plugged into a 19-slot cPCI backplane that implements cPCI
geographic addressing; with slots being numbered 1 through 19. The LTC4245 uses four
addressing pins, ADR[3:0], with ADR[1:0] matching the cPCI geographic addressing scheme,
but ADR[3:2] do not. So, although the LTC4245 implements 32 possible addresses, they are
not the same 32 addresses as the cPCI scheme. Direct connection of the LTC4245 ADR[3:0]
pins to the cPCI GA[3:0] pins yeilds 15 possible addresses (see Table 5 on p29 of the LTC4245
data sheet [78], and recall that address 0 is reserved); which is an insucient number of
unique addresses to fully populate a 19-slot cPCI crate. See the CARMA board engineering
specication for the logic required to enable the use of 24 of the LTC4245 addresses.
7. cPCI I2C hot-swap buering.
The I2C interface on the LTC4245 is intended for use via the cPCI I2C bus. The cPCI
chassis host CPU uses the I2C interface to enable or disable boards, or to monitor the power
consumption of a board. Since the CARMA board will be monitoring other board-level supplies
and currents, it will also perform the reading of the LTC4245 monitor points. When multiple
CARMA boards are loaded into a chassis, all the LTC4245 devices will appear on a common
bus. The host processor will distinguish the LTC4245s via their unique address, which is
generated from the cPCI geographic address. The CARMA board processor can read its cPCI
geographic address via a system controller register, so it uses that that to determine the address
of the LTC4245 on its board. In situations where the CARMA board processor is the only
device accessing the LTC4245 registers, the cPCI I2C interface can be disabled. The I2C bus
is disabled via an LTC4300A-3 [75] I2C hot-swap buer that is enabled by default on powerup. The enable control on the I2C hot-swap controller is accessed via a system controller
register, so the host CPU can re-enable the I2C interface via the memory-mapped version
of these registers, or by sending a message to the CARMA board processor to re-enable I2C
(assuming the processor is alive and responsive). Worst-case the host CPU can issue a PCI
reset, and the default for the hot-swap controller enable control is to leave the buer enabled.
The LTC4300A-3 has dual power supply pins, so the device can interface with a 3.3V or 5V
cPCI bus and work with the CARMA 3.3V I2C bus.
139
CARMA Correlator
7.1.2
December 4, 2006
Core 1.2V at 8A, DDR-SDRAM VDD 2.5V at 8A
The CPU and system controller 1.2V core supply, and the DDR-SDRAM 2.5V supply each use a
TPS54910 9A SWIFT controller [41]. The part can be upgraded to the 14A TPS54010, or downgraded to the 6A TPS54610. Note that the 8A TPS54810 has an input voltage range of 4V to
6V, so it is not suitable. The two TPS54910 controllers are externally synchronized to 500kHz
clocks that are phased to minimize input voltage ripple. For 20% current ripple at an 8A load, at
a 500kHz switching frequency, with an input voltage of 3.3V, the recommended inductor value for
the 1.2V supply is 0.95H, and for the 2.5V supply is 0.76H. Since the core and DDR-SDRAM
current requirements are the same, and the inductor values are close, a common power supply with
dierent output voltage set resistors can be used. A common design for the 1.2V and 2.5V supplies
is desirable as it minimizes the bill-of-materials.
The CARMA Board 1.2V and 2.5V supply design procedure was;
1. Requirements;
Core voltage: 1.20V 50mV (p152 [1], p8 [20])
DDR voltage: 2.50V 125mV (p8 [20], p52 [55])
8A maximum load current for each supply.
The limit on the 1.2V supply is determined by the FPGA core voltage requirement, and the
limit on the 2.5V supply is determined by the MPC8349E/EA DDR voltage requirement.
2. Select the inductor and output capacitance.
The power supply designs on the CARMA board are optimized for small size. The inductors on each supply are selected from the Vishay/Dale IHLP-2525CZ-01 series of inductors.
These inductors use a small 0.25-inch by 0.25-inch package, eg. see the inductor used on the
TPS54010 evaluation board in Figure 85. The other inductor selection criteria are; limiting
the temperature rise to under 30 C, and selecting an inductance value compatible with the
output capacitance value. The output voltage peaking due to full load current decrease is a
function of the inductor value and the output capacitance value.
Tables 12 and 13 show the ripple current, power dissipation, and capacitance requirement for
the 1.2V and 2.5V supplies. The ripple currents are very similar for the two designs, and the
power dissipation is virtually identical. The main dierence is in the output capacitance, which
is due to the fact that the 1.2V core peaking is limited to 50mV, whereas the 2.5V peaking
is allowed to reach 125mV. The ESR requirements for either supply are also dierent, i.e., for
an 8A load increase, the requirement for the 1.2V supply is RESR = 50mV/8A 6m, and
for the 2.5V supply is RESR = 125mV/8A 15m, Designing the 2.5V supply to match the
1.2V supply will more than meet the 2.5V supply requirements.
Tables 12 and 13 indicate that a 1.0H inductor will meet the requirements of both power
supply designs (relative to the 1.5H inductor, its lower DC resistance causes a lower temperature rise). The output capacitance ESR required is 6m, which can be satised by a
pair of Sanyo TPE-series POSCAP capacitors, eg., two 470F 4TPE470MCL capacitors. The
4TPE470MCL has a voltage rating of 4V, ESR of 12m, and RMS current rating of 3.5A.
The 470F is larger than required, however, this same value is used on the FPGA supplies, so
its use minimizes the BOM.
3. Select the soft-start capacitor (p13 [41]).
Figure 80 shows the soft-start waveform on the TPS54910EVM-001. The voltage ramp consists
of two slopes; the rst (brief) section is controlled an internal slow-start rate, and the second
is set by the soft-start capacitor. The output voltage tracks the soft-start voltage, eectively
140
CARMA Correlator
December 4, 2006
Table 12: CPU and system controller 1.2V core inductor power handling and minimum output
capacitance requirement.
L
(H)
RDCR(MAX)
(m)
IOUT
(A)
IPEAK
(A)
IRMS
(A)
2
IRMS
RDCR
(mW)
T
( C)
COUT(MIN)
(F)
0.33
0.47
0.68
0.82
1.00
1.50
3.9
4.2
5.5
8.0
10.0
15.0
4.6
3.2
2.2
1.9
1.5
1.0
10.3
9.6
9.1
8.9
8.8
8.5
8.1
8.1
8.0
8.0
8.0
8.0
257
272
354
514
641
961
9
10
12
13
15
30
287
355
462
534
621
887
Table 13: DDR-SDRAM 2.5V inductor power handling and minimum output capacitance requirement.
L
(H)
RDCR(MAX)
(m)
IOUT
(A)
IPEAK
(A)
IRMS
(A)
2
IRMS
RDCR
(mW)
T
( C)
COUT(MIN)
(F)
0.33
0.47
0.68
0.82
1.00
1.50
3.9
4.2
5.5
8.0
10.0
15.0
3.7
2.6
1.8
1.5
1.2
0.8
9.8
9.3
8.9
8.7
8.6
8.4
8.1
8.0
8.0
8.0
8.0
8.0
253
271
353
513
641
961
9
10
12
13
15
30
50
63
84
98
116
165
putting the output into a constant-current mode while it charges the output capacitance. The
soft-start time can be determined from
tSS =
CSS VSS
CSS 0.7V
=
ISS
5A
(156)
Ignoring the initial slightly higher ramp rate, the output current during soft-start is approximately
IOUT = COUT
dV
VOUT
COUT VOUT 5A
COUT
=
dt
tSS
CSS 0.7V
(157)
The TPS54910EVM-001 has VOUT = 1.8V, COUT = 66F, and CSS = 47nF, so the output
current during the startup is IOUT = 18mA, i.e., low current relative to its 9A maximum.
The CARMA board supplies have much more capacitance than the EVM, COUT = 2 470F
for both supplies, so an initial estimate of the soft-start capacitor can be obtained by placing a
limit of say IOUT = 500mA on the output current during soft-start. For the 1.2V supply this
gives CSS = 13nF, and tSS = 1.8ms, while for the 2.5V supply CSS = 33nF, and tSS = 4.6ms.
The schematic uses a 47nF soft-start capacitor on both supplies so that they both power-up in
6.6ms. The output current is limited to 86mA on 1.2V and 179mA on 2.5V. The processor and
system controller FPGA will draw current during the initial power-on, so the inrush current
141
CARMA Correlator
December 4, 2006
is likely higher than estimated. However, its far from the current-limit of the device, and far
from the current-limit on the 3.3V input supply, so the hot-swap controller will not trigger a
current-limit event due to 1.2V and 2.5V supply power-on.
4. SWIFT designer simulation.
Figure 104 was generated by the following procedure;
Start the SWIFT Designer tool.
From the Choose Your Application pull-down, select Standard 3.0 to 6.0 Vin.
Inputs; Vout = 1.2V, Iout = 8A, Min Vin = 3.25, Max Vin = 3.35.
Mount type; Surface mount only.
Output caps; Any type capacitor.
Advanced/optional; Sw Freq = 475kHz, Input ripple = 100.
Then click the GO button.
The generated design selects a 5.6H inductor and a pair of 100F ceramic capacitors.
Change the inductor to IHLP-2525CZ-01 1.0F, and then the output capacitance to two
4TPE470MIL 470F (which are close enough to the 4TPE470MCL, but with 18m ESR).
The properties of the completed design are;
Input voltage ripple of 11mV.

Output voltage ripple of 22mV.
Output current ripple of 1.9A.
Eciency of 77.7% at 8A load (but over 80% for loads between 1 to 6.5A).
Inductor power dissipation of 643mW.
Controlller power dissipation of 2.086W, and junction temperature of 88.0 C.
Closed-loop bandwidth of 49.6kHz with 105-degrees phase margin.
Figure 104 is slightly modied with respect to the SWIFT generated schematic. A 49.9
resistor has been added in the feedback loop to enable measurement of the loop-gain and
closed-loop response, and R2 has been replaced by parallel resistors, R2a and R2b , to enable
more accurate setting of the output voltage.
The SWIFT designer selects R2 = 28.7k for the 1.2V supply, which sets VOUT = 1.2 with
an error of 1.5mV, and adding the eect of the 49.9 resistor increases the error to 3mV.
The ideal parallel resistance value is R2 = (R1 + 49.9) 0.891/(1.2 0.891) = 28978.8,
which can be closely matched using parallel 1% resistors R2a = 35.7k R2b = 154k, to give
R2 = 28981.5, and an output voltage error of only 29V.
Repeating the design procedure for the 2.5V supply gives a circuit like Figure 104, with R2 =
5.49k, which results in an output voltage error of 22mV. The ideal parallel resistance is
R2 = 5565.2, which is closely matched using parallel 1% resistors R2a = 5.62k R2b = 576k,
to give R2 = 5565.7, and an output voltage error of only 134V.
If the 1.2V or 2.5V supplies require upgrading to the 14A TPS54010, a Vishay/Dale IHLP2525CZ-01 series 0.68H has sucient current rating and will have a temperature rise of under
30 C under full load.
142
CARMA Correlator
December 4, 2006
Vin
R4
105 k
28
24
RT
VIN
Thru
27
SYNC
C5
0.068 uF
0.10 uF
100 uF
VIN
26
14
PH
25
VBIAS
Thru
4
PWRGD
C7
C9
20
SS/ENA
C4
C1
470 uF
TPS54910
U1
L1
1.0 uH
150 pF
Vo
PH
3
4.22 k
C6
R3
COMP
BOOT
0.022 uF
19
VSENSE
PGND
Thru
R5
475
C3
0.047 uF
C2
2 x 470 uF
1
15
AGND
PGND
R2a
R2b
R1
10.0 k
PowerPad
C8
0.010 uF
R6
49.9
Figure 104: TPS54610 core 1.2V and DDR 2.5V at 8A SWIFT designer circuit.
7.1.3
VTT 1.25V at 3A
The DDR-SDRAM VTT termination uses a Philips/NXP NE57811 DDR termination linear regulator powered from the VDD rail.
7.1.4
System controller 1.5V at 500mA
The monotonic power-on, and current requirement of the system controller FPGA 1.5V I/O interface
voltage are satised using a 1.5A TPS74201 soft-start linear regulator. The regulator is powered from
the 3.3V supply, and the TPS74201 QFN20 package JA = 36.5 C/W, so the maximum 1.5V current
to limit the device temperature rise to under 60 C is 60 C/((3.3V 1.5V) 36.5 C/W) = 913mA.
143
CARMA Correlator
7.2
December 4, 2006
Data Processing FPGA Supplies
The data processing FPGA high-current supplies are derived from a custom power supply located on
the cPCI J3 connector. The custom supply voltage is nominally 12V, with the option for operation
at 5V supported (but board re-work to change some component values is required). The FPGA
supplies are operated as a 6-phase converter; 4-phases for the core voltage, and two single-phase
converters for the I/O voltages. The TPS40140 multi-phase converter was considered for creating
all 6-phases of the converter. However, the parts were not available (November, 2006), so the
TPS40090 4-phase and TPS40100 single-phase converters were selected, and they are operated in
an externally synchronized 6-phase conguration.
7.2.1
LTC4215 hot-swap controller
The input supplies of the multi-phase buck converter are decoupled with several hundred microfarads
of capacitance (see the calculation below). If this amount of capacitance was plugged (hot-swapped)
into a live backplane the in-rush current would be likely cause damage to the cPCI connector. The
Linear Technology LTC4215 [77] hot-swap controller in conjunction with an International Rectier
IRF6618 low on-resistance MOSFET are used to separate the cPCI connector from the high input capacitance. When the hot-swap controller is enabled, it limits the in-rush current, acting as
a constant current-source operating at a board-dened maximum current, and charges the input
capacitance in a controlled manner. The board also monitors the current after power is enabled,
and shuts-down the MOSFET if an over-current condition is sensed. The LTC4215 incorporates
an I2C interface for reading the input voltage, output voltage, and current-sense resistor voltage.
The CARMA board uses these monitor points for checking the input voltage before enabling the
hot-swap controller, and for monitoring FPGA total power consumption.
The requirements for the CARMA FPGA power supply input capacitance is that the ripple
voltage is limited to 100mV peak-to-peak. A cPCI crate will house up to 20 boards, so the worstcase coherent addition of the ripple is 2V peak-to-peak, while the best-case RMS sum of ripple is
450mV peak-to-peak. The largest currents from the multi-phase buck converters will come from
the 60A 1.2V core supply. Each phase will generate current pulses of 15A, so the ESR required
to limit the ESR-induced ripple voltage to under 100mV is RCIN < 100mV/15A = 6.7. The
minimum capactance required to limit the capactance induced ripple current to under 100mV at
a converter switching frequency of 500kHz, and duty cycle of D = 1.2V/12V = 0.1, is CIN >
15A 0.1/(100mV 500kHz) = 30F. Four Sanyo OS-CON 16SVP150M 150uF, 16V, 30mOhm,
20%, 3A-rated capacitors were selected to meet these requirements. The use of 600F of capacitance
results in a capacitor-induced ripple voltage component of under 5mV, while the eective ESR of
7.5m results in an ESR induced ripple voltage of 113mV. The total input ripple voltage for this
input capacitance should be on the order of 120mV peak-to-peak.
The CARMA Board LTC4215 hot-swap controller design procedure was;
1. Select the sense resistor.
The LTC4215 monitors current via a sense resistor. The current-limit and circuit breaker
threshold is VSENSE(TH) = 25mV. The FPGA power should be limited to around 60W to
70W.
For a 12V input supply, the current limit for 60W dissipation is 5A, and 70W is 5.8A. A sense
resistor of 5m will set the current-limit to 5A (60W), and a sense resistor of 4m will set the
limit to 6.25A (75W).
For a 5V input supply, the current limit for 60W dissipation is 12A, and 70W is 14A. A sense
resistor of 2m will set the current-limit to 12.5A (62.5W).
The CARMA board will nominally use a 12V input supply with 4m sense resistor, i.e., a
current limit of 6.25A. The power dissipation of the sense resistor under continuous full load
144
CARMA Correlator
December 4, 2006
current is 156mW.
2. Select the MOSFET.
The MOSFET should be selected based on the required maximum current, and its ability to
charge the input capacitance. The IRF6618 is used as the low-side MOSFET on the switchmode power supplies and is appropriate for use as the hot-swap MOSFET.
The LTC4215 gate driver generates a gate-to-source voltage of VGATE(MAX) = 6.5V, so when
the MOSFET is on, it has a low on-resistance of less than 2.8m. At a load current of
6.25A, the power dissipation is about 110mW, so the MOSFET junction temperature rise for
JA = 45 C/W is less than 5 C.
The critical MOSFET characteristic to check is the safe-operating-area (SOA) of the MOSFET
during power-on. During power-on, the drain of the MOSFET is at the supply voltage (12V),
while the source is at ground (0V), i.e., the power supply input capacitors are discharged.
When the LTC4215 is enabled, the in-rush current will reach the current-limit set by the sense
resistor and remain in current-limit until the input capacitors are charged. Power is dissipated
in the MOSFET due the drain-to-source voltage and current. The drain-to-source voltage
decreases as the load capacitance charges up. This power-loss is identical to the switchingloss experienced by a buck converter high-side MOSFET, however, the time-scales are much
longer as the gate-drive current of the hot-swap controller is measured in micro-amperes, not
milli-amperes or amperes.
The power dissipated by the MOSFET during switch on can be estimated as follows; given Q =
CV , I = dQ/dt, and a constant current-source (the LTC4215 in current-limited operation),
the time taken to charge a capacitive load is t = CV /I. For 600F of input capacitance
charged to 12V, at a constant current of 6.25A, the charging time is 1.15ms. The IRF6618
SOA chart shows that the device is capable of handling a 12V 5A pulse (60W) for 1ms, so the
charging time of 1.15ms is near the SOA. However, the charging of the load capacitance is not
a constant 12V pulse, its a ramp that starts o at 12V and linearly ramps down towards 0V as
the capacitance charges (at which point, the drain-to-source voltage is VDS = ILOAD RDS(ON) ).
The charging of the 600F load capacitance does not violate the SOA of the MOSFET.
A SwitcherCAD simulation of the LTC4211 hot-swap controller is described shortly to show
the power-up waveforms to expect from the LTC4215 (which did not have a SwitcherCAD
model).
3. Select the soft-start capacitor.
The soft-start capacitor limits the edge-rate of the current as the MOSFET is turned on, i.e.,
it limits dI/dt, which in turn limits any voltage spike due to parasitic inductances between the
MOSFET and power-source. The edge-rate is set to 10.3A/ms using a 9.4nF capacitor, and
RSENSE = 4m (p16 [77]).
4. Select the timer capacitor.
The timer capacitor is set to 470nF, providing for a t = CV /I = 470nF 1.235V/100A =
5.8ms start-up timeout.
5. Select the input under-voltage and over-voltage resistors.
The input under-voltage and over-voltage thresholds are set using an input resistive divider
consisting of 24.9k, 1.27k, and 2.56k.
VOV(RISING) = (24.9k + 1.27k + 2.56k)/2.56k 1.235V = 13.9V
VOV(FALLING) = VOV(RISING) /1.235V 1.185V = 13.3V
VUV(RISING) = (24.9k + 1.27k + 2.56k)/(1.27k + 2.56k) 1.235 = 9.3V
145
CARMA Correlator
December 4, 2006
RS
VIN
Q1
IRF6618
VOUT
0.008
RX
10
R6
10K
BZX84C15L
GATE
D1
V1
VS
R5
10K
I1
C4
C1
R7
10
12
0.1
Vcc
R1
Sense
ON
1A
600F
R3
10K
GATE
U1
20K
FAULT_N
FAULT
FB
LTC4211
Filter
RESET
Timer
R2
10K
C3
C2
0.1
10n
RESET_N
GND
R4
1.37K
.tran 0 18ms 0us startup
Figure 105: LTC4211 hot-swap controller circuit.

VUV(FALLING) = VUV(RISING) /1.235V 1.215V = 9.1V
6. Select the output feed-back (power-good) resistors.
The power-good thresholds are set using an output resistive divider consisting of 10k and
1.37k.
VOUT(RISING) = (10k + 1.37k)/1.37k 1.235V = 10.2V
VOUT(FALLING) = VOUT(RISING) /1.235V 1.155 = 9.6V
7. Congure the analog-input channel.
The analog input is used to monitor the input voltage via a 11.5k and 1k resistor that
creates a 1/12.5 scaling of the input. This matches the scaling used by the channel that reads
the voltage of the MOSFET source. The input voltage can be read by the control system
before enabling the FPGA power supplies.
8. Select an I2C address.
The LTC4215 address pins are all pulled low via resistors. This provides a default 7-bit address
of 40h that does not conict with the other devices on the CARMA board.
9. Input protection.
The board has an SMAJ15A 15V transient voltage suppressor (TVS), and a snubber circuit.
If the input supply to the board is changed to 5V, then these component values will need to be
recalculated.
Figure 105 shows a circuit containing an LTC4211 hot-swap controller. The circuit is based on
Linears Demonstration Circuit DC536. Figure 106 shows the power-on response of the circuit. The
LTC4211 has a sense resistor threshold of 50mV, so the 8m sense resistor sets a current limit of
ILIMIT = 6.25A. The waveforms in Figure 106 help describe the MOSFET power dissipation during
power on. The rst trace shows the gate voltage as it is charged by the 10A current source. Once
the gate voltage reaches the MOSFET threshold voltage, current starts to ow from the drainto-source. The current reaches the current-limit, and the MOSFET eectively becomes a 6.25A
current-source charging the output capacitance. The output voltage then ramps up linearly, with
a ramp time given approximately by t = CVOUT /ILIMIT = 600F 12V/6.25A = 1.15ms. During
this time, the drain-to-source voltage is falling. The average power dissipation during this time is;
2
, i.e., the
PMOSFET = 12 VOUT ILIMIT , so the energy lost is EMOSFET = 12 VOUT ILIMIT t = 12 CVOUT
energy lost in the MOSFET is equal to the amount stored in the capacitance once its charged.
146
CARMA Correlator
December 4, 2006
V(GATE)
30V
25V
Volts
20V
15V
10V
5V
0V
-5V
V(VS)-V(VOUT)
14V
12V
Volts
10V
8V
6V
4V
2V
0V
-2V
Id(Q1)
7A
6A
Amps
5A
4A
3A
2A
1A
0A
-1A
V(VOUT)
14V
12V
Volts
10V
8V
6V
4V
2V
0V
-2V
V(RESET_N)
14V
12V
Volts
10V
8V
6V
4V
2V
0V
-2V
0ms
2ms
4ms
6ms
8ms
10ms
12ms
14ms
16ms
18ms
Figure 106: LTC4211 hot-swap controller response. The MOSFET turns on when the gate voltage
reaches the threshold voltage, and the output current then reaches the 6.25A current-limit set by the
8m sense resistor (50mV sense voltage). The 600F load capacitance is then eectively charged
via a 6.25A constant-current source. The MOSFET dissipated power during the time the output
voltage is charging up, i.e., during the time the drain-to-source voltage is falling.
147
CARMA Correlator
7.2.2
December 4, 2006
Core voltage 1.2V at 60A
The data processing FPGA 1.2V at 60A core supply is generated using a Texas Instruments
TPS40090 multi-phase controller [43], UCC27223 predictive gate drivers [29] (similar to the UC272222
drivers used on the TPS40090EVM-001 board [33]), and a TPS40120 programmable feedback divider [31]. The TPS40120 data sheet contains a reference design containing these three devices. The
TPS40120 provides a programmable method of changing the FPGA core supply in increments of
25mV. This will allow the optimization of the operating core voltage, i.e., it will be reduced as low
as possible to reduce power dissipation.
The CARMA Board 1.2V supply design procedure was;
The power supply designs on the CARMA board are optimized for small size. The inductors on
each supply are selected from the Vishay/Dale IHLP-2525CZ-01 series of inductors. The other
inductor selection criteria are; limiting the temperature rise to under 30 C, and selecting an
inductance value compatible with the output capacitance value. The output voltage peaking
due to full load current decrease is a function of the inductor value and the output capacitance
value, and the Altera Stratix II FPGA 1.2V core voltage limit for this peaking is 50mV
(p152 [1]). For a 4-phase converter, the energy stored in the four inductors is dumped into the
output capacitance when the load current decreases, i.e.,
1 2
1
1
2
COUT VOUT
+ 4 LIPEAK
= COUT (VOUT + VOUT )2
2
2
2
(158)
where IPEAK = IOUT + IOUT /2. The voltage peaking in a multi-phase converter for a given
per-phase inductor value and total output capacitance is

4L 2
2
I
+ VOUT
VOUT
(159)
VOUT(MAX) =
COUT PEAK
or alternatively, given an inductance value, and a output voltage peak limit, the minimum
output capacitance is
COUT(MIN) =
2
4LIPEAK
2
(VOUT + VOUT )2 VOUT
(160)
The inductance selection starts with an initial valued determined from the following parameters; VIN = 12V, VOUT = 1.2V, D = 0.1, IOUT = 60A, NPHASES = 4 (4-phases), per-phase
current IOUT PH = 15A, 20% ripple current IOUT = 0.2IOUT PH = 3A, and switching frequency f = 500kHz, which gives L = 0.72H. For VOUT(PEAKING) = 50mV, the minimum
output capacitance with this size inductor, and IPEAK = 16.5A, is COUT(MIN) = 6400F. Each
phase of the converter could be decoupled with 2 to 3 POSCAP capacitors, i.e., a total of
8 to 12 capacitors could be used. The capacitance value required tor each capacitor is then
from 800F down to 533F. These are fairly large capacitance values, so selecting a smaller
inductor size is recommended, as this will result in a lower output capacitance value requirement, however, the increased ripple current may require improved (lower) ESR in the output
capacitance.
Table 14 shows the power handling characteristics of some Vishay IHLP-2525CZ-01 [4] series
inductors, along with the output capacitance required to keep voltage peaking under 50mV
(f = 500kHz, VIN = 12V). The temperature rises in the table were estimated from the IHLP
data sheet temperature plots. The IHLP-2525 inductors use a small 0.25-inch by 0.25-inch
package, eg. see the inductor used on the TPS54010 evaluation board in Figure 85.
A 0.47H inductor for each phase requires a total output capacitance of 4592F. This capacitance can be implemented using multiple parallel Sanyo TPE-series POSCAP capacitors, eg.,
148
CARMA Correlator
December 4, 2006
Table 14: FPGA core voltage inductor power handling and minimum output capacitance requirement.
L
(H)
RDCR(MAX)
(m)
IOUT
(A)
IPEAK
(A)
IRMS
(A)
2
IRMS
RDCR
(mW)
T
( C)
COUT(MIN)
(F)
0.20
0.22
0.33
0.47
0.68
0.82
3.0
2.8
3.9
4.2
5.5
8.0
10.8
9.8
6.5
4.6
3.2
2.6
20.4
19.9
18.3
17.3
16.6
16.3
15.3
15.3
15.1
15.1
15.0
15.0
704
652
891
952
1242
1805
15
18
25
30
35
45
2718
2847
3598
4592
6110
7129
ten 470F 4TPE470MCL capacitors. The 4TPE470MCL has a voltage rating of 4V, ESR of
12m, and RMS current rating of 3.5A. The peak-to-peak ripple current from each phase is
4.6A, so ignoring the eects of multi-phase ripple current cancellation, with ten 12m capacitors in parallel, the outut ripple voltage would be 5.5mV. Ripple current cancellation will
reduce that further. A load current increase of 60A will cause an ESR-induced voltage drop
of 72mV, which exceeds the 50mV requirement, so either lower-ESR is required, or additional
capacitors are required. The CARMA board schematic has 12 470F capacitors on the
output of the 1.2V FPGA core supply.
2. Operating frequency (p12 [43]).
The device start-up frequency is set to 475kHz using a 64.9k resistor. The controller the
synchronizes to a 500kHz signal on the EN/SYNC input.
3. Internal regulator power-up (p9 [43]).
The BP5 ramp time is set using a pair of 4.7F capacitors;
tBP5 =
4.5 CBP5
= 5.3ms
8 103
(161)
4. Soft-start (p10 [43]).

The soft-start ramp time is set using a 36nF capacitor;
tSS =
0.7 CSS
= 5.0ms
5 106
(162)
5. Current-limit (p11 [43]).

The voltage on the ILIM pin sets the peak output current, according to VILIM = 2.7IPEAK RCS ,
where RCS is the current-sense resistance. The CARMA board uses the inductor DCR resistance for current-sensing, so RCS = RDCR = 4.2m. The current-limit voltage is set to 200mV,
using a 24.9k and 10k resistance from the 0.7V reference. The peak per phase current is
then
IPEAK =
200mV
= 17.6A
2.7 4.2m
(163)
i.e., slightly higher than the full-load peak inductor current.

149
CARMA Correlator
December 4, 2006
6. MOSFET selection.
The UCC27223 gate drivers use predictive gate-drive logic, which minimizes the deadtime
between high-side and low-side MOSFET switching, and virtually eliminates power loss due
to low-side MOSFET diode conduction. Reference [51] contains a comparison of dierent gate
drive techniques.
The TPS40090EVM-001 is designed to generate 1.5V at 100A. The evaluation board uses a
Vishay/Silconix Si7858DP MOSFET for the high-side switch, and a pair of Si7858DPs for the
low-side switch. The Si7858DP has an on resistance of RDS(ON) = 3m at VGS = 4.5V, and a
switching charge of QG(SW) = 13nC (as dened by Fairchild AN6005 [46]).
Using the MOSFET analysis procedures described in Fairchild application note AN6005 [46],
the International Rectier IRF6617 was selected as the high-side MOSFET, and the IRF6618
was selected as the low-side MOSFET. The IRF6617 has an on-resistance of RDS(ON) = 7.9m
at VGS = 4.5V, and a switching charge of QG(SW) = 5nC, while the IRF6618 has an onresistance of RDS(ON) = 2.2m at VGS = 4.5V, and a switching charge of QG(SW) = 19nC.
The UCC27221 gate drivers generate a 6.5V gate drive voltage, so the on-resistance will be
lower than that at VGS = 4.5V.
The AN6005 analysis estimated the following for each MOSFET;
High-side MOSFET;
Total power dissipation: 0.807W
Junction temperature: 96.8 C
On-resistance : 8.1m
Low-side MOSFET;
Total power dissipation: 0.624W
Junction temperature: 78.1 C
On-resistance : 2.0m
The eciency of the supply was estimated as 92.6% under 15A load. Figure 107 shows the
supply eciency for dierent load currents and input voltages. The eciency plot only includes
MOSFET and gate driver power loss, it does not include inductor loss. So for example, under
a 15A load the MOSFET and gate drive loss is 807mW plus 624mW, and from Table 14 the
inductor loss is 952mW, so the total loss is 2.383W, giving a supply eciency of 88.3%. There
are no other signicant power loss components, eg. the input and output capacitance power
loss is small. The IRF6618 was also tested for use as the high-side MOSFET, however, its
power dissipation was estimated at 1.695W, and its junction temperature at 126 C.
7. Switching-node snubber circuit design.
The switching-node of each supply phase contains an RC-snubber network with values that
match the TPS40090EVM-001. The power dissipated by the snubber resistor is given by
2
PR(SNUBBER) = CSNUBBER VIN(MAX)
f = 1nF 14V2 500kHz = 0.098W
(164)
The snubber resistor should be rated to at least 0.25W to allow for tuning of the circuit (which
may require larger capacitance). A 1206-size resistor should be used.
8. Current-mode control compensation.
The highest load current of 60A, gives an eective load resistance of RLOAD = 1.2V/60A =
20m. The pole produced by the load resistance and output capacitance (12 470F) will be
located at
1
1
= 1411Hz
(165)
fOUT =
=
2RLOAD COUT
2 20m 5640F
150
CARMA Correlator
December 4, 2006
100
95
Efficiency
90
85
80
Vin=10V
V =12V
in
Vin=14V
75
70
0
8
10
Output current
12
14
16
Figure 107: TPS40090 FPGA 1.2V core voltage supply eciency. The supply eciency exceeds 90%
for load currents of 5A to 15A.
The zero from the POSCAP capacitors occurs at
fESR =
1
2RESR COUT
1
= 28kHz
2 12m 470F
(166)
and the lower-valued ceramic capacitors in parallel with these output capacitors (located near
the MOSFETs) will generate a pole and higher frequency zero.
The CARMA board uses a Type II compensation network (since that was sucient on the
100A TPS40090EVM-001), and has an allowance for a Type III network. The TPS40120
programmable divider contains the 10k error amplier input resistor, while the board contains
a compensation feedback network consisting of a 330pF capacitor in parallel with a series 10k
resistor and 9.1nF capacitor. These components place the compensation zero close to the load
pole, i.e.,
fZ =
1
= 1749Hz
2 10k 9.1nF
(167)
and the compensation pole above the ESR zero, i.e.,

fP =
1
= 48kHz.
2 10k 330pF
(168)
A 49.9 resistor has been included in the feedback loop for measuring the loop-gain of the
controller. If the closed-loop bandwidth is insucient, then a Type III compensation network
151
CARMA Correlator
December 4, 2006
CARMA Board inductor temperature tracking
Inductor relative resistance
1.3
1.2
1.1
0.9
0.8
10
20
30
40
50
60
Temperature (degreesC)
70
80
90
100
Figure 108: TPS40090 temperature compensated inductor current-sense compensation. The blue
line is the relative temperature coecient of copper, K(T ) = 1 + 0.004 (T 25 C), while the
red line is the temperature compensated network response. The + and mark the temperatures
selected in the design procedure where the compensation curve matches the copper curve.
can be used to increase the mid-frequency compensation-network gain and increase the closedloop bandwidth.
9. Inductor current-sense temperature compensation.
Procedures for designing a temperature compensated inductor current-sense resistor network
can be found in the TPS40090 and TPS40100 data sheets. The design equations from the
TPS40100 data sheet were coded into a MATLAB program, several Vishay NTHS-series negative temperature coecient (NTC) thermistor tables were copied from the tables in reference [5] and converted to MATLAB arrays, the MATLAB program was then used to select
an appropriate resistor network for a given inductor and NTC value. Figure 108 shows the
compensation network response relative to the nominal temperature response of the inductor.
The plot in Figure 108 is the compensatation network response for a 0.43H inductor with
a DC resistance of 4.2m. The compensation network uses a 100k NTC resistor (Vishay
NTHS0603N01N1003J), and a 10nF capacitance, and the TPS40100 design procedure leads to
1% standard resistor values of RF1 = 14.0k RF2 = 15.8k and RF3 = 66.5k, where these
reference designators are those used by the TPS40100 design procedure.
152
CARMA Correlator
7.2.3
December 4, 2006
FPGA I/O voltages; 1.5V and 2.5V at 5A
The FPGA 1.5V inter-FPGA I/O, and 2.5V LVDS voltages are generated using TPS40100 synchronous buck regulators operated in a 2-phase conguration (externally synchronized 180-degrees
out of phase) [37]. The switching frequency is 500kHz, and the output current for each supply is
nominally 5A, but the circuit requirements for an 8A load are also considered. For 20% current
ripple at a 5A load, at a 500kHz switching frequency, with an input voltage of between 5V and
12V, the recommended inductor value for the 1.5V supply is between 2.1H and 2.6H, and for the
2.5V supply is between 2.5H and 4H. Since these ranges of inductor values are similar, a common
design (diering only in the output voltage set resistors) is possible. A common design for the 1.5V
and 2.5V supplies is desirable as it minimizes the bill-of-materials.
The CARMA Board 1.5V and 2.5V supply design procedure was;
Table 15 shows the properties of a selection of Vishay IHLP-2525CZ-01 inductors [4]. These inductors use a small 0.25-inch by 0.25-inch package, eg. see the inductor used on the TPS54010
evaluation board in Figure 85. Table 15 estimates the inductor power dissipation using
2
2
RDCR , since IRMS = IOUT 1 + IOUT
/12 IOUT , and the eect of IOUT is marIOUT
ginal (a few milli-Watts). The estimates for temperature rise of the inductor, T were read
from the IHLP-2525CZ-01 data sheet performance graphs [4]. The power supply inductor
selection criteria includes limiting the temperature rise to 30 C.
Table 16 shows the 1.5V and 2.5V supply ripple current estimates for the IHLP-2525CZ-01
inductor values shown in Table 15. For the 1.5V supply with a 5A load current, and a target
ripple current of 20% (1A), the 2.2H or 3.3H inductors are suitable choices. With a 12V
input supply, the ripple current for the 2.2H inductor would be 1.2A (24% of 5A), while the
for the 3.3H inductor it would be 0.8A (16% of 5A). For the 2.5V supply with a 5A load
current, the 3.3H inductor is a suitable choice. With a 12V input supply, the ripple current
would be 1.2A (24% of 5A).
If the maximum load current requirement for both supplies was increased to 8A, then a 1.5H
inductor would be more suitable for both supplies to limit the power dissipation to under 1W,
and the inductor temperature rise to under 30 C. The 1.5H inductor would result in a 1.5V
supply ripple current of 1.8A (23% of 8A), and a 2.5V supply ripple current of 2.6A (33% of
8A).
The inductor selection inuences the output capacitance requirements, as does the output
voltage. For example, if the peak-to-peak voltage ripple requirement for both the 1.5V and 2.5V
supplies is VOUT = 100mV, the voltage peaking requirement is VOUT(PEAKING) = 50mV,
and so for IOUT = 5A, IOUT = 1.2A, and L = 3.3F (the largest inductor option), then
the minimum amount of output capacitance to limit the voltage peaking due to load current
decrease is 679F for the 1.5V supply, and 410F for the 2.5V supply. If there is a load current
increase of 5A, then the ESR requirement is RESR < 50mV/5A = 10m, and if an 8A load
is to be supported, the ESR should be smaller still. A pair of Sanyo TPE-series POSCAP
capacitors would provide suitable total capacitance (with an allowance to increase the total),
with suciently small ESR, eg. the 470F 4TPE470MCL has a voltage rating of 4V, ESR
of 12m, and RMS current rating of 3.5A. With an output capacitance consisting of a pair
of these 470F capacitors, the 1.2A ripple current would produce a 7mV ripple voltage, an
5A load increase would cause a voltage dip of 30mV, and an 5A load dump would cause a
voltage peak of 36mV on the 1.5V supply, and a peak of 22mV on the 2.5V supply. The 8A
load current version of the supplies would use a smaller 1.5H inductor, so its output voltage
ripple would also be acceptable with this output capacitance; eg. the 1.5V supply would have
1.8A ripple current, 11mV ripple voltage, 48mV voltage dip, and a 42mV voltage peak, while
153
CARMA Correlator
December 4, 2006
Table 15: FPGA I/O voltage inductor power handling.
L
(H)
Inductor
RDCR (max)
(m)
0.68
0.82
1.0
1.5
2.2
3.3
4.7
5.5
8
10
15
20
30
40
IOUT = 5A
2
IOUT
RDCR T
(mW)
( C)
138
200
250
375
500
750
1000
5
5
8
8
15
20
30
IOUT = 8A
2
IOUT
RDCR T
(mW)
( C)
352
512
640
960
1280
1920
2560
8
10
15
25
40
70
95
Table 16: FPGA 1.5V and 2.5V I/O supplies ripple current.
L
(H)
0.68
0.82
1.0
1.5
2.2
3.3
4.7
Ripple current, IOUT

VOUT = 1.5V
VOUT = 2.5V
VIN = 5V VIN = 12V VIN = 5V VIN = 12V
(A)
(A)
(A)
(A)
3.1
2.6
2.1
1.4
1.0
0.6
0.4
3.9
3.2
2.6
1.8
1.2
0.8
0.6
3.7
3.0
2.5
1.7
1.1
0.8
0.5
5.8
4.8
4.0
2.6
1.8
1.2
0.8
the 2.5V supply would have 2.6A ripple current, 16mV ripple voltage, 48mV voltage dip, and
a 27mV voltage peak.
The 1.5V and 2.5V supplies both use an IHLP-2525CZ-01 3.3H inductor, and a pair of
4TPE470MCL 470F output capacitors.
2. Operating frequency (p9 [37]).
The device start-up frequency is set to 475kHz using a 100k resistor. The controller then
synchronizes to a 500kHz signal on the SYNC input.
3. Soft-start (p22 [37]).
The soft-start ramp time is set using a 150nF capacitor;
tSS =
VFB CSS
0.69 150nF
= 5.2ms
=
ISS
20A
(169)
4. Current-sense amplier gain (p14 [37]).

The amplier gain is set to the recommended gmCSA = 280S using a 274k resistor.
154
CARMA Correlator
December 4, 2006
5. Current-limit (p24 [37]).

The current-limit is set via a 24.9k resistor on the ILIM pin to;
IPEAK =
VILIM
1.48V
= 7.1A
=
gmCSA RDCR RILIM
280S 30m 24.9k
(170)
6. MOSFET selection.
The 1.5V and 2.5V supplies each use an IRF6617 for the high-side MOSFET and an IRF6618
for the low-side MOSFET. The MOSFETs were selected to match those used for the 1.2V core
supply. These MOSFETs are more than adequate for these lower-current supplies.
7. Switching-node snubber circuit design.
See the 1.2V snubber circuit design comments.
8. Current-mode control compensation.
The TPS40100EVM-001 uses a Type III compensation network, so the same type of network
was designed for the CARMA board 1.5V and 2.5V supplies. The eective load resistance of
the 1.5V supply with a 5A load is RLOAD = 0.3, and for the 2.5V supply with a 5A load is
RLOAD = 0.5, which reduces to 0.3 for an 8.3A load. At a nominal operating load of 5A
for both supplies, the 1.5V supply will have the highest load-induced pole in its power-stage
gain. The compensation network can be designed for the 1.5V supply and reused for the 2.5V
supply.
The 1.5V supply power-stage gain pole caused by the interaction of the eective load resistance
and the two 470F output capacitors is located at
fOUT =
1
= 564Hz
2 0.3 940F
(171)
1
1
= 28kHz.
=
2RESR COUT
2 12m 470F
(172)
2RLOAD COUT
and the capacitance ESR zero is located at

fESR =
The Type III compensation network zeros and poles are congured as follows;
fZ1 = 904Hz
fZ2 = 995Hz
fP1 = 9.9kHz
fP2 = 29.4kHz
(173)
i.e., the two zeros are placed just above the load pole, the rst pole is placed at about 10kHz,
and the second pole is placed near the ESR zero. Figure 109 shows the response plots. The
closed-loop frequency of the supply is about 40kHz.
9. Inductor current-sense temperature compensation (p11 [37]).
The TPS40100 current-sense amplier has a temperature coecient of -2000ppm/C to oset
the 4000ppm/C temperature coecient of the resistance of the copper in the inductor. The
MATLAB temperature compensation network design program used for the TPS40090 inductor
current-sense resistance compensation network was applied to the TPS40100 design. Figure 110
shows the compensation network response relative to the nominal temperature response of the
inductor plus the current-sense amplier temperature coecient, i.e., the network compensates
for a total temperature coecent of 2000ppm/C.
155
CARMA Correlator
December 4, 2006
CARMA Board 1.5V Supply Compensation
100
80
60
40
dB
20
0
20
40
60
80
0
10
10
10
Frequency (Hz)
10
10
Figure 109: TPS40100 1.5V supply Type III compensation network response. The blue line is the
power-stage gain, the red is the compensation network, and the black is the closed-loop response.
The closed-loop cross-over (circle) occurs at 42kHz with a phase margin of 102-degrees.
The plot in Figure 110 is the compensatation network response for a 3.3H inductor with
a DC resistance of 30m. The compensation network uses a 10k NTC resistor (Vishay
NTHS0603N01N1002J), and a 100nF capacitance, and the TPS40100 design procedure leads
to 1% standard resistor values of RF1 = 1.37k RF2 = 2.32k and RF3 = 4.54k, where these
reference designators are those used by the TPS40100 design procedure.
10. Supply margining control.
The TPS40090 margining pins can be used to increase or decrease the supply voltage by 3% or
5%. The CARMA board contains the appropriate logic to enable the selection of the dierent
margins on both the 1.5V and 2.5V supplies.
156
CARMA Correlator
December 4, 2006
CARMA Board inductor temperature tracking
Inductor relative resistance
1.3
1.2
1.1
0.9
0.8
10
20
30
40
50
60
Temperature (degreesC)
70
80
90
100
Figure 110: TPS40100 temperature compensated inductor current-sense compensation. The blue
line is the relative temperature coecient of copper plus the TPS40100 current-sense amplier
compensation coecient, i.e., K(T ) = 1 + 0.002 (T 25 C), while the red line is the temperature
compensated network response. The + and mark the temperatures selected in the design procedure
where the compensation curve matches the K(T ) curve.
7.2.4
FPGA pre-driver supply; 3.3V at 1A
The FPGA 3.3V pre-driver supply requirements are;

On/o control.
Monotonic power-on (soft-start).
Maximum current of 1A.
The 3.3V supply could be generated using a switch-mode converter, or a linear regulator. If a
linear regulator was powered from the FPGA custom power supply, and that supply operated at
12V, then the power dissipation at 1A would be (12V 3.3V) 1A = 8.7W, which is excessive.
The CARMA board uses a TPS74201 [44] linear regulator powered from the cPCI 5V supply. The
power dissipation for a 1A load would be (5V 3.3V) 1A = 1.7W, which for JA = 36.5 C
(QFN package) results in a temperature rise of 62 C. The board also includes a stu-option for a
TPS2022 [30] integrated MOSFET switch that can power the FPGA 3.3V pre-driver supply from a
ltered cPCI 3.3V supply. The TPS74201 incorporates a soft-start feature that is congured on the
CARMA board for a 5ms soft-start. The TPS2022 rise-time is internally xed to 6.1ms.
157
CARMA Correlator
December 4, 2006
Mean, RMS, and standard deviation
The mean value of a continuous time signal x(t) over the period t (T1 , T2 ) is
XMEAN
1
= x(t) =
T2 T1
T2
x(t)dt
(174)
T1
the mean-squared of the signal is

XMEAN SQUARED = x2 (t) =
T2 T1
T2
x2 (t)dt
(175)
T1
The root-mean-squared (RMS) is the square-root of the mean-squared. The variance, or standarddeviation squared is given by
x2 = x2 (t) x(t) 2
2
= XMEAN SQUARED XMEAN
(176)
The variance of a signal is equal to its mean-squared value if the mean of the signal is zero.
The buck converter power dissipation analysis uses DC current terms such as IOUT , and RMS
current terms such as IRMS . The RMS current calculation for each circuit component is slightly
dierent, since each current waveform is slightly dierent. For example, the high-side and low-side
switches each alternate conducting current through the output inductor to the load. The steadystate inductor current is a triangular waveform with a DC oset; the DC component is delivered to
the load, while the AC component charges and discharges the output capacitance. The calculation
of the RMS current through the output inductor includes both DC and AC current components,
however, current does not ow through the output capacitors once they have charged, so their mean
current is zero, and their RMS is determined solely by the AC component of the inductor waveform,
i.e., the output capacitor RMS current is equivalent to the variance of the inductor current.
The power dissipation calculations for the buck converter components involves determining the
RMS, or variance of circuit component currents, where the signals are repeating with a period T ,
and contain a signal with a DC oset, and linearly increasing or decreasing current ramps over a
fraction of the period DT , where the duty-cycle D (0, 1). Given a linear signal
x(t) = mt + c
(177)
over time t (0, DT ), the mean over t (0, T ) is

XMEAN =

0
DT
(mt + c)dt

DT
1
1
(mt + c)2
T
2m
0
1
= mDT + c
2
1
= XPP + c
2
(178)
where the peak-to-peak parameter XPP = mDT = x(DT ) x(0) is the increase in signal height
from time t = 0 to time t = DT . The mean of the signal is half the peak-to-peak variation plus the
initial oset c.
158
CARMA Correlator
December 4, 2006
The mean-squared value for the linear signal over t (0, T ) is

2
=
XRMS

0
DT
(mt + c)2 dt
DT

1
1
3
=
(mt + c)
T
3m
0
1
= (mDT )2 + (mDT )c + c2
3
1
2
= XPP
+ XPP c + c2
3
(179)
The variance is over t (0, T ) is

2
2
x2 = XRMS
XMEAN

2

1
1
2
XPP
XPP + c
=
+ XPP c + c2
3
2
2
X
= PP
12
(180)
so the standard-deviation is
XPP
x =
12
(181)
The RMS of the signal can now be written as

XRMS =
X2
2
XMEAN
+ PP
12

= XMEAN
2
XPP
1+
2
12XMEAN
(182)
The RMS of the sum of multiple signals is the square-root of the sum of their mean-squares. For
example, the sum of signals with RMS quantities IA RMS and IB RMS is

2
2
(183)
IRMS = IA
RMS + IB RMS
The RMS of a DC component, is the same as its mean, so the RMS of a DC signal IDC , and an AC
signal with RMS IAC RMS is

2 + I2
IRMS = IDC
(184)
AC RMS
The RMS current in a buck converter output inductor in steady-state has this form; the DC component is delivered to the load, while the AC current charges and discharges the output capacitance.
159
CARMA Correlator
December 4, 2006
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CARMA Correlator: Power Supply Design

3 Buck and synchronous buck converters

5 DDR termination regulators

7 CARMA Board Power Supplies

A Mean, RMS, and standard deviation

Basic circuit components review

The current in a capacitor is related to the change in voltage via

and conversely the current in a capacitor produces a change in voltage via

PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)

.tran 0 10u 0 0.0001u

Figure 1: Basic capacitor circuit with a voltage source.

.tran 0 10u 0 0.0001u

Figure 3: Basic capacitor circuit with a current source.

The voltage across an inductor is related to the change in current via

PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)

Figure 5: Basic inductor circuit with a voltage source.

PULSE(0 1 0 0.5u 0.5u 1.0u 4.0u)

Figure 7: Basic inductor circuit with a current source.

where 0 is the resonant frequency,

where u(t) is the Heaviside step function.

The s-domain response for a unity voltage-step input, is

and the time-domain response is

PWL(0 0 49u 0 50u 1)

Figure 10: LC unity voltage-step transient response.

where 0 is the undamped resonant or natural frequency, is the damping coecient

and d is the damped frequency

v2 (t) = 1 exp(t) cos(d t)

The s-domain response for a unity voltage-step input, is

and the time-domain response is

exp(t) sin(d t) u(t)

drops o with a time constant , where

PWL(0 0 49u 0 50u 1)

Figure 12: RLC unity voltage-step transient response.

Capacitor voltage ripple

PULSE(0 1 0 0.1u 0.1u 0.4u 2u)

.tran 0 10u 0 100p uic

Figure 14: Buck inductor current transient response.

PULSE(0 1 0 0.5u 1.5u 0 2.0u)

Figure 16: Buck capacitor voltage ramp transient response.

PULSE(0 1 0 0.5u 1.5u 0 2.0u)

PWL(0 0 49.999u 0 50u 0.5)

.tran 0 100u 0 100p

Figure 18: Buck capacitor voltage ripple transient response.

current flow with control switch closed

Buck and synchronous buck converters

Continuous-mode and discontinuous-mode operation

A buck converter transistions from continuous-mode to discontinuous-mode when the average

so the transfer function is

giving a discontinuous-mode transfer function of

RMS current analysis

Low-side switch current

Input capacitor RMS current

Normalized RMS current

Normalized RMS current

Normalized RMS current

Highside switch RMS current

Synchronous buck operation

Output capacitance selection

Input capacitance selection

MOSFET and controller parameters

Maximum junction temperature

The maximum junction temperature of a MOSFET can be estimated from

Table 1: Controller parameters used for MOSFET power analysis

where the approximation is valid for C7 C6 .

where the approximation holds for C7 C6 .