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# COUNTERS

Circuits for counting events are frequently used in computers and other digital
systems is called as counter
It can be classified into two broad categories according to the way they are clocked:
1. Asynchronous (Ripple) counters: In asynchronous counter, all the flip-flops are
not clocked simultaneously. The output of the first flip-flop is given to next
flip-flop. It is also called as ripple counter because FF transition ripple from
one flip-flop to another.
2. Synchronous Counters - In asynchronous counter, all the flip-flops are clocked

simultaneously.
ASYNCHRONOUS COUNTER (OR) RIPPLE COUNTER (OR) SERIAL COUNTER
ASYNCHRONOUS UP COUNTER:
CONSTRUCTION:

These counters are constructed by using JK flip-flop with J = K =1. The flip-flop changes
its states during the trailing edge of the clock pulse.

It consists of 3 JK flip-flops connected in cascade. All the JK inputs are tied to Vcc.

The A FF must change state before it can trigger the B FF and the B FF must change state
before it can trigger the C FF.

OPERATION:

Let as assume that all the flip-flops are initially reset to zero. So the content of counter is
000

On the occurrence of negative edge of the 1st clock pulse, the A flip-flop changes its states
to 1 hence after the 1st clock pulse, the output is 001.

During the negative edge of 2nd clock pulse, the flip-flop A changes from 1 to 0, since this
negative change is applied to flip-flop B, it changes its state from 0 to 1, but C flip-flop is
not changed. The output is 010.

TRUTH TABLE:
Coun
t
0
1
2
3
4
5
6
7
8

TIMING DIAGRAM

0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0

STATE DIAGRAM:

## ASYNCHRONOUS DOWN COUNTER:

CONSTRUCTION:

These counters are constructed by using JK flip-flop with J = K =1. The flip-flop changes
its states during the trailing edge of the clock pulse.

It consists of 3 JK flip-flops connected in cascade. All the JK inputs are tied to Vcc.

The A FF must change state before it can trigger the B FF and the B FF must change state
before it can trigger the C FF.

OPERATION:

Let as assume that all the flip-flops are initially reset to zero. So the content of counter is
000

On the occurrence of negative edge of the 1st clock pulse, the A flip-flop changes its states
to 1 hence after the 1st clock pulse, the output is 111.

During the negative edge of 2nd clock pulse, the flip-flop A changes from 1 to 0, since this
negative change is applied to flip-flop B, it changes its state from 0 to 1, but C flip-flop is
not changed. The output is 110.

TRUTH TABLE:
Coun
t
8=0
7
6
5
4
3
2
1
0

TIMING DIAGRAM

0
1
1
1
1
0
0
0
0

0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0

STATE DIAGRAM:

## SYNCHRONOUS COUNTER (OR) PARALLEL COUNTER

SYNCHRONOUS UP COUNTER:
PRINCIPLE:

In this counter, the outputs of flip-flop can change simultaneously because the clock
pulses are applied to the input of all the flip-flop simultaneously.

CONSTRUCTION:

These counters are constructed by using JK flip-flop with FF0 of J = K =1, FF1 of
J=K=Q0, FF2 of J=K=Q1. The clock pulse is applied simultaneously to all the FFs.

Using the reset input, initially all the flip-flops are reset to 0, so the output is 000.

OPERATION:

Let as assume that all the flip-flops are initially reset to zero. So the content of counter is
000

On the occurrence of negative edge of the 1st clock pulse, the FF0 flip-flop changes its
states to 1 hence after the 1st clock pulse, the output is 001.

During the negative edge of 2nd clock pulse, the flip-flop 0 changes from 1 to 0, since this
negative change is applied to flip-flop 1 , it changes its state from 0 to 1, but flip-flop 2 is
not changed. The output is 010.

## The counting continues in fashion until the circuits output is 111.

TRUTH TABLE:
Coun
t
0
1
2
3
4
5
6
7
8

TIMING DIAGRAM

Q2 Q1 Q0
0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0

STATE DIAGRAM:

The most important advantage of synchronous counters is that there is no cumulative time delay
because all flip-flops are triggered in parallel. Thus, the maximum operating frequency for this
counter will be significantly higher than for the corresponding ripple counter.
SYNCHRONOUS DOWN COUNTER:
PRINCIPLE:

In this counter, the outputs of flip-flop can change simultaneously because the clock
pulses are applied to the input of all the flip-flop simultaneously.

CONSTRUCTION:

These counters are constructed by using JK flip-flop with FF0 of J = K =1, FF1 of
J=K=Q0, FF2 of J=K=Q1. The clock pulse is applied simultaneously to all the FFs.

Using the reset input, initially all the flip-flops are reset to 0, so the output is 000.

OPERATION:

Let as assume that all the flip-flops are initially reset to zero. So the content of counter is
000 in Q2Q1Q0 respectively. So output in Q2Q1Q0 is 111

On the occurrence of negative edge of the 1st clock pulse, the FF0 flip-flop changes its
states to 1 hence after the 1st clock pulse, the output is 001 in Q2Q1Q0 and Q2Q1Q0is
110.

During the negative edge of 2nd clock pulse, the flip-flop FF0 changes from 1 to 0, since
this negative change is applied to flip-flop FF1, it changes its state from 0 to 1, but FF2
flip-flop is not changed. The output is 010 in Q2Q1Q0 and Q2Q1Q0 is 101.

The counting continues in fashion until the circuits output is 111 in Q2Q1Q0 and
Q2Q1Q0 is 000.

TRUTH TABLE:
Coun
t
8=0
7
6
5
4
3
2
1
0

TIMING DIAGRAM

0
1
1
1
1
0
0
0
0

0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0

STATE DIAGRAM: