PURPOSE OF PROJECT

The main purpose of the project is to develop a digital logic system using Quartus II to display 2
student IDs.

PROBLEM STATEMENT
Design a circuit diagram by using Quartus II and Model-Sim Altera Software to display the
students IDs. The circuit design must has 1 input (excluding clock) and 8 bits output. Assume
the output will be directly connected to 7 segment display (without using 7448 IC). The output is
used to display the last 4 digits of the ID numbers of BOTH students in sequence when the input
is 0 (zero). The charging state of the input to 1(one) will cause the output to start displaying the
alternate ID numbers of both students immediately for the next clock pulse.

OBJECTIVE
1. Design a circuit diagram to display both students ID number in sequence.
2. Design the circuit diagram by using Quartus II.
3. Show the output in the waveform editor in hexadecimal number.

EQUIPMENT
1. Quartus II Software
2. Model-Sim Altera Software

PROCEDURE:

1. Based on the question given we make the table to figure out the output.

Student Name
Lim Pei Fan
Phua Mei Guan

Decimal (ID Number)

EE087695
EE087732

7 Segment display
(07,7D,6F,6D)
(07,07,4F,5B)

2. Than we try to sketch the input and the output needed to design the circuit diagram. We
decide to use mod 8 counters as the input. From that we create the truth table including
Is,QC,QB,QA as the input and 7 segment part as the output. The truth table as figure below:

IS

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

QC

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

QB

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

QA

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1

0
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0

0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1

0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0

1
0
1
0
1
1
1
1
1
1
0
1
1
1
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

ID

Equivalent

numbe

HEX

r
7
6
9
5
7
7
3
2
7
7
6
7
9
3
5
2

07
7D
6F
6D
07
07
4F
5B
07
07
7D
07
6F
4F
6D
5B

3. From the truth table we make the K-Map for each output to get the Boolean equation. The
K-map are:
Output a:
QBQA
ISQC
00

00

01

11

10

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

a=1
Output b:
QBQA
ISQC

b = ISQA+ ISQB+QCQA+ ISQA

Output c:
QBQA
ISQC

c = QB + QA+ QC

Output d:
QBQA
ISQC

00

01

11

10

00

01

11

10

d = ISQC +ISQCQA+ISQB+ QBQA

Output e:
QBQA
ISQC

00

01

11

10

00

01

11

10

11

10

e = ISQCQBQA+QCQBQA+ISQCQBQA
Output f:
QBQA
ISQC

00

01

00

01

11

10

00

01

11

10

00

01

11

10

f=ISQCQA+QCQBQA+ISQCQA

Output g:
QBQA
ISQC

g=ISQC+QCQB+ISQCQA+QBQA
Output h:

QBQA
ISQC

00

01

11

10

00

01

11

10

h=0
From the Boolean equation we design the circuit using mod 8 counter and using AND
gate, OR gate and NOT gate.

DISCUSSION
The project was about displaying IDs numbers. The main idea of the project is to display
the last 4 numbers of my ID (7695) and my friend ID (7732) using Quatus II. The last 4 IDs
numbers for both students will display in sequence when the input is (Zero) and will display the
IDs alternate when the input is (one). The logic circuit has a one input and 8 outputs. Other than
that the output must display last 4 digits of our ID number and it must be in sequence, where
when the input is set to be zero (0) the output must display 76957732. While when the input is
set to be one (1) the output displays 77679352. These numbers must convert to hexadecimal
number for the final result of the output.
After analyzing and understanding the requirement specifications given earlier, I knew
that there were 12 alphabets (Is,Qc,Qb,Qa), (a,b,c,d,e,f,g,h). I got my project by drowning the truth
table. We make the truth table and simplify it using the K-Map to get the Boolean equation. From
the equation we can design the logic gate circuit. I found that some of the output has a 0 or 1
value. I assumed that if the equation is 0 the output will connect with ground and if 1 the output
will connect with VCC.
I assumed that A is (control 1 or 0) and I have used a counter (7493)
Figure 1 in the circuit connected with a DFF and its truth table is:

D
0
1

Q
0
1

After that I had constructing the circuit by using a (AND, OR, NOT). By simulation, I
obtained the waveform diagram. Instead the output in binary, I was changing them into Hex. So
its much easier to see the output, from the simulation results I noticed that our circuit was
functioning correctly and could get the same output as in the truth table.
We simulate the circuit to see the output. While we make the simulation we get 3 errors,
than we try to trouble shoot our circuit. The errors happen because our connection for one logic
gate in the circuit is not connected.
We simulate the circuit again than we see the output waveform. The output is not as what
we assume. We try to check our circuit connection but the connection is true. We refer to our KMap and the Boolean equation than we see our mistakes where put the input in a wrong sequence
of the K-Map and it causes our circuit design wrong. After that we repair the mistake and try to
simulate the circuit and finally we get the true answer.

CONCLUSION
Based on this experiment we are able to design a circuit to display our own ID numbers.
The output must display the last 4 digit of our ID numbers and it must be in sequence. As the
input we need to set either zero or one. From this experiment we understand that when the clock
is given to the circuit and the input is set to zero than the output will display our ID number in
sequence of 76957732 while if the input is set to one the output will display in sequence of
77679352. These number must shown in hexadecimal number where when the input is zero the
output

is

077D6F6D07074F5B.

But

when

the

input

is

one

the

output

will

show07077D076F4F6D5B. Besides we understand that for the output to produce our own ID
number we get from the application of the 7 segment. From the output we are able to design the
truth table. For the truth table we have 4 inputs and 8 output, where the 3 input from the mod 8
counter and other one we use it to set as input either 1 or zero. From the truth table we can

simplify it using K-Map and make the Boolean equation. We create the circuit by using the logic
gates. By doing this experiment we are applying all the theory that we learn in the class and
finally we are able to create student ID display.

SEMESTER 3 2011/2012

DESIGN CHALLENGE 2: STUDENTS ID DISPLAY

EEEB161 DIGITAL LOGIC DESIGN LAB

NAME:

LIM PEI FAN

ID:

EE087695

NAME:

PHUA MEI GUAN

ID:

EE087732

SECTION :

LECTURER:

NURUL ASYIKIN

SUBMISSION DATE :

24 APRIL 2012