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SEMICONDUCTOR TECHNICAL DATA

  


 

 




   

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET

52 AMPERES
60 VOLTS
RDS(on) = 0.022 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V

Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS

Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous

GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous

Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

52
41
182

Adc

Total Power Dissipation

Derate above 25C

PD

188
1.25

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 )

EAS

406

mJ

Thermal Resistance Junction to Case

Thermal Resistance Junction to Ambient

RJC
RJA

0.8
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

EFET, Designers, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

TMOS
Motorola
Motorola, Inc.
1996

Power MOSFET Transistor Device Data

MTP52N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

66

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
6.4

4.0

Vdc
mV/C

0.019

0.022

1.4
1.2

gFS

17

24

mhos

Ciss

1900

2660

pF

Coss

580

810

Crss

150

300

td(on)

12

20

tr

298

600

td(off)

70

140

tf

110

220

QT

125

175

Q1

10

Q2

30

Q3

40

1.0
0.98

1.5

trr

100

ta

80

tb

20

QRR

0.341

3.5
4.5

7.5

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DrainSource Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

(Cpk 2.0) (3)

Static DrainSource OnResistance

(VGS = 10 Vdc, ID = 26 Adc)

(Cpk 2.0) (3)

VGS(th)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150C)

Ohm

VDS(on)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f = 1.0 MHz)

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc,
Vd ID = 52 Adc,
Ad
VGS = 10 Vdc
Vdc,
RG = 9.1 ))

Fall Time
Gate Charge
(See Figure 8)
((VDS = 48 Vdc,
Vd , ID = 52 Adc,
Ad ,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1)

(IS = 52 Adc, VGS = 0 Vdc)

(IS = 52 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time

(See Figure 14)
((IS = 52 Adc,
Ad , VGS = 0 Vdc,
Vd ,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance

(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

MTP52N06V
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

110

VGS = 10 V
9V

TJ = 25C

8V

7V

90
80
70
60

6V

50
40
30

5V

20

90
25C

80
70
60
50
40
30
10
0

0.035

10

2.5

3.5

4.5

5.5

6.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

0.03

0.025
25C
0.02

0.015

55C

0.01

0.005
0
0

TJ = 55C

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

20

30

40

50

60

70

80

90

100

110

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

20

10
0

0.023

7.5

95

105

TJ = 25C

0.022
0.021
VGS = 10 V

0.020
0.019

15 V

0.018
0.017
0.016
0.015

15

25

35

45

55

75

65

85

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

Figure 4. OnResistance versus Drain Current

and Gate Voltage

100

2
1.75

VGS = 0 V

VGS = 10 V
ID = 26 A

1.5

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE

(NORMALIZED)

VDS 10 V

100
I D , DRAIN CURRENT (AMPS)

110
100

1.25
1
0.75

TJ = 125C

10
100C

0.5
0.25
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

175

10

20

30

40

50

60

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage

Current versus Voltage

MTP52N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
7000

C, CAPACITANCE (pF)

6000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

5000
Crss

4000
3000

Ciss

2000

Coss

1000
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

36
33

QT
10

30
27

VGS

24
21

Q2

Q1

18
15

12
9

ID = 52 A
TJ = 25C

2
Q3

VDS

0
0

20

40

60
80
100
QT, TOTAL CHARGE (nC)

120

6
3
0
140

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP52N06V
VDD = 30 V
ID = 52 A
VGS = 10 V
TJ = 25C

100

tr
tf
td(off)

td(on)

10

1
1

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

55
VGS = 0 V
TJ = 25C

50
I S , SOURCE CURRENT (AMPS)

45
40
35
30
25
20
15
10
5
0
0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

Motorola TMOS Power MOSFET Transistor Device Data

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

MTP52N06V
SAFE OPERATING AREA
450
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE

AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
10 s

100

100 s
1 ms

10

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

dc

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 52 A

400
350
300
250
200
150
100
50
0

100

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

25

50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

MTP52N06V
PACKAGE DIMENSIONS

T
B

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

SEATING
PLANE

F
T

Q
1 2 3

STYLE 5:
PIN 1.
2.
3.
4.

H
K
Z
L

G
D
N

GATE
DRAIN
SOURCE
DRAIN

DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045

0.080

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15

2.04

CASE 221A06
ISSUE Y

Motorola TMOS Power MOSFET Transistor Device Data

MTP52N06V

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals
must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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*MTP52N06V/D*

Motorola TMOS Power MOSFET Transistor MTP52N06V/D

Device Data