EE311 Notes/Stanford Univ.

Prof. Saraswat

Interconnections: Copper & Low K Dielectrics

ITRS 2002 Interconnect Scaling Recommendations

Narrow line effects

Ref: J. Gambino, IEDM Short Course, 2003

Interconnect Scaling Scenarios

50
40

Dealy Time (psec)

30
Al+SiO2
Total Delay

20
Cu+Low-k(2.0)
Total Delay

Gate
Delay

10
9
8
7
6
5
4
3
2
0.1

Cu+Low-k(2.0)
Interconnect Delay
0.2

Al+SiO2
Interconnect Delay
0.3

Feature Size (m)

Scaling need for lower resistivity metal, Low-k

0.4

0.5

0.6

EE 311 Notes/Prof. Saraswat

Copper Interconnect

1
CS1
1

A1
1
A1/S

SCS1

0.5

0.5

Scale Metal Pitch and Height

- R and J increase by square of scaling factor
- Sidewall capacitance unchanged
- Aspect ratio for gapfill / metal etch unchanged
- Drives need for very low resistivity metal with significantly improved EM
performance
1
CS1
1

A1
1

A 1/S2

C S1

0.5

0.5

0.5

Why Cu?

Lower resistivity than Al or Al alloys - reduced RC delay.

Metal
Ag
Cu
Au
Al
W

Bulk Resistivity [!"cm]

1.63
1.67
2.35
2.67
5.65

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Number of Metal Layers

14
12
10

Al/SiO2
Al/Low-k

Cu/SiO2

8
6

Cu/Low-k

4
2
0

0.09

0.13

0.18

0.25

0.35

Technology Generation (m)

Better electromigration reliability than Al alloys.

Al
Melting Point
Ea for Lattice Diffusion
Ea for Grain Boundary
Diffusion

Cu

660 C
1083 C
1.4 eV
2.2 eV
0.4 0.8 eV 0.7 1.2 eV

Ref: S. Luce, (IBM), IEEE IITC 1998

Challenges for Cu Metallization

Limited processing methods: Introduction of Cu must be managed carefully.
Obstacles
- Line patterning: Poor dry-etchability of Cu
- Poor adhesion to dielectrics
3

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Copper is very mobile in SiO2 => Contamination to Si Devices

Increased leakage in SiO2
Increased junction leakage
Lower junction break down voltage

Cu atoms ionize, penetrate into the dielectric, and then accumulate in the dielectric as
Cu+ space charge.

Bias temperature stressing is employed to characterize behavior

- Both field and temperature affect barrier lifetime
- Neutral Cu atoms and charged Cu ions contribute to Cu transport through
dielectrics
- Silicon nitride and oxynitride films are better barriers

Ref: A. Loke et al., Symp. VLSI Tech. 1998

EE 311 Notes/Prof. Saraswat

Fast diffusion of Cu into Si and SiO2

Copper Interconnect

Dielectrics

Poor oxidation/corrosion resistance

Poor adhesion to SiO2
Barrier Layer

Diffusion barrier /adhesion promotor

Passivation

Cu

Difficulty of applying conventional

dry-etching technique

Damascene Process
Typical Damascene Process

Solutions
- Damascene process for patterning
- Using diffusion Barriers
Liners TiN, TaN, etc
Silicon Nitride, PSG

Barriers/Linears

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Barrier Requirements:
Ultrathin films should be good barriers
Low resistance
Chemically stable
Defect free to high temperatures
Barriers:
Transition metals (Pd, Cr, Ti, Co, Ni, Pt) generally poor barriers, due to high
reactivities to Cu <450C
Exception: Ta, Mo, W ... more thermally stable, but fail due to Cu diffusion
through grain boundaries (polycrystalline films)
Transition metal alloys: Can be deposited as amorphous films (stable up to 500C)
Transition metal - silicon compounds: Adding Si to Ta, Ti, Mo, W yields amorphous
refractory barriers with stability to 700C
Amorphous ternary alloys: Very stable due to high crystallization temperatures (i.e.,
Ta36S14,N50, Ti34Si23N43)
Currently PVD (sputtering/evaporation is used primarily to deposit the barrier/liner,
however, step coverage is a problem. ALD is being developed for barrier/liner
application.

ALD

PVD

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Interconnect Fabrication Options

Positive
Pattern

Metal
Etch

Dielectric
Deposition

Negative
Pattern

Dielectric
Etch

Metal
Depos ition

Metal
Dielectric
Metal CMP

Photoresist
Dielectric
Plan arization
by CMP

Subtractive Etch
(Conventional Approach)

Dielectric
Depos ition

Etch Stop
(Dielectric)

Damascene

Conventional approach of metal etch is used for Al

Damascene approach is used for Cu as it cant be dry etched

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Cu Damascene Flow
Cu Damascene Flow Options
Single Damascene

Dual Damascene

Via
Pattern
& Etch

Via &
Lead
Pattern
& Etch

Barrier
& Cu
Dep
Barrier
& Cu
Dep

Cu Via
CMP

Nitride
+ Oxide
Dep

Lead

Cu CMP

Via
Lead
Pattern
& Etch
+
Barrier
& Cu
Dep

Oxide

Lead

Cu Lead
CMP

Copper
Conductive Barrier

Via

Dielectric Etch Stop/Barrier

Options

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Deposition methods

Physical vapor deposition (PVD) : Evaporation, Sputtering

conventional metal deposition technique: widely used for Al interconnects

produce Cu films with strong (111) texture and smooth surface, in general
poor step coverage: not tolerable for filling high-aspect ratio features
Chemical vapor deposition (CVD)

conformal deposition with excellent step coverage in high-aspect ratio holes and vias
costly in processing and maintenance
generally produce Cu films with fine grain size, weak (111) texture and rough surface

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Electroplating System for Cu

Dissociation:
CuSO4 Cu2+ + SO42- (solution)
Reduction: Cu2+ + 2e- Cu (cathode)
Oxidation: Cu Cu2++ 2e- (anode)

Direct electroplating on the barrier gives poor results. Therefore a thin layer of Cu is
needed as a seed. It can be deposited by PVD, CVD or ALD.
Good step coverage and filling capability comparable to CVD process (0.25 m)
Compatible with low-K dielectrics
Generally produce strong (111) texture of Cu film
Produce much larger sized grain structure than any other deposition methods through
self-annealing process

10

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Trench Filling PVD vs. Electroplating of Cu

"bottom-up filling"
("superfilling")

non-conformal

void

PVD
Trench Filling Capability of Cu Electroplating

0.13 trenches

0.18 vias

Electroplating

029 vias

Ref: Jonathan Reid, IITC, 1999

11

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Effect of the seed layer on the properties of the final Cu

Seed Layer Texture

Plated
PlatedFilm
FilmTexture
Texture

Seed Layer
Surface Roughness

Plated Film Grain Size

Seed Layer

Electroplated Film

Strong (111) texture

Smooth surface

Strong (111) texture

Large grain size

(Thin, PVD seed preferred)

Scanning electron micrographs of Damascene trenches of 0.13 m width showing

bottom-up filling of Cu electroplating using DC current (demonstrated by Novellus).

Electroplating needs a seeding layer of Cu as electroplating does not occur

at a dielectric or barrier surface. The deposition of the seed layer can be
done by PVD or CVD. The properties of the final Cu layer critically depend
upon the characteristics of the seed layer.

12

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Additives for Copper ECD

Mixture of organic molecules and chloride ion which adsorb at the copper surface during
plating to:
enhance thickness distribution and feature fill
control copper grain structure and thus ductility, hardness, stress, and surface
smoothness
Brighteners
Adsorbs on copper metal during plating, participates in charge transfer reaction.
Determines Cu growth characteristics with major impact on metallurgy
Levelers
Reduce growth rate of copper at protrusions and edges to yield a smooth final
deposit surface.
Effectively increases polarization resistance at high growth areas by inhibiting growth
to a degree proportional to mass transfer to localized sites
Carriers
Carriers adsorb during copper plating to form a relatively thick monolayer film at the
cathode. Moderately polarizes Cu deposition by forming a barrier to diffusion of Cu2+
ions to the surface.
Chloride
Adsorbs at both cathode and anode.
Accumulates in anode film and increases anode dissolution kinetics.
Modifies adsorption properties of carrier to influence thickness distribution.

t = 0 sec

Wafers immersed in plating

bath. Additives not yet
adsorbed on Cu seed.

t = 2 sec

Accelerators
Suppressors
Chloride ions
Levelers

Additives adsorbed on Cu
seed. No current flow.

t = 10 sec

Conformal plating begins.

Accelerators accumulate at
bottom of via, displacing less
strongly absorbed additives.

=
=
c=
L=

t = 20 sec

Accumulation of accelerator
due to reduced surface area in
narrow features, causes rapid
growth at bottom of via.

Ref: J. Reid et al., Solid St. Tech., 43, 86 (2000)

D. Josell et al., J. Electrochem. Soc., 148, C767 (2001)
13

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Lognormal grain size distribution

0.1

(a)

CVD

as-deposited
= 0.161m
0.08 S
= 0.372
0.06

annealed

0.04

S = 0.294m

= 0.344

0.02
0
0.01

0.1

10

D (m)
0.1

(b)

0.08

electroless
plating

0.06

as-deposited
S = 0.150m
= 0.318

0.04
0.02
0
0.01

0.1

(c)

electroplating

0.08

0.1

D (m)

as-deposited
S = 0.863m
= 0.716

10

annealed
S = 2.682m

= 0.435

0.06
0.04
0.02
0
0.01

0.1

10

D (m)
Comparison of grain size distribution of the films deposited by (a) CVD, (b) electroless plating,
and (c) electroplating (S is the median grain size and s is the lognormal standard deviation of the
grain size). Ref: H. Lee, PhD Thesis, Stanford University, 2001

14

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Electromigration
Electroplated Cu has higher resistance to electromigration because of its
grain structure (mostly grain size).

107

263

238

213 C

Time-to-Failure (sec)

grain size
Electroplated Cu
E = 0.89 eV

10

e =1.4 !m
CVD Cu
E = 0.82 eV
a

10

=0.3 !m

10

1.8

1.9

2.0

2.1

2.2

2.3

-3

1/T (10 /K)

Ref: C. Ryu et al., IEEE IRPS 1997

CVD Cu
Electroplated Cu
Electromigration in Cu is strongly affected by grain size and texture, which is
strongly affected by the linear, seed and the deposition method.

15

EE 311 Notes/Prof. Saraswat

Time-to-Failure (sec)

10

Copper Interconnect

263

106

238

213

188 C

(111) CVD Cu
Ea = 0.86 eV

105
(200) CVD Cu
Ea = 0.81 eV

104

103
1.8

1.9

2.0

2.1

2.2

2.3

-3

1/T (10 /K)

Ref: C. Ryu etal., Symp. VLSI Tech. 1998

1 m

(a) t = 2 hrs

5 m

5 m

(b) t = 1 day

(c) t = 60 days

Plan view TEM images showing evolution of grain size as a function of time for Cu films
DC-plated with additives; at 10 mA/cm2. Grain size of the electroplated films increases
with annealing time. (Ref: H. Lee, PhD Thesis, Stanford University, 2001)

16

EE 311 Notes/Prof. Saraswat

Copper Interconnect

1.6
60 days

1.4

10 days

grain size (m)

1.2
1

1 day

0.8
0.6
0.4
0.2

2 hrs

0
0

10

20

30

40

DC plating current density (mA/cm

50
2

Grain size evolution for Cu films DC-plated at different plating current density. (Ref: Ref:
H. Lee, PhD Thesis, Stanford University, 2001)

200
3.5mA/cm2

190

I (111)/ I(200) ratio

7.5mA/cm2

180
10mA/cm2

170

160
20mA/cm2

150
140
0

50

100

150

200

250

Hours

Evolution of texture at room temperature for films DC-plated with

different current density and with additives. (Ref: H. Lee, PhD Thesis,
Stanford University, 2001)
17

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Scaling of Layered Interconnections

W. Steinhgl et al., Phys. Rev. B66 (2002)

Future

Resistivity increases when barriers/liners are used. The main conductor

(Cu or Al) size is scaled down but the surrounding barrier film size is not
scaled to ensure the barrier properties.
Barriers have much higher resistivity
Barrier consumes progressively larger area
Barrier thickness doesnt scale rapidly
Higher aspect ratio => larger barrier area (non-conformal
deposition technology, e.g., PVD)

18

EE 311 Notes/Prof. Saraswat

Copper Interconnect

ALD

IPVD

C-PVD

Resistivity increases as grain size decreases, which in turn is a function

of the film thickness. Grain boundaries cause electron scattering leading
to reduction in mobility.
Electron surface scattering: resistivity increases in future
Reduced electron mobility as dimensions decrease

Copper/barrier interface quality further reduces the mobility

P=0

P=1

Diffuse scattering
Lower Mobility

Elastic scattering
No Change in Mobility
Barrier

Cu

AR=h/w
Aint=AR*w2

19

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Barrier Effect
!b
=
!o

Important parameter: Ab to Aint ratio

!b increase with Abto Aint ratio
Future: ratio may increase

1
Ab
1"
AR * w2

Electron Surface Scattering Effect

!s
=
!o

1"

P: Fraction of electrons
scattered elastically from
the interface
k= d/ #mfp
#mfp: Bulk mean free path
for electrons
d: Smallest dimension of
the interconnect

3(1" P)#mfp
2d

1
)
%1
1 ' 1" e "kX
"
* & X 3 X 5 (1" Pe "kX dX
1

Reduced electron mobility

Operational temperature
Copper/barrier interface quality
Dimensions decrease in tiers: local, semiglobal, global
Technology node (m)

Effective resistivity ( ohm-cm)

0.18

0.15

0.12 0.1

Global
100C

0.07

0.05

P=0
P=0.5
P=1

Al

Cu, P=0.5

0.035

VD

I-P

PV

D
-PV

D:
AL

10n

ALD: 3

nm
m
ALD: 1n

ier

No Barr

Year

20

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Technology node (m)

0.18

0.15

0.07

0.1

0.12

C-P

VD
D
AL

D
I-PV

:1

0n

0.035

P=0
P=0.5
P=1

Al

Semiglobal
Temp.=100 0C

PV

0.05

ALD:

3nm
nm
ALD: 1

No Barrie

Cu, P=0.5

Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April 2002
Technology node (m)

Effective resistivity ( ohm-cm)

0.18

0.15

0.12

0.07

0.1

0.05

0.035

Temp.=100 0C

Local
Local
Temp.=100 0C
Al

D
PV

VD

C-P

D:

AL

P=0
P=0.5
P=1

10n

ALD:

3nm
m
ALD: 1n

No Barrie

Cu, P=0.5

Year

With ALD least resistivity rise

Higher P value => higher mobility
Al resistivity rises slower than Cu

no 4 sided barrier
higher intrinsic resistivity => smaller mfp => smaller thin film
effect

Cross over with Al resistivity possible

21

EE 311 Notes/Prof. Saraswat

Copper Interconnect

Effective resistivity (microohm-cm)

Cu Resistivity: Effect of Chip Temperature

3.6

Technology Node (m)

0.12
0.18
0.07 0.05 0.035
se
ffu
Di

3.2

T=100 0C
stic
Ela

2.8
2.4

se
Diffu

Global

stic
Ela

1.6

T=27 0C
2000

2004

2008
Year

2012

Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April 2002

Higher temperature lower mobility higher resistivity

Realistic Values at 35 nm node: P=0.5, temp=100 0C
- local ~ 5 -cm
- semi-global ~ 4.2 -cm
- global ~ 3.2 -cm

22