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For more details about the Centre Electronique Horloger (CEH) and its
history, please read the article of E. Vittoz on page 7 in this issue.
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2008 IEEE
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TECHNICAL LITERATURE
tial. The incremental linear relationship between
inversion charge and surface potential was first considered by M. Bagheri and C. Turchetti [18], but the
linearization of the inversion charge versus surface
potential was originally proposed in 1987 by the pioneering work of M. Maher and C. Mead [19], [20]. At
that time we did not realize that most of the chargebased formulation, including the effect of velocity saturation, was already present in the model of M. Maher
and C. Mead. Strangely, this work was only published
in the proceedings of a local workshop [19] and in the
Appendix of a book by C. Mead [20]. Clearly it did not
receive the recognition it actually deserved.
Several years later, different groups looked at this
problem of inversion charge linearization. B. Iiguez
and E.G. Moreno [21], [22] derived an approximate
explicit relation between inversion charges and surface potential which included a fitting parameter.
While their first linearization was done at the source
[21], they later obtained a substrate referenced model
[22] based on the original EKV MOSFET model
approach [17], that also included some short-channel
effects. A similar approach was also proposed by
A.I.A. Cunha et al. [23] - [26] who obtained an interpolate expression of the charges versus the potentials
that used the basic EKV model definitions [17]. We
also adopted the inversion charge linearization
approach, since it offers physical expressions for both
the transconductance-to-current ratio and the current
that are valid from weak to strong inversion [27]-[30].
This gave rise to the charge-based formulation of the
EKV model which was the basis of the compact
model that was then extended and coded by my
Ph.D. student M. Bucher. The inversion charge linearization principle was rediscovered once more in
2001 by H.K. Gummel and K. Singhal [31], [32]. Finally, a formal detailed analysis of the inversion charge
linearization process and a rigorous derivation of the
EKV model was finally published by J-M. Sallese et al.
in [33]. Note that this approach actually provides voltages versus currents expressions that cannot be
explicitly inverted. It can nevertheless be easily inverted by using a straightforward Newton-Raphson technique or by an appropriate approximation. Both these
techniques have been used in the final model implementation.
C. The Compact Model Stage
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TECHNICAL LITERATURE
of multi-gate MOS devices and more particularly on
double-gate devices [58], [59].
26
factor to include important effects such as velocity saturation and mobility reduction due to the vertical
field, allowing for a more accurate design for shortchannel devices at high inversion factors. Drain
induced barrier lowering (DIBL) is also included in
the calculation of the voltage gain, since it often dominates the channel length modulation (CLM) effect at
short transistor length and low inversion factors. D. M.
Binkley recently published a book on his work making it the first true reference on the original EKV
design methodology and the many extensions he
developed [60].
For more details on the history of CMOS read-out chip design for particle
physics experiment, please read the article by E. Heijne in this issue.
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TECHNICAL LITERATURE
pressed logarithmically when transformed into voltages and expanded exponentially when converted
back to currents. The voltage swings are hence
strongly reduced making them almost independent of
the supply voltage, which can be reduced to the minimum required for a proper operation of the circuit.
This principle is illustrated by the simple integrator
shown in Fig. 2(a), where the companded voltage
across the linear capacitor C is expanded when transformed to the output current iout using the nonlinear
function f(v), which for log-domain circuit is simply
an exponential function.
It can be shown that, in order to have a linear
transfer function from the input current iin to the output current iout, the current on the capacitor C has to
be inversely proportional to the derivative of the
expanding function f(v). This can obviously easily be
implemented using the exponential I-V characteristic
of bipolar transistor since the derivative remains an
exponential function which can be matched to the
output expander. It leads to the simple translinear
integrator shown in Fig. 2(b). The principle was successfully implemented in several BiCMOS filters by G.
van Ruymbeke and M. Punzenberger [66]-[69]. The
basic integrator used in [68] is presented in Fig. 2(c).
The same concept can also use the exponential characteristic of the MOS transistor in weak inversion,
which was explored by D. Python in his Ph.D. thesis
[70]. The basic CMOS log-domain integrator used in
[70] is shown in Fig. 2(d).
Other innovative circuits taking advantage of the
MOS transistor operating in weak inversion were
developed by R. Fied for the purpose of low-power
analog signal processing. The goal was to emulate the
behavior of large electric power distribution networks
in order to determine their stability [71]. The main
advantages of using an analog VLSI circuit are the
much shorter computation time and lower complexity compared to the classical simulation methods
based on numerical calculations [71]. The limited
accuracy achieved by the analog simulation can be
circumvented by using the solution found by the circuit as initial conditions for the numerical simulation,
greatly speeding up the convergence.
All the circuits mentioned above were operating at
a rather low frequency. Following the exploration
done by other research groups in the US and in
Europe in the 90s to investigate the potential of
CMOS for RF, we also started to work on RF CMOS
design but focused on low-power and low-voltage
circuits for low data rate and short distance wireless
communication targeting applications such as wireless
sensor networks. The goal was to study the feasibility of designing a complete RF CMOS transceiver operating in the ISM 433 MHz band and running at 1-mA
from a 1-V supply voltage. A.-S. Porret, T. Melly and
D. Python designed such a complete transceiver. It
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was running at 1-V, despite the 0.75-V threshold voltages of the 0.5 m process, and consumed around 1mA in receive mode, demonstrating the feasibility of
implementing low-power radio in CMOS [72], [73]. It
also showed that the EKV design methodology could
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TECHNICAL LITERATURE
be extended to the design of low-power and lowvoltage RF-CMOS circuits. This work was then continued at the CSEM, migrating the original design to a
0.18 m standard digital process and including all the
functions required by a wireless sensor node (sensor
interface, ADC, C, embedded low-leakage SRAM,
power management, etc) on a complex system-onchip (SoC) [74]. This set the basis for new RF-CMOS
activity at CSEM that started in 2001 and focuses on
the design of ultra low-power radios for wireless sensor networks [75]. This constitutes a very good example illustrating the technology transfer mission of
CSEM: Ideas are first explored in the academic environment (for example at EPFL) and if successful they
are transferred to CSEM for further improvement and
consolidation before being proposed to industry as a
technology platform that can be customized and
industrialized for a particular application. More recently, this activity has been combined at CSEM with the
development high-Q resonators such as bulk acoustic
wave (BAW) resonators and temperature-compensated
low-frequency MEMS resonators for the implementation of an ultra low-power MEMS-based radio [76]-[79].
IV. CONCLUSION
From its beginning, the EKV MOS transistor model really enabled the design and optimization of new lowpower and low-voltage analog and RF circuits where
most transistors were operating in the weak and moderate inversion regions. Together with the development
of the EKV compact model, a design methodology for
low-power circuits based on the inversion factor was
formulated. This powerful concept allows the optimum
operating point to be chosen and the transistor to be
sized accordingly. The availability of a MOS transistor
model and the related design methodology that is valid
in all modes of operation becomes even more crucial
today. Indeed, with the aggressive downscaling of
CMOS technologies, the operating points of analog and
even RF circuits transistors are more and more shifted
from the traditional strong inversion region towards the
moderate and eventually the weak inversion regions.
ACKNOWLEDGMENT
First I would like to thank Prof. Eric Vittoz who taught
me the art and science of low-power CMOS analog IC
design based on a deep understanding of the operation
and correct modeling of the MOS transistor. I would
also like to thank all my Ph.D. students who pushed
the limit of low-power IC design always a bit further.
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