Akash Rai

B-803, Kesar Garden, Sector 48, NOIDA, UP, INDIA

Tel :+91-99688-42489, +91-95604-01599
Current US VISA: B1 (10 Years)
E-mail: akashrai@gmail.com

Technical Skills:
- Languages: C, C++, Unix shell Scripting, PERL, Python (basic).
- Tools: Visual Studio, MS Project, MS Office, Rational Suite and UML.
- Dev Tools : GDB, , Purify, Quantify, PureCov
- Procedures : RUP
- Version Control Tools : Clear Case , CVS, SVN.
- OS used: Linux, Sun Solaris, MS-Windows NT.
- Design Tools : Virtusdo, Calibre, PrimeTime, MC2, Interra BIST.
- PMP Certification (ongoing)

Work Experience:
- Organisation : Interra Systems, NOIDA, India.
- Current Designation : Management Staff (M1).
- Duration : Jan 2005-Till Date

- Organisation :Interra Systems INC, USA.

- Designation : Project Leader
- Duration : Nov 2007-Feb 2009

- Organisation : ON Semiconductors, Pocatello,

IDAHO, USA.
- Designation : Project Manager (ONSITE
Assignment)
- Duration : June 2006-Nov 2007

- Organisation : Magma Design Automation,

Bangalore Site, India.
- Designation : Member Technical Staff (II).
- Duration : Sept 2003-Jan 2005
- Organisation : STMicroelectronics, NOIDA Site,
India.
- Designation : Design Engineer.
- Duration : Sept 1999- Sept 2003

Highlights
- Acquired $900,000 project for Interra Systems India Pvt Ltd.
- Project Managing a Team of 10 engineers
- Project Lead for 3 Product components (Managing 5 People)
- Elements Developed displayed at DAC (Design Automation Conference) in 2005, 2006,2009
- Participated in numerous Customer Product Evaluations.

Projects Handled:
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Akash Rai.
Project 1) Title: Memory Design Solution: Jan’05 – Till Date
Project Brief:
MC2 automates the design process for standard and embedded memories. MC2 also provides a
platform for seamless migration to new processes.
1a) Power Ring Generation
1b) Power Bridging (Point-to-Point routing)
1c) Tiler Checker
1d) Yield Estimation for Memories (probabilistic DFM model)
1e) Customized Metal Spacing.
 Implementation: C++

Project 2) Title: Customer End Automation: June’06 – Nov’07

Project Brief:
Automation tasks done at customer end (ON Semiconductors) working closely with the memory
design and CAD teams.
2a) Software Design (EDA component) and support for Memory Design.
2b) Memory Compiler Development & Memory Delivery System
2c) Regression Platform (for memory compilers & IP Regression Environment)
2d) Centralized IP Distribution System.
2e) LibGen (Liberty Generation tool)
2f) Multi Site Project Management

Project 3) Title: ASIC Floorplanner: Sep’03-Jan’05

Project Brief:
The ASIC Floorplanner is a complete, hierarchical design planning and prototyping solution that is
fully integrated into Magma’s RTL to GDSII flow to enable designers to manage the complexity of
multimillion-gate designs and reliably achieve timing closure.
3a) Padring placement and routing
3b) Chip Core Estimator
3c) Automatic Pad Placement Engine
 Implementation: C++

Project 4) Title: FPGA Floorplanner: Dec'01-Sep'03

Project Brief:
This purpose of this project is to perform Global Interconnect and Physical Mapping Planning with
respect to Logical (Hybrid Macro and PLB Level) Netlist, under the (User supplied and other)
constraints. The Floorplan with Constraints strives for Timing optimization while doing Physical
Mapping of the Netlist.
Doing floorplanning will provide the optimal seed to the further design implementation tools to
perform its task of layout and to provide optimal result. Specific tasks to be carried out in the
floorplanner subsystem are partitioning of the netlist taking into consideration the Relative location
and absolute blocking constraints, congestivity analysis followed by the placement of macros and
the glue logic.
4a) Physical Hierarchy Generator
4b) Block Constructor
4c) Title: Congestion Estimation Engine
 Implementation: C++

Project 5) Title : Vector Test Bench Generator: Sep'99-June'00

Project Brief :
The project is a Vector Test Bench Generator for validating memory models (RAM & ROM). It
generated elaborate self-testing test vectors that were simulated under Verlog environment to
help determine the bugs in the memory models.
 Implementation: PERL

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Akash Rai.
Education:
Graduation:
Bachelor of engineering (B.E) in Computer Technology (Class of 1999)
Yeshwantrao Chawan College of Engineering, Nagpur University, India.

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Akash Rai.