Analog

Office®
 A key aim is to develop highly accurate models for
transistors and passives such as spiral inductors at
Advancing the frequencies up to 40 GHz. Analog Office software
Design of RFICs enables us to accurately model active devices, passives,
and interconnects on SoS so that our customers realize
first-time-right designs.

Yash Moghe, Design Engineering Manager

Sapphicon Semiconductor

The Analog Office RFIC design environment is a unique user experience as it combines
ease-of-use, flexibility and accuracy with all the tools essential for RFIC design in a
single desktop solution. It also lets you control and seamlessly integrate best-in-class
third-party tools to capture, synthesize, simulate, optimize, layout, extract, and verify
designs from system to final tape-out. Built upon AWR’s Unified Data Model™, Analog
Office software gives you the power to streamline your design process, increase
productivity, and shorten time-to-market.

Productivity-focused Design Flow

Windows UI: simply an elegant interface Since the company was founded in
1994, AWR’s mission has been simple: To provide a superior “high-frequency
design flow,” whether you’re learning a new capability or preparing a final design
for the foundry. Every element of the Analog Office software environment is so
well integrated it’s easy to forget that working behind the scenes is
exceptionally powerful design software.

Unified Data Model: schematic and layout The cornerstone

of AWR’s design flow, our single, object-oriented database is
synchronized at its core, in the database, not through multiple layers
of software. So whether you’re driving the design from the schematic,
simulation, or layout, the Analog Office design environment lets you
take your ideas from concept through simulation and directly to
physical implementation— all in one platform.

Open, standard-based PDKs: true interoperability Analog Office

software lets you export design layouts to an OpenAccess-based
database using interoperable PDK libraries (IPL) so you can access
the same libraries across all design tools from OpenAccess-based
tool vendors. You’ll save time, achieve optimum performance, and
get your product through development faster.

Analog Office software handles mixed-signal user-flexible Design Environment

designs like this complex PLL in a 0.13um
AWR’s Analog Office RFIC design platform is unique in its ability to let you integrate
RFCMOS process.
third-party tools at all stages of the design process.

DRC/LVS: “signed off/approved” links to EDA vendors Analog Office supports

multiple sign off verification flows including PowerDRC/LVS, Mentor Graphic’s
Calibre®, Cadence’s Assura® and open-source ICED. All are easily managed from
within the Analog Office environment.

HSPICE®: direct import of formatted netlists Import HSPICE-formatted encrypted

netlists directly into Analog Office software for ready simulation within the AWR
environment. This makes it possible to bring in legacy designs as well as those
from other groups or companies.
 ANALOG OFFICE
DESIGN FLOW

System Design &

Simulation: VSS

Design Open
Entry Access

Circuit Sim.
Circuit Sim.
HB/APLAC
Spectre
HSPICE

Block/Chip
Layout
EM Socket : seamless integration of third-
™

party EM point tools AWR’s EM Socket interface Spiral

Extraction
AXIEM
allows you to directly and seamlessly integrate popular EM
solvers into the Analog Office design environment. Choose Net
EM Simulator
Extraction
high-frequency EM tools like AXIEM™, CST, and Sonnet, as well as specialized “silicon- ACE/Net-An
CST, Sonnet

wise” tools from OEA International.

DRC & LVS
Calibre,
Innovative Technologies PowerDRC/
LVS
Assura, ICED

All of AWR’s software tools are continually enhanced to ensure they always
Tape-out
represent the state-of-the-art in technology while making sure they serve to
increase your productivity. AWR innovations include:

APLAC® Simulation Technology APLAC high-frequency circuit simulator Analog Office software is a complete
technology ,used by Nokia® mobile phones for more than a decade — today is a analog and RFIC design environment
standard component of the Analog Office design suite. Powerful APLAC engines that’s readily complemented by
deliver efficient simulators tailored for harmonic balance and time-domain analysis third-party EDA tools.
of large-scale and extremely nonlinear RFIC designs. APLAC harmonic balance
simulation is further enhanced by patent-pending Multi-Rate Harmonic Balance
(MRHB™) technology for even more complex designs.

Intelligent Net (iNet™) Technology iNet delivers “on the fly”

interconnect extraction, similar in concept to timing-driven
or wire-driven digital design, yet tailored to the needs of RF
designers. iNet focuses on accurate RF interconnect modeling
and analysis throughout the entire RFIC design process.

ACE™ Automated Circuit Extraction Technology ACE technology

dramatically reduces the time required to perform initial modeling
of complex interconnects by using layout-based models for circuit
extraction - automating identification of transmission lines from
layout and partitioning these structures into pre-existing models.

AXIEM 3D Planar EM Technology AXIEM transforms RFIC

design by enabling EM analysis to be accurate and fast enough
to serve as an upfront design diagnostic utility. AXIEM is tailored
to 3D high-frequency planar components, delivering exceptionally
accurate EM simulation that is fast, efficient and capable to Ring oscillator layout in Analog Office.
handle extremely large and complex designs.
 www.awrcorp.com
www.awr.tv

Analog Office in the Design Process

USA   Linear and nonlinear circuit simulation
Corporate Headquarters
  Layout with parasitic extraction
AWR Corporation
  EM analysis
1960 E. Grand Avenue, Suite 430
  Co-simulation with system tools
El Segundo, CA 90245
  Statistical design and design centering
+1 310 726 3000
  Link to back-end DRC/LVS
+1 310 726 3005 (fax)

Japan Features at a Glance

  High performance harmonic balance and transient solver technologies
AWR Japan KK
Level 5, 711 Building
  •  Harmonic balance

7-11-18 Nishi-Shinjuku, Shinjuku-ku   •  Transient-assisted harmonic balance

Tokyo 160-0023 Japan   •  MRHB multi-rate harmonic balance

+81 3 5937 4803   •  Transient/time-domain

Korea
AWR Korea Co. Ltd.
B-1412, Intellige-II, 24 Jeongja-dong,
Bundang-gu, Seongnam-si,
Gyeonggi-do, South Korea, 463-811
+82.31.603.7772~3

UK
AWR UK
2 Hunting Gate
Hitchin, Herts
SG4 0TJ, UK
+44 (0) 1462 428 428   Transient, AC and noise analysis using both HSPICE and APLAC
  Intelligent Nets (iNets) interconnect extraction technology
Finland
  ACE automatic circuit extraction technology
AWR – APLAC
  EM Socket interface for integration of third party tools:
Lars Sonckin kaari 16
  •  OEA International NET-AN for 3D RLCK extraction
FI-02600 Espoo, Finland
+358 10 834 5900  AXIEM 3D planar EM analysis for upfront design diagnostics and post-
layout verification
France  DRC/LVS tools such as PowerDRC/LVS, Calibre, Assura and ICED
AWR France  Seamless integration with AWR’s Visual System Simulator™ design suite
140 Avenue Champs Elysees for system co-simulation
75008 Paris, France
+33 1 70 36 19 63

Copyright © 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Analog Office, Microwave
Office and APLAC are registered trademarks and Visual System Simulator, AXIEM, ACE, EM Socket, iNet,
Unified Data Model are trademarks of AWR Corporation. All others are property of their respective holders.

BR-AO-2010.5.6