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Microwave

Office®
For PCBs
Advancing the State The integrated flow between the Mentor and AWR tools has
of High-Frequency enabled us to significantly cut our design times. By concurrently
Design Automation designing the RF circuits in the context of the rest of the PCB,
we can also reduce our design and manufacturing re-spins,
which helps us meet aggressive time-to-market goals.

Xavier Leblanc, Hardware Tools Manager, PHC


Alcatel-Lucent

Not so long ago state-of-the-art design was done on the chip, and RF/microwave
engineers designing printed circuit boards (PCBs) were an afterthought. Today
however it’s a far different story. PCB design has not has not only caught up with
cutting-edge IC design, but now faces some of the most difficult problems in the
industry. The complexity of modern wireless devices requires multiple layers on
PCBs, and the need to add additional layers in order to fit all the features makes it
that much more difficult to get the RF right. AWR understands your dilemna—we
System are microwave engineers ourselves and we know the pressure you are under to
Design
produce complex designs that meet demanding specs—and to do it in constantly
shrinking market windows.

the awr RF PCB design flow advantage


Even more than most design flows, RF PCB demands a layout-driven
Circuit
Design design methodology. Component placement combined with multiple route
LVS/DRC types—digital control lines, DC bias, and RF signal path—challenge
designers to get the performance right....directly from the layout. AWR
Design Environment™ (AWRDE) provides the plug-and-play capability that
unifies a schematic-layout data representation with requisite simulation
capabilities and your favorite EM tools. AWR brings it all together in a flow
that lets you get there from the layout even when you need to work from
Simulation
Extraction & Analysis the schematic. The industry-leading and unique AWR environment with its
Unified Data Model (UDM™), ties all design, analysis, and verification views to a
concurrent layout and schematic with an open integration interface for easy access
Layout
to industry-standard component modelling.

AWR’s powerful suite of layout-driven schematic elements makes it easy to


adaptively model your RF signal path. First creating a schematic with your RF-
Much more than a design tool, Microwave critical elements in a design-before-layout phase and then using the very same
Office software is a complete design flow schematic in a layout-driven mode, AWRDE can automatically resize junction
offering all of the essential technologies:
and discountinuity models as you tune, optimize, or re-route your design without
linear and nonlinear circuit simulators,
changing the schematic. This capability even extends to differential lines for QPSK
EM analysis tools, layout-vs.-schematic
checks, statistical design capabilities, and or SerDes applications. If your schematics are just components and wires, AWR’s
parametric cell libraries with built-in DRC. Intelligent Net™ (iNet) technology enables you to design a classical PCB schematic,
forestalling interconnect design and analysis until you get to the layout. iNets
provide the ability to have a wire on the schematic that is routable over many
layers, with an auto via insertion capability that knows how to terminate the route
on whatever pins to which it is connected. A built-in connectivity checker lets you
know about missed or unfinished routes.
AWR Connected for Cadence Allegro
enables the extraction of user-specified
data from large designs to Microwave
Office for verification/simulation.

user-flexible Design Environment


Modern PCBs are not only physically dense, but they are also technologically rich,
combining digital, baseband, thermal control, bias management, and RF, all on
the same board. To keep your designs flowing smoothly into production, AWR
integrates with the most popular and powerful PCB platforms. AWR Connected™
solutions support complete front-to-back integration with Mentor Graphics and
others so that bills of material can go forward into manufacturing and traces come
back for DC-to-daylight EM and interconnect analysis.

AWR Connected for Cadence brings Cadence Allegro and APD integration to
AWRDE for AXIEM™, ACE™ or any EM Socket™ solution. For engineering boards
and prototypes, DXF, Gerbers, and drill files can be exported directly from
Microwave Office layouts.

A HOST OF INNOVATIVE TECHNOLOGIES


ACE circuit extraction AWR’s unique microwave circuit extraction technology,
ACE, does what no other interconnect analysis tool can. It converts your gnarliest
PCBs into the RF/microwave netlist—with all the crossovers, vias, and multi-layer
coupled line models—you would have created if you could create that flawless
schematic of trace models of all your lines. ACE even uses method-of-moments
(MoM) and finite element method (FEM) solvers on the densest parts of your AWR Connected for Mentor Graphics Expedition
design for improved accuracy, without worrying about the lines that don’t matter as enables achieving a concurrent design flow with the
much. And using ACE’s coupling radius discriminator, you can isolate the handful of real-time bidirectional link between the tools.

couplings that are limiting your board’s performance.

AXIEM 3D planar EM technology AXIEM, AWR’s 3D planar EM


simulator has transformed RF and microwave design by enabling
EM analysis to be an upfront design diagnostic utility rather than
a pure back-end post-verification tool. AXIEM is tailored to 3D
high-frequency planar components, the heart of today’s electronic
products. It delivers exceptionally accurate EM co-simulation that
is fast and efficient even with the most complex designs. A host of
port types, even for coplanar and differential, with multiple options
for grounded and groundless de-embedding, AXIEM delivers
accurate and results. And if your PCB comes with an integrated
antenna, AXIEM can handle that too.

Vivaldi antenna simulated in AXIEM.


www.awrcorp.com
www.awr.tv

USA Key Features of Microwave Office


Corporate Headquarters for RF PCBs
AWR Corporation
 AWR Design Environment supports a layout-driven design methodology
1960 E. Grand Avenue, Suite 430
 AWR’s APLAC high-speed, high-capacity harmonic balance and
El Segundo, CA 90245
transient simulator for comprehensive and accurate frequency/time-
+1 310 726 3000 domain simulation
+1 310 726 3005 (fax)  ACE technology delivers fast and accurate interconnect modeling

Japan  iNets technology provides automated interconnect construction

AWR Japan KK  EM Socket for easy access to multiple EM simulation and analysis tools,
including AWR’s ACE, AXIEM and EMSight technologies
Level 5, 711 Building
 AXIEM 3D planar EM solver technology delivers capacity, accuracy
7-11-18 Nishi-Shinjuku, Shinjuku-ku
and speed
Tokyo 160-0023 Japan
 Collaborative PCB design with Mentor, Cadence, others (optional):
+81 3 5937 4803
  • Full PCB, arbitrary sectioning, select traces & proximity
Korea   • Specify layers and shape types
AWR Korea Co. Ltd.   •  Layout and schematic creation in AWR
B-1412, Intellige-II, 24 Jeongja-dong,   • Drawing layers and colors match Allegro
Bundang-gu, Seongnam-si, database
Gyeonggi-do, South Korea, 463-811 •  Schematic place holders for components
+82.31.603.7772~3   •  Uses iNet technology for traces
  •  Ready to simulate
UK
  • Full dielectric and conductor material definition
AWR UK
transfer
2 Hunting Gate
  • Ports automatically added
Hitchin, Herts
  • EM verify with ACE, AXIEM , etc.
SG4 0TJ, UK
+44 (0) 1462 428 428

Finland
AWR – APLAC
Lars Sonckin kaari 16
FI-02600 Espoo, Finland
+358 10 834 5900

France
AWR France
140 Avenue Champs Elysees
75008 Paris, France
+33 1 70 36 19 63

Copyright © 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Microwave Office
and APLAC are registered trademarks and Visual System Simulator, AXIEM, ACE, Analyst, AWR Design
Environment, Unified Data Model, EMSight, Intelligent Net, and X-model are trademarks of AWR Corporation.
All others are the property of their respective holders.

BR-MWO-PCB-2010.5.12