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File Name

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Date

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SDRAM_Power_Calc_10.XLS
1.0
April 10, 2001

E-Mail
Company

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dramsupport@micron.com
Micron Technology, Inc.

Description

Calculates the power consumed by an SDRAM based on system


operating conditions and the device data sheet.

Limitations

Notes

Disclaimer

THIS SPREADSHEET IS FOR ESTIMATING PURPOSES ONLY. ANY


INFORMATION PROVIDED HEREIN IS PROVIDED "AS IS" AND
WITHOUT WARRANTIES OF ANY KIND. MICRON WARRANTS ONLY
THAT ITS PRODUCTS COMPLY WITH MICRON'S SPECIFICATION
SHEET FOR THE PRODUCT AT THE TIME OF DELIVERY; PROVIDED
THAT DEVIATIONS FROM SPECIFICATIONS WHICH DO NOT
MATERIALLY AFFECT FORM, FIT OR FUNCTION OF SUCH
PRODUCT IN THE SYSTEM AND CONFIGURATION IN OR FOR
WHICH IT IS INITIALLY INSTALLED OR QUALIFIED BY CUSTOMER
SHALL NOT BE DEEMED TO CONSTITUTE FAILURE TO COMPLY
WITH SUCH SPECIFICATIONS.
SEE MICRON'S STANDARD TERMS AND CONDITIONS OF SALE
FOR COMPLETE WARRANTY DETAILS.

Copyright 2001 Micron Semiconductor Products, Inc.


All rights reserved

SDRAM Configuration and Data Sheet Parameters


DRAM Density
Number of DQs per DRAM
Speed Grade

Parameter Condition
Maximum VCC
Minimum VCC
IDD0
Maximum Active Current (calculated)
IDD1
Maximum Operating Current
IDD2
Maximum Precharge Power-Down Standby Current
IDD3
Maximum Active Standby Current
IDD4
Maximum Read Burst Current
IDD6
Maximum Distributed Refresh Current
t
CK for current measurements (see current notes)
t
RRD
Minimum activate-to-activate timing (different bank)
t
RC
Minimum activate-to-activate timing (same bank)
Minimum tCK cycle rate

Values that may be updated are shown in green. These


values are taken from the device data sheet.

128 M
8
-7E

Value
3.6
3
131
160
2
50
165
3
7.5
14
60
7

Units
V
V
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns

DRAM Usage Conditions in the System Environment


System VCC
System CK Frequency
Output Load in System
Percentage of time that all banks on the
DRAM are in a precharged state
The percentage of the all bank precharge
time for which CKE is held LOW
The percentage of the at least one bank
active time for which CKE is held LOW
The average time between ACT commands
to this DRAM (includes ACT to same or
different banks in the same DRAM device)
The percentage of clock cycles which are
outputting read data from the DRAM
The percentage of clock cycles which are
inputting write data to the DRAM

3.3
133
25

V
MHz
pF

70%
80%
0%

120
40%
15%

Values that may be updated are shown in green.

ns

System Derating for 128Mb SDRAM (x8, -7E Speed Grade)


Power is calculated after after scaling for VDD. Next, some powers are scaled for frequency effects to derate from test condition to use condition. Finally, these
numbers are scaled for actual system usage. All parameters are calculated and require no user input.

Worst-Case Power Based


on Data Sheet

p(PRE_PDN)

Background power used


during precharge powerdown

Power Derated for


System Usage
Conditions Input Into
this Model

7.2 mW

4.0 mW

p(PRE_STBY)

Background power used


during idle standby

180.0 mW

25.2 mW

p(ACT_PDN)

Background power used


during active power-down

7.2 mW

0.0 mW

p(ACT_STBY)

Background power used


during active standby

180.0 mW

54.0 mW

p(REF)

Background power to
complete refreshes

3.6 mW

3.6 mW

P(REF)

3.0 mW

p(ACT)

DRAM power for ACT/PRE


commands

292.5 mW

146.3 mW

P(ACT)

122.9 mW

p(WR)

DRAM write power

414.0 mW

62.1 mW

P(WR)

52.1 mW

p(RD)

DRAM read power

414.0 mW

165.6 mW

P(RD)

138.8 mW

p(DQ)

DQ output power

172.8 mW

69.1 mW

P(DQ)

57.9 mW

Total DRAM Power Consumed

529.9 mW

Power Scaled for Actual


System CK Frequency and VCC

P(PRE_PDN)
p(PRE_STBY)
P(ACT_PDN)
P(ACT_STBY)

3.4 mW
21.1 mW
0.0 mW
45.3 mW

444.5 mW

128Mb SDRAM with 8 DQs and a -7E Speed Grade

P(ACT)
Total Activate Power

122.9 mW
122.9 mW

P(WR)
P(RD)
P(DQ)
Total Read/Write Power
Total SDR SDRAM Power

52.1
138.8
57.9
248.8
444.5

mW
mW
mW
mW
mW

Device Power (mW)

System is operating at 133 MHz at VCC = 3.3V. Read bandwidth is 53.2MB/s with write bandwidth of 19.95 MB/s. The data bus is
idle 45% of the time. ACT commands are separated by 120ns on average. All parameters are calculated and require no user
input.
Power Consumption Summary
P(PRE_PDN)
3.4 mW
Power Consumption per Device
500.0
P(PRE_STBY)
21.1 mW
P(ACT_PDN)
0.0 mW
450.0
P(ACT_STBY)
45.3 mW
400.0
P(REF)
3.0 mW
350.0
Total Background Power
72.8 mW
300.0
Total Read/Write Pow er

250.0

Total Activate Pow er

200.0

Total Background Pow er

150.0
100.0
50.0
0.0

Power Consumption Breakout

160.0

Pow er (mW )

140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
P(PRE_PDN)

P(PRE_S TBY)

P(ACT_PDN)

P(ACT_S TBY)

P(REF)

P(ACT)

P(WR)

P(RD)

P(DQ)