Energy Summit, Santa Barbara, May 12, 2010

High Speed Transistors

Low Power Transistors for VLSI

Mark Rodwell
University of California, Santa Barbara
Coauthors: HBT
E. Lobisser, V. Jain, A. Baraskar, B. J. Thibeault,University of California, Santa Barbara
Z. Griffith, J. Hacker, M. Seo, M. Urteaga, Richard Pierson, B. Brar
Teledyne Scientific Company
Coauthors: FET
M. A. Wistey*, U. Singisetti, G. J. Burek, A. Carter B. J. Thibeault, A. Baraskar, J. Law, J. Cagnon, C.
Palmstrom, S. Stemmer, A. C. Gossard
University of California, Santa Barbara (*Now at Notre Dame)
E. Kim, P. C. McIntyre
Stanford University
B. Yue, L. Wang, P. Asbeck, Y. Taur, A. Kummel
University of California, San Diego
rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax
High-Speed Transistors
...an overview.
Why Build THz Transistors ? 500 GHz digital logic
! fiber optics

THz amplifiers! THz radios

! imaging, sensing,
communications

precision analog design Higher-Resolution

at microwave frequencies Microwave ADCs, DACs,
! high-performance receivers DDSs
 Changes required to double transistor bandwidth
HBT parameter change
emitter & collector junction widths decrease 4:1
current density (mA/µm2) increase 4:1
current density (mA/µm) constant
collector depletion thickness decrease 2:1
base thickness decrease 1.4:1
emitter & base contact resistivities decrease 4:1
nearly constant junction temperature ! linewidths vary as (1 / bandwidth)2

FET parameter change

gate length decrease 2:1
current density (mA/µm), gm (mS/µm) increase 2:1
channel 2DEG electron density increase 2:1
gate-channel capacitance density increase 2:1
dielectric equivalent thickness decrease 2:1
channel thickness decrease 2:1
channel density of states increase 2:1
source & drain contact resistivities decrease 4:1

constant voltage, constant velocity scaling fringing capacitance does not scale ! linewidths scale as (1 / bandwidth )
THz & nm Transistors: it's all about the interfaces

Metal-semiconductor interfaces (Ohmic contacts):

very low resistivity
Dielectric-semiconductor interfaces (Gate dielectrics):
very high capacitance density
Transistor & IC thermal resistivity.
256 nm InP HBT 150 nm thick collector
Z. Griffith
340 GHz
dynamic
frequency
divider
M. Seo, UCSB/TSC

440 GHz VCO

M. Seo, UCSB/TSC 70 nm thick collector

E. Lind

324 GHz
amplifier
J. Hacker, TSC

60 nm thick collector

204 GHz Z. Griffith

static
frequency
divider
Z. Griffith, TSC
 InP Bipolar Transistor Scaling Roadmap
industry university university appears maybe
!industry 2007-9 feasible

emitter 512 256 128 64 32 nm width

16 8 4 2 1 !"µm2 access #$

base 300 175 120 60 30 nm contact width,

20 10 5 2.5 1.25 !"µm2 contact #

collector 150 106 75 53 37.5 nm thick,

4.5 9 18 36 72 mA/µm2 current density
4.9 4 3.3 2.75 2-2.5 V, breakdown

f% 370 520 730 1000 1400 GHz

fmax 490 850 1300 2000 2800 GHz
power amplifiers 245 430 660 1000 1400 GHz
digital 2:1 divider 150 240 330 480 660 GHz
 128 / 64 nm process: Sputtered Refractory Base
In-situ MBE emitter contacts:
refractory! high J
low contact #: ~0.7 !-µm2
Refractory emitter contact
dry-etched! nm resolution
refractory! high current
Wet/dry etched emitter
dry-etched! nm resolution
Refractory base contacts
low penetration! thin bases
low contact # ~2.5 !-µm2
self-aligned/ liftoff-free

V. Jain
E. Lobisser
128 nm InP DHBT Process
V. Jain
E. Lobisser
 InGaAs FET Scaling Roadmap

Applications
microwave / mm-wave / THz ICs
VLSI
27 nm InGaAs MOSFET with Regrown Source/Drain
Carter, Burek,
Law, Baraskar
 III-V MOSFETs: What Are Our Goals ?
Low off-state current (10 nA/µm) for low static dissipation
! minimum subthreshold slope! minimum Lg / Tox
low gate tunneling, low band-band tunneling

Low delay CFET !V/I d in gates where

transistor capacitances dominate.
Parasitic capacitances are 0.5-1.0 fF/µm
! while low Cgs is good,
high Id is much better

Low delay Cwire !V/Id in gates where

wiring capacitances dominate.
large FET footprint ! long wires between gates
! need high Id / Wg at low voltage
target ~2.5 mA/µm @ 500 mV Vdd
Power In Electronics
Ultra Low Power Logic for Future Computers

A subject of great importance; being broadly pursued.

Can we greatly reduce static and dynamic IC power ?

Modified { transistors, gates, interconnects, singaling}

Alternate logic devices to replace FETs ?
 Logic must Compute

e.g. , problem if input is DC H-field e.g. , problem if input is DC current e.g. , problem if input is at 2 GHz,
and output is 50 GHz spin wave amplitude and output is DC B-field and output is at 25 GHz (parametric gain)
Logic Must Be Robust

e.g. , nondegenerate parametric gain ---bilateral

e.g. clockless tunnel diode logic---bilateral

e.g. clockless Josephson Junction logic---bilateral

Logic Elements Must Communicate

ion / reagent concentration in solution (biology)

wires
gears (adding machines)
optical waveguides
 Parts to Build Computers

What would you use

....to compute ?
....to communicate ?

Gluonics ?
Gravitonics ?

http://en.wikipedia.org/wiki/File:Standard_Model_of_Elementary_Particles.svg
Wires

CMOS VLSI
 The VLSI Power Problem

Low standby power ! increase supply voltage

Low dynamic switching power ! decrease supply voltage

Transistors Exhibit Boltzmann Characteristics
Thermal-Noise-Limited Voltage Swing

No Poisson statistics
(Shot noise) associated with the
capacitor charge
Zero-Resistance wires ! no CV2f dissipation
Trying To Beat C(kT/q ln(Ion/Ioff))2 : Transistor Approaches
gate
N+++
source

channel
P+++
source drain

Appenzeller, Purdue
Seabaugh, Notre Dame
Asbeck, San Diego
Beating CVdd2F Using Linear Amplifiers ... at a cost
Beating C(kT/q ln(Ion/Ioff))2 using optical interconnects
Low Power Logic Using Magnetic Devices ?
Current Signaling Suffers From Static Dissipation
Reducing Power by Scaling FET & IC Dimensions
Reducing Power by Reducing Supply Voltage
Normalized Drive Current Comparison
end