Вы находитесь на странице: 1из 5

CHAPTER-47

POWERPC PROCESSOR AND MICROBLAZE PROCESSOR BASED


EMBEDDED SYSTEM DESIGN FLOW
In this chapter we discussing how an Embedded System is designed
using different core processors like Microblaze and PowerPc Processors.

MicroBlaze processor was developed by Xilinx. This is a 32-bit Soft Core

RISC processor.
Performance Optimization With Enhanced RISC Performance
Computing (PowerPC) family was developed by IBM. This is 32/64-bit
Hard Core RISC processor.

Generic Embedded System Design Process consists mainly


Step 1: Specifications
Step 2: Hardware Design Flow
Step 3: Software Development Flow

Figure 47.1 : Design Flow Diagram


Step 4: Synchronizing Software and Hardware design
Step 5: Generation of Image File

Step 6: Download into Target device


Embedded systems are complex. It is combination of hardware and software.
Generally Embedded System is designed using different tools.
Merging the two design components i.e., Hardware and Software components
so they function as one system creates additional challenges.
So generally embedded development kits are used.
An Embedded Development Kit (EDK) is a suite of tools and IP that one can
use to design a complete embedded processor system.
Xilinx ISE is one of the EDK which supports different processors.
Xilinx ISE: This kit includes all the tools, documentations and IP that are require for
designing systems with embedded IBM PowerPC family hard processor cores
and Xilinx MicroBlaze soft processor cores.
Some of EDK tools in Xilinx ISE are:
Xilinx Platform Studio (XPS) is the development environment used for
designing the hardware portion of embedded processor system
In recent versions XPS is integrated in PlanAhead tool in Xilinx ISE
Software Development Kit (SDK) is an integrated development environment,
complementary to XPS.
SDK is used for C/C++ embedded software application creation and
verification
SDK is built on the Eclipse open source framework .
Hardware IP is used for Xilinx Embedded Proccessors.
GNU compiler and debugger for C/C++ software development targeting the
MicroBlaze and PowerPC processor.
MIcroBlaze processor can be designed on following FPGAs

Spartan-3 family
Spartan-6 family
Virtex-4 family
Virtex 5 family
Virtex 6 famly

PowerPC processor can be designed on following FPGAs


Virtex-4 FX (PowerPC 405 processor)
Virtex-5 FXT (PowerPC 440 Processor)
The design flow for PowerPC and MicroBlaze Processors is similar.

The only difference is IP for PowerPC processor is fixed i.e., IP cannot be

customize. It is Hard Core Processor.


In MicroBlaze Processor IP can be customized. It is Softcore Processor.

PowerPC supports only Big Endianness.


MIcroBlaze Supports both Big Endianness and Little Endianness.

Step-1:Intellectual Property (IP) :

It contains details and specifications of different peripherals like


Bus infrastructures likePLB,OPB,DCR and bridge cores
Memory and memory controller cores
Timers,Clocks,Reset and Interrupts
Inter-processor communication
External peripheral controller
DMA controller
PCI
General purpose IO

In Softcore processors above IP peripherals can be modify .but in Hardcore


processors they are not customizable.

Embedded Design Flow using EDK


Create a new EDK project
Use the Base System Builder(BSB) to construct basic embedded design
Run PlatGen to make HDL instantiations files and netlist for each component
in embedded design.
Create and compile embedded software for design using SDK.
Merge compiled software with bitstream using Data2MEM utility.
Download complete bitstream using iMPACT into target system.
Step-2:Generation of Processor hardware Netlist(Hardware design flow)
Open PlatGen for netlist generation
Input files are .MHS and .MPD
.MHS file defines configuration of the embedded processor system including
the bus architecture, peripherals and processor(s), interrupt request priorities
and address spacing
.MPD file defines configurable parameters with their default values and
available ports for peripheral.
Output files are netlist and .BMM file

Figure 47.2: Embedded Development Overview


Step-3:Software design Flow:
Software development is performed with Xilinx software Development
Kit(SDK)
A hardware image XML file must first be generated for which the software
application will be developed
The SDK software tool will then attach the software project to hardware
It creates software platforms for System software, board support packages and
library packages.
Then creates .ELF file after compile, assemble and link

Figure 47.3 : EDK Tool Flow Chart


Step-4:Merging software and hardware (Co-design)
By using Data2MEM tools both hardware (.bit) file and software(.elf) files are
combined together form a single system.
The output of Data2MEM is .BIT file
Step-5 & 6:Downloading into Target Hardware :

For downloading this .bit file into target hardware iMPACT tool is used
Input to iMPACT tool is .bit file
Output from iMPACT tool is .CMD file
This .cmd file load into target hardware

Оценить