UCSD ECE 30

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UCSD ECE 30

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Topics
ARM Data path
ARM Registers
ARM Modes

Programming ARM

Arithmetic Operations
ARM Condition Codes

ECE 30 Lecture 2

Comparison Operations
Move and Logic Operations
Branch Operations
Shift Options
Multiplication Operations
2

UCSD ECE 30

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UCSD ECE 30

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ARM Datapath

ARM Registers and Modes

User

Supervisor

CPU
Address
Register

PC-bus

ALU-bus

MUX
PC
RAM
Memory

Write
Data
Register

Register
Bank

A-bus

ALU

32 x 8
Multiplier

B-bus
Read
Data
Register

Instruction Decode
& Control

IRQ

Undefined

FIQ

r13_undef
r14_undef

r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq

spsr_undef

spsr_fiq

r0
r1
r2
r3
r4
r5
r6
r7

MUX

Address
Incrementer

Abort

Barrel
Shifter
r13 (sp)
r14 (lr)

r13_svc
r14_svc

NA

spsr_svc

r8
r9
r10
r11
r12
r13_abt
r13_irq
r13_abt
r14_irq
r15 (pc)
cpsr
spsr_abt
spsr_irq

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UCSD ECE 30

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Example Mode Switch

ARM Modes
User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (pc)
cpsr

User: Where most tasks run

FIQ: Entered on a high priority (fast) interrupt
IRQ: Entered on a low priority interrupt
Supervisor: Entered on reset or soft ware interrupt
Abort: Entered on memory access violation
Undef: Entered when an undefined instruction is
encountered

Interrupt

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Contents of CPSRs and SPSRs

31 30 29 28

N Z C V

Not Used

FIQ
r0
r1
r2
r3
r4
r5
r6
r7
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r15 (pc)
cpsr
spsr_fiq

Address
of FIQ
routine

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Assembly Language Basics

7 6 5 4 3 2 1 0
I F T
Mode

Assembly language has one processor operation per

line

N = Negative result from ALU

Z = Zero result from ALU
C = Carry out of ALU or shift out of ALU
V = Overflow from ALU
I = 1 disables IRQ
F = 1 disables FIQ
T = 0 Processor in ARM state
T = 1 Processor in Thumb state
Mode = Processor mode

C-language: a = b + c;
Assembly language: ADD r0, r1, r2

Each assembly language line gets translated into a

one word ( 32 bits ) machine code instruction (by
the assembler program)
Each processor has its own assembly language, to
match its own particular capabilities
ARM is generally a three-operand machine

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The Compilers Job: C to Assembly

Arithmetic Operations

Assume a = r0, b = r1, c = r2, etc.

General form: <Operation>{<cond>}{S} Rd, Rn, Operand2

Where {} indicate an optional part, and:
<Operation> is:
ADD - Rd = Rn + Operand2
ADC - Rd = Rn + Operand2 + carryBit
SUB - Rd = Rn - Operand2
SBC - Rd = Rn - Operand2 + carry - 1
RSB - Rd = Operand2 - Rn
RSC - Rd = Operand2 - Rn + carry - 1
<cond> is: EQ, NE, HS, CS, LO, CC, MI, PL, VS, VC, HI,
LS, GE, LT, GT, LE, AL
Examples:
ADD r0,r1,r2
SUBGT r3, r3, #1
RSBLES r4, r5, #5

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; r0 = r1 + r2
; if CPSC=GT then r3 = r3 - 1
; if CPSC=LE then r4 = 5 - r5
;
and set CPSC with result

C-code

ARM Assembly

a = b + c;

add r0, r1, r2

a = b - c;

sub r0, r1, r2

a = -b + c;

rsub r0, r1, r2

c = e - a;

sub r2, r4, r0

b = b + e;

add r1, r1, r4

a = b - 5;

sub r0, r1, #5

a = 2 - b;

rsub r0, r1, #2

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The Compilers Job: C to Assembly (2)

Assume a = r0, b = r1, c = r2, etc.

C-code

ARM Assembly

add r1, r1, #2

add r2, r2, #5
sub r0, r1, r2
a = b + 2 - (c + 5) (note: the values
of a, b, and c are
all changed by this
code)

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Register Assignment
One important task for the compiler is to decide
what variable name in C-code will correspond with
what register in ARM.
If there are more variables than registers (likely),
values can be swapped back and forth from
memory.
A good compiler makes assignments that require as
few memory swaps as possible.

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Meaning of Condition Codes

ARM Condition Codes <cond>

Very powerful and unique(?) feature of ARM assembly
All ARM instructions have <cond> codes
An instruction is executed only if its <cond> matches
the CPSR
Alternative to branching over instructions ( e.g. if-then-else )
Non-executed instructions take much less time
Also, improves pipelining (explained later)

Instructions dont affect CPSR unless {S} is appended

Except for comparison instructions, which always affect CPSR

Code

Meaning

Binary

EQ
NE
HS/CS
LO/CC
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
NV

ALU result = 0
ALU result 0
C-bit set (Carry)
C-bit clear (No carry)
N-bit set (Negative)
N-bit clear (Non-negative)
V-bit set (Overflow)
V-bit clear (No overflow)
C-bit set and Z-bit clear
C-bit clear or Z-bit set
N-bit = V-bit ( >= )
N-bit V-bit ( < )
Z-bit clear and V-bit set ( > )
Z-bit set or N-bit V-bit ( <= )
Always ( same as no cond )
Never (reserved)

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

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Comparisons

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Logical and Move Instructions

<Operation>{<cond>} Rn, Operand2

Where <Operation> is:
CMP - Set CPSC based on Rn - Operand2
CMN - Set CPSC based on Rn + Operand2
TST - Set CPSC based on Rn AND Operand2
TEQ - Set CPSC based on Rn EXOR Operand2

<Operation>{<cond>}{S} Rd, Rn, Operand2

Where <Operation> is:
AND - Rd = Rn AND Operand2
EOR - Rd = Rn EXOR Operand2
ORR - Rd = Rn OR Operand2
BIC - Rd = Rn AND NOT Operand2 ; Bit clear

Example:
CMP r0, r1

MOV{<cond>}{S} Rd, Operand2 ; Moves between registers

;Compare the values in r0 and r1

;Set the CPSR bits accordingly
;e.g. r0 = 3, r1 = 5, CPSR indicates nonzero negative
TSTEQ r2, #5

MVN{<cond>}{S} Rd, Operand2 ; Moves NOT of Operand2

Examples:
AND r0, r1, r2
BICEQ r2, r3, #7
EORS r1, r3, r0
MOV r0, r1
MOVS r2, #10
MVNEQ r1, #0

;Only if CPSR indicates last comparison

;was equal (EQ) then
;AND r2 with binary 5
;Set CPSR according to result

15

;
;
;
;
;
;

r0
if
r1
r0
r2
if

= r1 AND r2
CPSC=EQ then
= r3 EXOR r0
= r1
= 10 and set
CPSC=EQ then

clear 3 right bits

and set CPSC
CPSC
r1 = NOT 0
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Example Program: GCD

Branch Instructions
Branch: B{<cond>} label

; Jump to label if <cond> is true

Start

Branch with Link: BL{<cond>} label ; Used to call subroutines

Puts the current value of R15(PC) into R14(LR)
To return from subroutine: MOV pc, lr

r0=r1
?

Both instructions are limited to label addresses 32MB

which is the same as 8 million instructions

Stop

N
Y

Examples:
SUBS r0, r1, r2
BEQ isZero
ADD r0, r0, #1
isZero: AND r3, r0, #255
...

BL sub1
AND r3, r0, #255
...

r0=r0-r1

r0>r1
?

r1=r1-r0

sub1: SUB r0, r0, 1

MOV pc, lr

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if - else Statement
C-code
ARM Assembly

Example Code
Normal
gcd: cmp
beq
blt
sub
bal
less:sub
bal
stop:...

Assembler
r0,r1
stop
less
r0, r0, r1
gcd
r1, r1, r0
gcd

if(a==b) {

; reached the end?

}
c = c + 2;

; if r0>r1
; subtract r1 from r0

if (a==b) {

; subtract r0 from r1

ARM Conditional Assembler

gcd: cmp r0, r1
;
subgt r0, r0, r1
;
sublt r1, r1, r0
;
bne gcd
;
....

} else {
}
c = c + 2;
if(a==b) {

if r0>r1
subtract r1 from r0
subtract r0 from r1
reached the end?

}
c = c + 2;
if (a==b) {
} else {
}
c = c + 2;
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lbl1:

CMP r0, r1
BNE lbl1
MOV r2, r3
ADD r2, r2, #2

lbl2:
lbl1:

CMP r0, r1
BNE lbl2
MOV r2, r3
B lbl1
MOV r2, r4
ADD r2, r2, #2

c = d;

c = d;
c = e;

c = d;
e = f;

c = d;
c = e;

CMP r0, r1
MOVEQ r2, r3
MOVEQ r4, r5
ADD r2, r2, #2

; Using condition execution

CMP r0, r1
MOVEQ r2, r3
MOVNE r2, r4
ADD r2, r2, #2

; Using condition execution

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Nested if - else Statement

C-code
if(a != b) {
if(c > d) {
a = a - b;
} else {
a = b - a;
}
} else {
if( a < 0 ) {
a = -a;
}
}
c = c + 2;

switch - case Statement

C-code

ARM Assembly

lbl1:

lbl1:
lbl2:

switch (a) {
case 1: b = a;
break;
case 2: c = a;
break;
case 5: f = a;
break;
default: m = a;
}
a = a +2;

CMP r0, r1
BEQ lbl1
; Outer if cant use cond. exec.
CMP r2, r3
SUBLT r0, r0, r1 ; Inner if uses cond. exec.
SUBGT r0, r1, r0 ;

B lbl2
; End of outer true clause
CMP r0, #0
; Outer else, inner if
RSBLT r0, r0, #0 ; Inner if uses cond. exec.
ADD r2, r2, #2

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C-code

while ( a < b ) {
a = a + a;
}
a = a - b;

ARM Assembly
wlp1:

wlp2:

CMP r0, r1
BGE wlp2
ADD r0, r0, r0
B wlp1
SUB r0, r0, r1

; Using conditional execution

wlp1:
CMP r0, r1
ADDLT r0, r0, r0
BLT wlp1
SUB r0, r0, r1

lbl2:

lbl3:

lbl4:
lbl5:

CMP r0, #1
BNE lbl2
MOV r1, r0
B lbl5
CMP r0, #2
BNE lbl3
MOV r2, r0
B lbl5
CMP r0, #5
BNE lbl4
MOV r5, r0
B lbl5
MOV r12, r0
ADD r0, r0, #2

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while Loops

while ( a < b ) {
a = a + a;
}
a = a - b;

ARM Assembly

for Loops
C-code

ARM Assembly
flp1:

for(a = 0; a < b; a++) {

c[a] = d[a] + e[a];
}
b = b - 1;

flp2:

MOV r0, #0
CMP r0, r1
BGE flp2
LDR r5, [r3, r0 LSL #2]
LDR r6, [r4, r0 LSL #2]
ADD r5, r5, r6
STR r5, [r2, r0 LSL #2]
ADD r0, r0, #1
B flp1
SUB r1, r1, #1

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Shift Instructions

Shift Examples

Shift commands can be appended to other instructions

They apply to Operand2
Can shift by a fixed number of bits,
or by an amount specified in a register
Shift left = multiply by a power of two
Shift right = divide by a power of two (discard remainder)

ADD r0,r1,r1,LSL#2

; r0 = r1*5 = r1 + r1*4

; Want r2 = r3 * 105 = r3 * (16-1) * (8-1)

RSB r2,r3,r3,LSL#4
;r2=r3*15
RSB r2,r2,r2,LSL#3
;r2=r2*7

<Operation>{<cond>}{S} Rd, Rn, Operand2 {<shift> #number}

Where <shift> is:
0
CF
Binary Value
LSL - Logical Shift Left

RSB Rd, Rn, Rn LSL#K gives Rd = Rn * (2K - 1)

MOV Rd, Rn LSL#K gives Rd = Rn * 2K

Binary Value

CF

ARS - Arithmetic Shift Right

Binary Value

CF

ROR - Rotate Right

Binary Value

CF

Binary Value

CF

LSR - Logical Shift Right

ADD Rd, Rn, Rn LSL#K gives Rd = Rn * (2K + 1)

RRX - Rotate Right Extended

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Shifts with Constants

Instead, 8 bits are used for 0 to 255

the remaining 4 bits are used to specify ROR by 0,2,4...30

ROR
ROR
ROR
ROR

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Recommended instruction for ANY load with constant:

LDR Rd, =constant
LDR r1, =7384

These bits could have been used for 0 to 4095

;
;
;
;

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Loading Full 32-bit Constants

Arithmetic instructions have 12 bits reserved for Operand2

This provides constants

0,1,2,...255
0,4,8...256, 260, 264...1020
0,16,32...1024, 1040, 1056...4080
0,64,128...4096, 4160, 4224...16320

26

Assembler will automatically:

see if constant can be generated using MOV
see if constant can be generated using MVN
or initialize memory with constant and load from there

#0
#30 => * 22
#28 => * 24
#26 => * 26

Be aware that 3rd option takes more run time

LDR Rd, =constant is an example of a pseudoinstruction
not an instruction that the hardware actually recognizes
but the assembler translates it into recognizable
instruction(s)

Implemented as third operand to MOV

MOV r0, #57, 26 ; r0 = 57 * 232-26 = 57 * 64 = 3648
Assembler will calculate for you
MOV r0, #4096 => MOV r0, #64, 26
Error reported if the value cant be generated
27

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Multiplication
MUL{<cond>}{S} Rd, Rm, Rs
MLA{<cond>}{S} Rd, Rm, Rs, Rn

Review
ARM Data path

; Rd = Rm * Rs

ARM Registers

; Rd = Rm * Rs + Rn

ARM Modes: USR, SVC, FIQ , IRQ , ABT, UNDEF

Rd and Rm cannot be the same register

PC cannot be used for any register
Takes less time if smaller number is in Rs
M-type ARMS also
UMULL{<cond>}{S}
UMLAL{<cond>}{S}
SMULL{<cond>}{S}
SMLAL{<cond>}{S}

provide:
RdLo,RdHi,Rm,Rs
RdLo,RdHi,Rm,Rs
RdLo, RdHi, Rm, Rs
RdLo, RdHi, Rm, Rs

Arithmetic Operations
ARM Condition Codes, Conditional Execution

;Unsigned
;Unsigned,Accumulate
;Signed
;Signed,Accumulate

Comparison Operations
Move and Logic Operations
Branch, Branch and Link
Shift Options
Multiplication Operations
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