Subject

Microcontroller & Interfacing

(2150306)
Experiment No: 1

Title
Page
Introduction to Architecture and Programming
No.
Model of 8051.
1.1
Date:
DOC. CODE:GECG/BM/MCI/01
Rev. No. : 2.00 / June 2016

Aim: Introduction to architecture and programming model of 8051.

Theory:
The 8051 is a general part number and represents a whole family of microcontrollers known
as MCS51. All microcontrollers in this family have same CPU but different on-chip peripherals.
Thus the instruction set primarily remains the same and controller can be selected on basis of
required peripherals as per the application. Premier features of 8051 are

40 pin chip in DIP package

8-bit CPU
Clock frequency 1 to 16 MHz
4K bytes ROM
128 bytes RAM
Four 8-bit I/O ports
Two 16-bit timers
Full duplex 1 UART for serial
communication
2 External & 3 internal interrupts
Special function register for
configuring on chip registers
64K external code memory space
64K data memory space

A. Pin diagram of 8051

8051 is a 40 pin IC available in DIP
package. The pin diagram is shown in
figure 1. Most of the pins are
multifunctional and their function is
described as follows.
Pin
Pin number 1 to 8

Pin 9 RST
Reset input

Pin 10 [P3.0 (RXD)]

Pin 11[P3.1 (RXD)]

Figure 1.1 Pin Diagram

Description
They have no dual functions and used as I/O lines. Pins from
1 to 8 serve as port1 bit 0 to port1 bit 7 respectively each
individual pin can be configured as either input or output
line.
It is an active high reset pin. When power is first applied,
reset pin should go high and remain high for some time (At
least for two machine cycles) and then goes low. RC circuit is
used at this pin to incorporate above timing. At a threshold
of 2.5V, the reset input reaches a low level and system
begins to run.
Dual function- can be used as port3 bit 0 or in serial
communication to receive data.
Dual function- can be used as port3 bit 1 or in serial

Biomedical Engineering Department, Government Engineering College, Gandhinagar

Subject
Microcontroller & Interfacing
(2150306)
Experiment No: 1

Pin 12[P3.2 (INT0)]

Pin 13[P3.3 (INT1)]
Pin 14[P3.4 (TO)]
Pin 15[P3.5 (T1)]
Pin 16[Port3.6/WR]
Pin 17[Port3.7/RD]
Pin 18 & 19[XTAL1 & XTAL2]

Pin 20 [Vss]
Pin 21 to 28[Port 2 bits 0 to
7/ Address bus A8 to A15]

Pin 29[PSEN Program Store

Enable)

Pin 30 ALE (Address Latch

Enable/ PROG-EPROM
program pulse)
Pin 31 (Vpp/ - ROM
programming
voltage/External Access)

Pin 32 to
39(Port0/Multiplexed Address
& Data bus AD0 to AD7)
Pin 40(Vcc)

Title
Page
Introduction to Architecture and Programming
No.
Model of 8051.
1.2
Date:
DOC. CODE:GECG/BM/MCI/01
Rev. No. : 2.00 / June 2016
communication to send data.
Dual function- serves as either port3 bit 2 in I/O or used as
external interrupt 0 pin.
Dual function- serves as either port3 bit 3 in I/O or as
external interrupt 1 source.
It serves as I/O pin of port3 bit 4 or alternatively when
timer0 is used as counter, it serves as counter0 input.
Dual function- can be used as port3 bit 5 or acts as input to
counter1 when timer1 is used as counter.
This can be used as port3 bit 6 or alternatively as WR signal
while writing to external RAM.
This can be used as port3 bit 7 or alternatively as RD signal
while interfacing (reading) from external RAM.
These pins are used for connecting crystal as a part of clock
circuit. Crystal frequency is the internal clock frequency and
all internal operations are synchronized with this clock.
Ground connection.
Dual functions - When interfacing external memory is used
these pins serve as higher order address bus A8 to A15
respectively. Alternatively they serve as port2 I/O pins from
port2 bit 0 (P2.0) to port2 bit 7 (P2.7).
When external ROM is used to store program this pin
provides read strobe. Note that PSEN is only used for
external ROM read. While RD or WR signals are used for
external RAM. When internal ROM is used PSEN is not
activated.
Dual function while programming internal EPROM,
programming pulse is given at this pin. Alternatively it
serves as ALE- address latch enable used to demultiplex low
order address and data bus (AD) to AD&)
Dual function-while programming internal ROM,
programming voltage (Vpp) is given at this pin. In run time,
decides whether program has to be fetched from internal
ROM or external ROM. if internal ROM is used should be tied
to VCC and if external ROM is used it should be tied to
ground.
Dual functions - When external memory is used these pins
serve as multiplexed low order address bus AD0 to AD7
respectively. Alternatively they serve as port0 I/O pins from
port0 bit 0 (P0.0) to port2 bit 7 (P0.7).
+5 V power supply is given to this pin.

8051 Internal Architecture:

There is no need of any detailed explanation to understand internal architecture of 8051 micro
controller. Just look at the diagram above and you observer it carefully. The system bus
connects all the support devices with the central processing unit. 8051 system bus composes
Biomedical Engineering Department, Government Engineering College, Gandhinagar

Subject
Microcontroller & Interfacing
(2150306)
Experiment No: 1

Title
Page
Introduction to Architecture and Programming
No.
Model of 8051.
1.3
Date:
DOC. CODE:GECG/BM/MCI/01
Rev. No. : 2.00 / June 2016

of an 8 bit data bus and a 16 bit address bus and bus control signals. From the figure you can
understand that all other devices like program memory, ports, data memory, serial interface,
interrupt control, timers, and the central processing unit are all interfaced together through
the system bus. RxD and TxD (serial port input and output) are interfaced with port 3.

Figure 1.2 Internal Architecture of 8051

B. Programming Model of 8051

Programming model represents that part of microcontroller over which user as direct access
through instructions. Programming model is shown in figure 2. Programming model includes
following
a. ROM: 4 K Bytes, address ranging from 0000H to 0FFFH
b. RAM: RAM has following features
4 Register Banks Bank0, Bank1, Bank2 and Bank3 (00h to 1Fh)
Each Bank consists of R0, R1, R2, R3, R4, R5, R6, R7
Bank 0 is the default upon power up of the microcontroller. Other banks can be
selected by programming PSW register.
These registers can be used by their name or by their address
Locations 20h -2Fh are byte as well as bit addressable. Bit addresses are from
00H to 7FH (16 x 8 = 128 bits). These registers/bits can be used by their
addresses.
Locations 30h -7Fh are general purpose RAM. Used only by address
Special Function Register:
Biomedical Engineering Department, Government Engineering College, Gandhinagar

Subject
Microcontroller & Interfacing
(2150306)
Experiment No: 1

Title
Page
Introduction to Architecture and Programming
No.
Model of 8051.
1.4
Date:
DOC. CODE:GECG/BM/MCI/01
Rev. No. : 2.00 / June 2016

21 SFRs in 8051.Address between 80h FFh.

All addresses not used. Attempt to used undefined address may result into
unpredictable behaviour by 8051.
Some SFRs are bit addressable and some are not. They can be referred by their
names or by address.

Biomedical Engineering Department, Government Engineering College, Gandhinagar

Subject
Microcontroller & Interfacing
(2150306)
Experiment No: 1

Title
Page
Introduction to Architecture and Programming
No.
Model of 8051.
1.5
Date:
DOC. CODE:GECG/BM/MCI/01
Rev. No. : 2.00 / June 2016

Special Function Registers in 8051

Byte
Addre
ss
FFh
F0h
E0h
D0h
B8h
B0h
A8h
A0h
99h
98h
90h
8Dh
8Ch
8Bh
8Ah
89h
88h
87
83
82
81
80

Bit Addresses

F7
E7
D7
B7
AF
A7

F6
E6
D6
B6
AE
A6

9F
97

9E
96

8F

8E

87

86

F5
E5
D5
B5
AD
A5
Not
9D
95
Not
Not
Not
Not
Not
8D
Not
Not
Not
Not
85

F4
F3
F2
E4
E3
E2
D4
D3
D2
BC
BB
BA
B4
B3
B2
AC
AB
AA
A4
A3
A2
Bit Addressable
9C
9B
9A
94
93
92
Bit Addressable
Bit Addressable
Bit Addressable
Bit Addressable
Bit Addressable
8C
8B
8A
Bit Addressable
Bit Addressable
Bit Addressable
Bit Addressable
84
83
82

Register

F1
E1
D1
B9
B1
A9
A1

F0
E0
D0
B8
B0
A8
A0

99
91

98
90

89

88

81

80

Register B
Accumulator
Program Status Word (PSW)
Interrupt Priority (IP)
Port 3
Interrupt Enable (IE)
Port 2
Serial Buffer (SBUF)
Serial Control (SCON)
Port 1
Timer 1 Higher Byte (TH1)
Timer 0 Higher Byte (TH0)
Timer 1 Lower Byte (TL1)
Timer 0 Lower Byte (TL0)
Timer Mode Register (TMOD)
Timer Control Register (TCON)
Power Control Register (PCON)
Data Pointer Higher Byte (DPH)
Data Pointer Lower Byte (DPL)
Stack Pointer
Port 0

Figure 1.4 Special Function Registers of 8051

Self Study Questions:

1. What is size of Internal RAM?
2. What is size of Internal ROM?
3. Name registers having 16 bit data width and also write their functions.
4. Name registers which can do division.
5. Give the number of register banks and their addresses.
6. Which port has no alternate functions?
7. Which port has maximum multiple functions?
8. Justify 8051 has 40 Pins, but it can function as if it has 64 Pins.
9. Name the SFRs which are bit addressable.
10. What do you mean by PSEN?
Figure 1.3 Programming Model of 8051

Biomedical Engineering Department, Government Engineering College, Gandhinagar

E0*

F0*

B8*

A8*

89

88*