ISBN:978-1534910799

Proceedings of ICAER-2016

GLITCH free NAND based Digitally Controlled

Delay Lines using Low Power Forced Stack
Clocked Pass Transistor Flip Flop
Mr.Madhusudhana B.S
Dept. of ECE
Sri Siddhartha Institute of Technology
madhu_99917@rediffmail.com

Mrs. G.Jyothi

Abstract---The paper here presents a NAND based digitally

controlled delay that avoids glitches by using various driving
circuits. In NAND based DCDL that is glitch free, control bits are
generated by driving circuits and that consumes the power of
considerable amount and delay time. Driving techniques are
suggested that use Low Power Forced Stack Clocked Pass
Transistor flip-flop (LP-FSCPTFF). That use considerably less
power and lesser delay time than conventional delay lines that use
dual edge triggred flip flops. The proposed technic is designed in
32nm CMOS technology.

HOD, Dept. of ECE

Sri Siddhartha Institute of Technology
Tumkur Karnataka, India
mzkurianbc@yahoo.com

(LP-FSCPTFF), that uses less power and lesser delay time than
that of conventional dual edge triggered flip flops.
II. EXISTING METHODOLOGY
GLITCHING PROBLEM OF NAND BASED DCDL
Figure shows NAND based DCDL is constructed by a series
of delay elements. (DE) shown in the Fig.1. Has each delay
element composed of four NAND gates. Each NAND gates
marked A are the fast input and that marked D are the
dummy cells that are for load balancing. Control bits are used
to control the delay of the delay chain. (Si). The complementary
control bits are S0, S1, S2, S3 and of those control bits S0, S1,
S2 and S3.

Keywords: digitally controlled delay lines (DCDL), glitches, Low

Power Forced Stack Clocked Pass Transistor flip-flop (LPFSCPTFF), phase locked loop (PLL,.dual edge triggered sense
amplifier based flip-flop.

I. INTRODUCTION
A delay-locked loop (DLL) and a phase-locked loop (PLL) are
similar, but unlike PLL, DLL does not have internal voltage
controlled oscillator. The clock rise-to-data output valid timing
characteristic is enhanced by such DLL. DLL also is used for
clock recovery (CDR). A DLL is a negative delay gate placed
in the clock path of a digital circuit. The main key block is a
delay chain. It provides high-bandwidth data transmission rates
in between devices. DLL transmissions dont have low clock
skew for output clock signals, propagation delay and advanced
clock domain control. This DLL fed by a reference clock. DLL
determines the period of that reference clock by adjusting a
feedback loop via the delay line. The loop is locked as the
delayed clock signal matches the incoming clock signal. Clock
skew can not only further increase system clock frequency but
also avoid system malfunction. Phase-locked loops and delaylocked loops have been widely used to overcome the clockskew problem. These kinds of circuits are called clock-deskew
buffers. A DLL has a phase detector (PD) or a phase comparator
(PC), a variable delay line, and a shift register for its operation,
to convert the PDs output signal to a control signal for the
delay line chain. Delay is produced using different driving
circuits that use different power efficient flip flops. Proposed
technic uses Low Power Forced Stack Clocked Pass Transistor
flip-flop

www.iaetsd.in

Dr. M Z Kurian

Dept. of ECE
Sri Siddhartha Institute of Technology
Tumkur Karnataka, India
grandhejyothi@gmail.com

Figure-1. Single glitch when the control code increased

by one.

In a situation if the control code c changes from 1(s=0,1,1,1)

to 2(s=0,0,1,1) glitches occur in two different paths as shown
by the solid lines. Single glitch occurs for one bit variation. The
delay control code c is encoded by the control bits Si. If i<c,
then Si=0 (pass state); if ic, then Si=1 (turn state),i refers the
number of stages, represents control code and Si the controlbits.

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ISBN:978-1534910799

Proceedings of ICAER-2016

CONVENTIONAL NAND DCDL USING DOUBLE

CLOCKED SENSE AMPLIFIER BASED FLIP-FLOP.
The driving circuit that is used in conventional DCDL is the
double clocked flip-flop. It is one among the special flip-flops
which use two different clock signal sources, so that it could
provide two different delays for LH as well as HL transitions.
One among these clock signals is CLH. I.e., Clock signal will
rise when there is low to high transitions. And the other one is
CHL. I.e., Clock signal will fall for high to low transitions. But
this too has disadvantages such as high power consumption and
higher delay time. This special sense amplifier based flip-flop
will have sense amplifier in the first and set-reset (SR) latch in
the next stage respectively. That conventional flip-flop tha is
used is shown in the Figure-4. on the clock rising edges the
sensing stage captures input state and a latch stage provides the
two flip-flop outputs that are detailed in the Figure and can be
analyzed using SR latch that is NAND based or more structures
that are advanced.

Figure-2. Multiple glitches forb the control code increased by two or more.

Figure-2 indicates, when the control code c is switched from

1(s=0,1,1,1) to 3(s=0,0,0,1), there exists four different paths as
shown in red lines. Whenever there are more than one bit
variation that leads to the more number of glitches.
III. GLITCH-FREE NAND BASED DCDL
Glitches that occur could be avoided by the control bits which
are Si and Ti. So that, each delay element in DCDL requires
two sets of control bits Si and Ti that control the DCDL with
the conditions : Consider the state if i<c, then Si=0 also if i c,
then Si=1; and here the control code Ti=1 and Tc+1=0 for
ic+1. The corresponding diagram of glitches free NAND
based DCDL is shown in Figure-3.

Figure-3. Schematic of glitch-free NAND based DCDL

The values of Si and Ti, and the delay element states that cause
these values are shown in the Table-1.

Figure-4. Schematic of existing DCDL with double

clocked sense amplifier based flip-flop.

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Proceedings of ICAER-2016

IV. PROPOSED NAND BASED DCDL

Proposed technic uses a special flip flop in the driving
circuit that is Low Power Forced Stack Clocked Pass Transistor
flip-flop (LP-FSCPTFF). That uses considerably less power
and has lesser delay time.
PROPOSED NAND BASED DCDL WITH LOW POWER
FORCED STACK CLOCKED PASS TRANSISTOR FLIPFLOP (LP-FSCPTFF)
To reduce the leakage power and to improve
synchronization of the components, a novel flip-flop using
forced stack technique is proposed, LP-FSCPTFF. The
schematic is shown in Figure 5 gives us with the idea of
proposed design, where forced stack technique is employed,
and in that by supplying a low voltage power to the stacked
transistors and that results in the transistors off and reduction
of the sub-threshold leakage current hence the power.
Both stack n MOS transistors M5 as well as M6 are off
When clock = 0 , which makes it consume low leakage power.
When D=1 and clock=1; then M3, M5 and M6 is turned on
and M1 will be off resulting in node x discharge from the
ground thus M2 is on as Q attains a high logic value.

Figure 6 : Low Power Forced Stack Clocked Pass Transistor flip-flop (LPFSCPTFF)

V. DCDL APPLICATION IN PLL

In contrast with conventional low power dual edge flip

flops, proposed flip flop uses lesser number of transistors hence
reduces the area, Power also is reduced considerably. And the
flip-flop operates at various temperatures without
compromising the consistency thus shows better results
Compared to other various low power consuming clocking flipflops.

Figure-7 shows the PLL architecture. Four major blocks it has

and they are the loop filter, phase/frequency detector, frequency
divider and digitally controlled delay loop. Phase detector
identifies the difference in phase between the incoming
references signal and outgoing feedback signal that is shown by
the
Figure 8.

Figure-7. Phase detector.

Depending upon the error in the signal the charge pump could
either increases or decreases charge that is of the low pass filter.
This loop filter removes high frequency and then will be applied
to the input of DCDL. The proposed DCDL has better
performances in delay and power consumption. The output
from the DCDL is given to frequency divider. It Generate s the
output signal frequency according to the input frequency given.

Figure 5: Proposed NAND based DCDL using Low Power Forced Stack
Clocked Pass Transistor flip-flop (LP-FSCPTFF)

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ISBN:978-1534910799

Proceedings of ICAER-2016
Conditional Data Mapping Flip Flop (CDMFF), Clock Pair
Shared Flip Flop (CPSFF), Low Power Clocked Pass Transistor
Flip Flop (LPCPTFF), Low Power Forced Stack Clocked Pass
Transistor Flip Flop (LPFSCPTFF). CDFF consumes less
power at 1.7v supply, where in CDMFF power reduction is seen
which is reduced by about 80% at 500 MHz. CPSFF
overshadows this CDMFF by showing reduced power upto
50%. Compared to all other power efficient D Flip Flops the
proposed LPFSCPTFF consumes the least power which is
reduced upto 90%. Simulation is done in Tanner EDA tool 13.0.

VI. SIMULATION RESULTS OF PROPOSED DCDL WITH

LOW POWER FORCED STACK CLOCKED PASS
TRANSISTOR FLIP-FLOP (LP-FSCPTFF)
The simulation results is shown for the DCDL using low power
forced stack clocked pass transistor flip flop, it consumes very
less power in contrast with the existing DCDLs.

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[2] D. D. Caro, C.A. Romani, N. Petra, A.G.M.Strollo and C. Parrella, A 1.27
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[9] B. Nikolic, V. G. Oklobdzija, V. Stajanovic, W. Jia, J. K. Chiu, and M.M.
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Figure-8. Simulation result of proposed DCDL using :Low Power Forced

Stack Clocked Pass Transistor flip-flop (LP-FSCPTFF)

VII. RESULT ANALYSIS

Figure 8. Power consumption plot vs supply voltage

Above plot of power consumption vs supply voltage shows the

power consumption of various low power efficient low power
flip flops like Conditional Dischrge Flip Flop (CDFF),

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