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Proceedings of ICAER-2016
Mrs. G.Jyothi
(LP-FSCPTFF), that uses less power and lesser delay time than
that of conventional dual edge triggered flip flops.
II. EXISTING METHODOLOGY
GLITCHING PROBLEM OF NAND BASED DCDL
Figure shows NAND based DCDL is constructed by a series
of delay elements. (DE) shown in the Fig.1. Has each delay
element composed of four NAND gates. Each NAND gates
marked A are the fast input and that marked D are the
dummy cells that are for load balancing. Control bits are used
to control the delay of the delay chain. (Si). The complementary
control bits are S0, S1, S2, S3 and of those control bits S0, S1,
S2 and S3.
I. INTRODUCTION
A delay-locked loop (DLL) and a phase-locked loop (PLL) are
similar, but unlike PLL, DLL does not have internal voltage
controlled oscillator. The clock rise-to-data output valid timing
characteristic is enhanced by such DLL. DLL also is used for
clock recovery (CDR). A DLL is a negative delay gate placed
in the clock path of a digital circuit. The main key block is a
delay chain. It provides high-bandwidth data transmission rates
in between devices. DLL transmissions dont have low clock
skew for output clock signals, propagation delay and advanced
clock domain control. This DLL fed by a reference clock. DLL
determines the period of that reference clock by adjusting a
feedback loop via the delay line. The loop is locked as the
delayed clock signal matches the incoming clock signal. Clock
skew can not only further increase system clock frequency but
also avoid system malfunction. Phase-locked loops and delaylocked loops have been widely used to overcome the clockskew problem. These kinds of circuits are called clock-deskew
buffers. A DLL has a phase detector (PD) or a phase comparator
(PC), a variable delay line, and a shift register for its operation,
to convert the PDs output signal to a control signal for the
delay line chain. Delay is produced using different driving
circuits that use different power efficient flip flops. Proposed
technic uses Low Power Forced Stack Clocked Pass Transistor
flip-flop
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Dr. M Z Kurian
Dept. of ECE
Sri Siddhartha Institute of Technology
Tumkur Karnataka, India
grandhejyothi@gmail.com
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ISBN:978-1534910799
Proceedings of ICAER-2016
Figure-2. Multiple glitches forb the control code increased by two or more.
The values of Si and Ti, and the delay element states that cause
these values are shown in the Table-1.
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IAETSD 2016
ISBN:978-1534910799
Proceedings of ICAER-2016
Figure 6 : Low Power Forced Stack Clocked Pass Transistor flip-flop (LPFSCPTFF)
Figure 5: Proposed NAND based DCDL using Low Power Forced Stack
Clocked Pass Transistor flip-flop (LP-FSCPTFF)
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IAETSD 2016
ISBN:978-1534910799
Proceedings of ICAER-2016
Conditional Data Mapping Flip Flop (CDMFF), Clock Pair
Shared Flip Flop (CPSFF), Low Power Clocked Pass Transistor
Flip Flop (LPCPTFF), Low Power Forced Stack Clocked Pass
Transistor Flip Flop (LPFSCPTFF). CDFF consumes less
power at 1.7v supply, where in CDMFF power reduction is seen
which is reduced by about 80% at 500 MHz. CPSFF
overshadows this CDMFF by showing reduced power upto
50%. Compared to all other power efficient D Flip Flops the
proposed LPFSCPTFF consumes the least power which is
reduced upto 90%. Simulation is done in Tanner EDA tool 13.0.
REFERENCES
[1] David De Caro, Glitch Free NAND-Based Digitally Controlled Delay
Lines, IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 21, no. 1,
January 2013.
[2] D. D. Caro, C.A. Romani, N. Petra, A.G.M.Strollo and C. Parrella, A 1.27
ghz, all digital spread spectrum clock generator/synthesizer in 65 nm
CMOS, IEEE J. Solid-state Circuits, vol. 45, no. 5, pp. 10481060. May 2010.
[3] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A wide power supply
range, wide tuning range, all static CMOS all digital PLL in 65nm SOI, IEEE
J. Solidstate circuits, Vol. 43, no. 1, pp. 42-51, January 2008.
[4] R. J. Yang and S. I. Liu, A 40-550 MHZ harmonicfree all digital delay
locked loop using a variable SAR algorithm, IEEE J. Solid-state circuits, Vol.
42, no. 2, pp. 361-373, February 2007.
[5] R. J. Yang and S. I. Liu, A 2.5 ghz all digital delay locked loop in 0.13 mm
CMOS technology, IEEE J. Solid-state Circuits, vol. 42, no.11, pp. 2338
2347, November 2007.
[6] A.G.M. Strollo, D.De Caro, E. Napoli, and N.Petra, A novel high speed
sense amplifier based flip-flop, IEEE Trans. Very Large Scale Integr. (VLSI)
Syst., vol. 13, no. 11, pp. 1266-1274, November 2005.
[7] C. C. Chung and C.Y. Lee, An all-digital phase locked loop for high speed
clock generation, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347-351,
February 2003.
[8] B. S. Kong, S. S. Kim, and Y. H. Jun, Conditionalcapture flip-flop for
statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8, pp.
1263- 1271, August 2001.
[9] B. Nikolic, V. G. Oklobdzija, V. Stajanovic, W. Jia, J. K. Chiu, and M.M.
Leung, Improved sense-amplifier based flip-flop: Design and measurements,
IEEE J. Solid-state Circuits, vol. 35, no. 6, pp. 876883, June
2000.
[10] J. Kim, Y. Jang, and H. Park, CMOS sense-amplifier
based flip-flop with two N-C2 MOS output latches,
Electron. Lett. vol. 36, no. 6, pp.468-500, March
2000
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