256MbSDRAMx32 PDF

256Mb: x32
SDRAM
SYNCHRONOUS
DRAM
MT48LC8M32B2 - 2 MEG x 32 x 4 BANKS

For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
Features
Figure 1: Pin Assignment (Top View)

86-Pin TSOP
PC100 functionality
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes Concurrent Auto
Precharge, and Auto Refresh Modes
Self Refresh Mode
64ms, 4,096-cycle refresh (15.6s/row)
LVTTL-compatible inputs and outputs
Single +3.3V 0.3V power supply
Supports CAS latency of 1, 2, and 3
Options
Marking
Configuration
8 Meg x 32 (2 Meg x 32 x 4 banks)
Package
86-pin TSOP (400 mil)
86-pin TSOP (400 mil) lead-free
90-ball FBGA (8mm x 13mm)
90-ball FBGA (8mm x 13mm) leadfree
Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
Operating Temperature Range
Commercial (0C to +70C)
Industrial (-40C to +85C)
NOTE:
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
A11
BA0
BA1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
8M32B2
TG
P
F5
B5
-6
-7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
NOTE:
None
The # symbol indicates signal is active LOW.
IT1
1. Available on -7 only.
8 Meg x 32
Table 1:
Key Timing Parameters
SPEED
CLOCK
GRADE FREQUENCY
-6
-7
166 MHz
143 MHz
ACCESS
TIME
CL = 3*
SETUP
TIME
HOLD
TIME
5.5ns
6.0ns
1.5ns
2ns
1ns
1ns
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
Part Number Example:
MT48LC8M32B2TG-7
*CL = CAS (READ) latency
09005aef8140ad6d
MT48LC8M32B2_1.fm - Rev. B 10/04 EN
2 Meg x 32 x 4 banks
4K
4K (A0A11)
4 (BA0, BA1)
512 (A0A8)
2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
SDRAM
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BURST READ/SINGLE WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ with AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
WRITE with AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
09005aef8140ad6d
MT48LC8M32B2TOC.fm - Rev. B 10/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x32
SDRAM
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

90-Ball FBGA Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagram 8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK - 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Single Read Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Read Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Read With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Read Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Read DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Write Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Write With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Write Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Write DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
86-Pin TSOP (400 MIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
90-Ball FBGA (8mm x 13mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
09005aef8140ad6d
MT48LC8M32B2LOF.fm - Rev. B 10/04 EN
256Mb: x32
SDRAM
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Pin Descriptions (TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Descriptions (FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Truth Table 1 Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Truth Table 2 CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Truth Table 3 Current State Bank n, Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Truth Table 4 Current State Bank n, Command To Bank m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .34
AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
09005aef8140ad6d
MT48LC8M32B2LOT.fm - Rev. B 10/04 EN
256Mb: x32
SDRAM
Figure 2: 90-Ball FBGA Assignment (Top View)
1
DQ26
DQ24
DQ28
VSS
VDD
DQ23
DQ21
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
NC
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Ball and Array
09005aef8140ad6d
256Mb: x32
SDRAM
256Mb (x32) SDRAM Part Number
PART NUMBER
ARCHITECTURE
PACKAGE
MT48LC8M32B2TG
MT48LC8M32B2P
MT48LC8M32B2F5
MT48LC8M32B2B5
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
86-pin TSOP
86-pin TSOP
90-ball FBGA
90-ball FBGA
The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a highspeed, fully random access. Precharging 1 bank while
accessing one of the other 3 banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All
inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and the
capability to randomly change column addresses on
each clock cycle during a burst access.
General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456-bits.
It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
67,108,864-bit banks is organized as 4,096 rows by 512
columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank, A0A11 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
09005aef8140ad6d
256Mb: x32
SDRAM
Figure 3: Functional Block Diagram 8 Meg x 32 SDRAM
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK 3
BANK 2
BANK 1
BANK 0
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK 0
ROWADDRESS
LATCH
&
DECODER
4,096
BANK 0
MEMORY
ARRAY
(4,096 x 256 x 32)
DQM0
DQM3
SENSE AMPLIFIERS
32
8,192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0A11,
BA0, BA1
14
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
32
32
256
(x32)
DQ0
DQ31
DATA
INPUT
REGISTER
COLUMN
DECODER
09005aef8140ad6d
COLUMNADDRESS
COUNTER/
LATCH
256Mb: x32
SDRAM
Table 2:
Pin Descriptions (TSOP)
86-PIN TSOP
SYMBOL
TYPE
DESCRIPTION
68
CLK
Input
67
CKE
Input
20
CS#
Input
17, 18, 19
WE#, CAS#,
RAS#
DQM0
DQM3
Input
22, 23
BA0, BA1
Input
25-27, 60-66, 24,

21
A0A11
Input
2, 4, 5, 7, 8, 10,
11, 13, 74, 76, 77,
79, 80, 82, 83, 85,
31, 33, 34, 36, 37,
39, 40, 42, 45, 47,
48, 50, 51, 53, 54,
56
3, 9, 35, 41, 49,
55, 75, 81
6, 12, 32, 38, 46,
52, 78, 84
1, 15, 29, 43
DQ0DQ31
I/O
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command
being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) during a READ cycle. DQM0 corresponds to DQ0DQ7; DQM1
corresponds to DQ8DQ15; DQM2 corresponds to DQ16DQ23 ; and DQM3
corresponds to DQ24DQ31. DQM0DQM3 are considered same state when
referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address Inputs: A0A11 are sampled during the ACTIVE command (row-address
A0A10) and READ/WRITE command (column-address A0A8 with A10 defining
auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine
if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1
(LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data Input/Output: Data bus.
16, 71, 28, 59
44, 58, 72, 86

14, 30, 57, 69, 70,
73
09005aef8140ad6d
Input
VDDQ
Supply DQ Power Supply: Isolated on the die for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
VSS
Supply Power Supply: +3.3V 0.3V.
NC
Supply Ground.
No Connect: These pins should be left unconnected. Pin 70 is reserved for SSTL
reference voltage supply.
256Mb: x32
SDRAM
Table 3:
Ball Descriptions (FBGA)
90-BALL FBGA
SYMBOL
TYPE
DESCRIPTION
J1
CLK
Input
J2
CKE
Input
J8
CS#
Input
J9, K7, K8
Input
K9, K1, F8, F2
RAS#, CAS#,
WE#
DQM0-3
J7, H8
BA0, BA1
Input
G8, G9, F7, F3, G1,

G2, G3, H1, H2, J3,
G7, H9
A0A11
Input
R8, N7, R9, N8, P9,

M8, M7, L8, L2,
M3, M2, P1, N2, R1,
N3, R2, E8, D7, D8,
B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1,
D2, D3, E2
B2, B7, C9, D9, E1,
L1, M9, N9, P2, P7
B8, B3, C1, D1, E9,
L9, M1, N1, P3, P8
A7, F9, L7, R7
A3, F1, L3, R3
E3, E7, H3, H7, K2,
K3
DQ0DQ31
I/O
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. DQM0 corresponds to
DQ0DQ7; DQM1 corresponds to DQ8DQ15; DQM2 corresponds to DQ16
DQ23; and DQM3 corresponds to DQ24DQ31. DQM0DQM3 are
considered same state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These balls also
provide the op-code during a LOAD MODE REGISTER command
Address Inputs: A0A11 are sampled during the ACTIVE command (rowaddress A0A11) and READ/WRITE command (column address A0A8; with
A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or
bank selected by BA0, BA1 (LOW). The address inputs also provide the opcode during a LOAD MODE REGISTER command.
Data Input/Output: Data bus.
09005aef8140ad6d
Input
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
VSS
NC
Supply Power Supply: Voltage dependant on option.

Supply Ground.
No Connect: These pins should be left unconnected. H3 is a No Connect for

this part but may be used as A12 in future designs.
256Mb: x32
SDRAM
Functional Description
Register Definition
In general, this 256Mb SDRAM (2 Meg x 32 x 4 banks) is

a quad-bank DRAM that operates at 3.3V and includes
a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the
67,108,864-bit banks is organized as 4,096 rows by 512
columns by 32-bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0A11 select the row).
The address bits (A0A8) registered coincident with
the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Mode Register
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode, and a write burst mode, as
shown in Figure 1. The mode register is programmed
via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed
again or the device loses power.
Mode register bits M0M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved),
M4M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode,
and M10, M11, BA0, and BA1 are reserved for future
use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Burst Length
Initialization
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, or 8 locations are available for both
the sequential and the interleaved burst types, and a
full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1A8 when the burst length is set to two;
by A2A8 when the burst length is set to four; and by
A3A8 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Fullpage bursts wrap within the page if the boundary is
reached.
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100s delay
prior to issuing any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100s period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
Once the 100s delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register programming. Because the mode register will power up in
an unknown state, it should be loaded prior to applying any operational command.
09005aef8140ad6d
10
256Mb: x32
SDRAM
Burst Type
Table 4:
Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting column address, as shown in Table 4.
ORDER OF ACCESSES WITHIN

A BURST
BURST
LENGTH
2
Figure 4: Mode Register Definition

BA1 BA0
13
12
A11
11
Reserved*
A10 A9
10
A8
A6
A7
A5
A4
A3
WB Op Mode CAS Latency
BT
A1
A2
Address Bus
A0
Mode Register (Mx)
Burst length
*Should be
programmed
to 0 to ensure
compatibility with
future devices.
8
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Reserved
Reserved
1 0 1
Reserved
Reserved
1 1 0
Reserved
Reserved
1 1 1
Full Page
Reserved
Full
Page
(512)
Burst Type
M3
0
Sequential
Interleave
CAS Latency
M6 M5 M4
0
0 1 0
0 1 1
1 0 0
Reserved
1 0 1
Reserved
1 1 0
Reserved
1 1 1
Reserved
M8
M7
M6 - M0
Operating Mode
Defined
Standard operation
Write Burst Mode
Programmed Burst Length
Single Location Access
STARTING
COLUMN
ADDRESS
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
n = A0A8
(Location
0511)
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1,
Cn + 2, Cn + 3,
Cn + 4...
...Cn-1,
Cn...
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
Reserved
0 0 1
M9
Burst Definition
All other states reserved
NOTE:
1. For BL = 2, A1A8 select the block-of-two burst; A0 selects the starting column within the block.
2. For BL = 4, A2A8 select the block-of-four burst; A0A1 select the starting column within the block.
3. For BL = 8, A3A8 select the block-of-eight burst; A0A2 select the starting column within the block.
4. For a full-page burst, the full row is selected and A0A8 select the starting column.
5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the
block.
6. For BL = 1, A0A8 select the unique column to be accessed, and mode register bit M3 is ignored.
09005aef8140ad6d
11
256Mb: x32
SDRAM
CAS Latency
Figure 5: CAS Latency
The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability of the first piece of output data. The latency can be
set to one, two, or three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result
of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant
access times are met, if a READ command is registered
at T0 and the latency is programmed to two clocks, the
DQs will start driving after T1 and the data will be valid
by T2, as shown in Figure 4. Table 5 indicates the operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
T0
T1
T2
READ
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 1
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
Operating Mode
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
The normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DONT CARE
UNDEFINED
Write Burst Mode

When M9 = 0, the burst length programmed via M0
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst) accesses.
09005aef8140ad6d
Table 5:
CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHZ)
12
SPEED
CL = 1
CL = 2
CL = 3
-6
-7
50
50
100
100
166
143
256Mb: x32
SDRAM
Commands
Table 6 provides a quick reference of available commands. This is followed by a written description of
each command. Three additional Truth Tables (Tables
Table 6:
7, 8, and 9) appear following Operations on page 15;

these tables provide current state/next state information.
Truth Table 1 Commands and DQM Operation
Note 1
NAME (FUNCTION)
CS#
RAS#
CAS# WE# DQM
COMMAND INHIBIT (NOP)

NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
H
L
L
L
X
H
L
H
X
H
H
L
X
H
H
H
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
L
L
L
H
L
L
H
H
L
X
X
X
8
L/H
ADDR
DQS
NOTES
X
X
Bank/Row
Bank/Col
X
X
X
X
3
4
Bank/Col
Valid
L
L
H
L/H8
X
X
X
X
Code
X
Active
X
X
5
6, 7
X
L
H
Op-Code
X
Active
High-Z
2
8
8
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0A11 define the op-code written to the mode register.
3. A0A11 provide row address, BA0 and BA1 determine which bank is made active.
4. A0A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0 and BA1 are
Dont Care.
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are Dont Care except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0
DQ7; DQM1 controls DQ8DQ15; DQM2 controls DQ16DQ23; and DQM3 controls DQ24DQ31.
COMMAND INHIBIT
LOAD MODE REGISTER
The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless
of whether the CLK signal is enabled. The SDRAM is
effectively deselected. Operations already in progress
are not affected.
The mode register is loaded via inputs A0A11. See

mode register in Register Definition on page 10. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
NO OPERATION (NOP)
ACTIVE
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations
already in progress are not affected.
The ACTIVE command is used to open (or activate) a

row in a particular bank for a subsequent access. The
value on the BA0 and BA1 inputs selects the bank, and
the address provided on inputs A0A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a
different row in the same bank.
09005aef8140ad6d
13
256Mb: x32
SDRAM
READ
AUTO PRECHARGE
The READ command is used to initiate a burst read

access to an active row. The value on the BA0 and BA1
(B1) inputs selects the bank, and the address provided
on inputs A0A8 selects the starting column location.
The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of
the READ burst; if auto precharge is not selected, the
row will remain open for subsequent accesses. Read
data appears on the DQs subject to the logic level on
the DQM inputs two clocks earlier. If a given DQMx
signal was registered HIGH, the corresponding DQs
will be High-Z two clocks later; if the DQMx signal was
registered LOW, the corresponding DQs will provide
valid data. DQM0 corresponds to DQ0DQ7, DQM1
corresponds to DQ8DQ15, DQM2 corresponds to
DQ16DQ23, and DQM3 corresponds to DQ24DQ31.
Auto precharge is a feature which performs the same

individual bank PRECHARGE function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable auto precharge
in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is
addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode,
where auto precharge does not apply. Auto precharge
is nonpersistent in that it is either enabled or disabled
for each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (tRP) is completed. This is determined
as if an explicit PRECHARGE command was issued at
the earliest possible time, as described for each burst
type in Operations on page 15.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0 and BA1
inputs selects the bank, and the address provided on
inputs A0A8 selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in Operations on page 15.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time
a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits Dont Care
during an AUTO REFRESH command. The 256Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 15.625s
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (tRFC), once every 64ms.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0
and BA1 select the bank. Otherwise BA0 and BA1 are
treated as Dont Care. Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
09005aef8140ad6d
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
14
256Mb: x32
SDRAM
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become Dont Care with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform
its own AUTO REFRESH cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to tRAS and may remain in self refresh mode for
an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for tXSR because time is required for the completion of any internal refresh in progress.
Upon exiting self refresh mode, AUTO REFRESH commands must be issued every 15.625s or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
A subsequent ACTIVE command to another bank can

be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by tRRD.
Figure 6: Activating a Specific Row in a

Specific Bank
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Operations
ROW
ADDRESS
A0-A11
Bank/Row Activation
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must
be opened. This is accomplished via the ACTIVE
command, which selects both the bank and the row to
be activated. See Figure 6.
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be issued. For example, a tRCD
specification of 20ns with a 143 MHz clock (7ns
period) results in 2.5 clocks, rounded to three. This is
reflected in Figure 7, which covers any case where 2 <
t
RCD (MIN)/tCK - 3. (The same procedure is used to
convert other specification limits from time units to
clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after
the previous active row has been closed (precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by tRC.
09005aef8140ad6d
BANK
ADDRESS
BA0, BA1
DONT CARE
Figure 7: Example: Meeting tRCD (MIN)

When 2 < tRCD (MIN)/tCK - 3
T0
T1
T2
T3
CLK
tCK
tCK
COMMAND
ACTIVE
NOP
tCK
NOP
READ or
WRITE
tRCD (MIN)
tRCD (MIN) +0.5 tCK
DONT CARE
NOTE:
tRCD
(MIN) = 20ns, tCK = 7ns

tRCD (MIN) x tCK where x = number of clocks for equation to be true.
15
256Mb: x32
SDRAM
Figure 8: READ Command
READs
READ bursts are initiated with a READ command, as
shown in Figure 8.
The starting column and bank addresses are provided
with the READ command, and auto precharge is either
enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic
READ commands used in the following illustrations,
auto precharge is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 9 shows general timing for each
possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixedlength READ burst may be immediately followed by
data from a READ command.
In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being
truncated. The new READ command should be issued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minus one. This is shown in Figure 10 for CAS latencies
of one, two and three; data element n + 3 is either the
last of a burst of four or the last desired of a longer
burst. SDRAMs use a pipelined architecture and therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ
command. Full-speed random read accesses can be
performed to the same bank, as shown in Figure 11, or
each subsequent READ may be performed to a different bank.
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A7
A8, A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,1
DONT CARE
Figure 9: CAS Latency

T0
T1
T2
READ
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 1
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DONT CARE
UNDEFINED
09005aef8140ad6d
16
256Mb: x32
SDRAM
Figure 10: Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
READ
X = 0 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CL = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
DONT CARE
NOTE:
Each READ command may be to either bank. DQM is LOW.
09005aef8140ad6d
17
256Mb: x32
SDRAM
Figure 11: Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CL = 3
DONT CARE
NOTE:
Each READ command may be to either bank. DQM is LOW.
vided that I/O contention can be avoided. In a given

system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a singlecycle delay should occur between the last read data
and the WRITE command.
Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by
data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, pro-
09005aef8140ad6d
18
256Mb: x32
SDRAM
Figure 12: READ-to-WRITE
T0
T1
T2
T3
Figure 13: READ-to-WRITE with Extra

Clock Cycle
T4
T0
CLK
T1
T2
T3
T4
T5
CLK
DQM
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
COMMAND
READ
ADDRESS
BANK,
COL n
tCK
DQ
DOUT n
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
tHZ
DQ
NOP
DOUT n
DIN b
tDS
DIN b
tDS
DONT CARE
DONT CARE
NOTE:
CL = 3 is used for illustration. The READ command may
be to any bank, and the WRITE command may be to any
bank. If a burst of one is used, then DQM is not
required.
NOTE:
CL = 3 is used for illustration. The READ command may
be to any bank, and the WRITE command may be to any
bank.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank
(provided that auto precharge was not activated), and
a full-page burst may be truncated with a PRECHARGE
command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge
at which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 14 on page 20 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or
the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that
part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
The DQM input is used to avoid I/O contention, as

shown in Figures 12 and 13. DQM must be asserted
(HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQMs.
The DQs remain High-Z, provided DQM was active on
the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE
will be an invalid WRITE. For example, if DQM was
LOW during T4 (in Figure 13), then the WRITEs at T5
and T7 would be valid, while the WRITE at T6 would be
invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for
input buffers) to ensure that the written data is not
masked. Figure 12 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 shows the case
where the additional NOP is needed.
09005aef8140ad6d
19
256Mb: x32
SDRAM
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 15 on page 21 for each possible CAS latency;
data element n + 3 is the last desired data element of a
longer burst.
Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at
Figure 14: READ-to-PRECHARGE

T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 0 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CL = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CL = 3
DONT CARE
NOTE:
DQM is LOW.
09005aef8140ad6d
20
256Mb: x32
SDRAM
Figure 15: Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CL = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 1 cycle
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
DONT CARE
NOTE:
DQM is LOW.
WRITEs
WRITE bursts are initiated with a WRITE command, as
shown in Figure 16 on page 22.
The starting column and bank addresses are provided
with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations,
auto precharge is disabled.
09005aef8140ad6d
During WRITE bursts, the first valid data-in element

will be registered coincident with the WRITE command. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure 17
on page 22). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0
and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data
21
256Mb: x32
SDRAM
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write
accesses within a page can be performed to the same
bank, as shown in Figure 19 on page 23, or each subsequent WRITE may be performed to a different bank.
for a fixed-length WRITE burst may be immediately

followed by data for a WRITE command. The new
WRITE command can be issued on any clock following
the previous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 18. Data n +
1 is either the last of a burst of two or the last desired of
a longer burst. This 256Mb SDRAM uses a pipelined
Figure 16: WRITE Command

CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0A8
A9, A11
A10
BANK
ADDRESS
BA0, BA1
VALID ADDRESS
Figure 18: WRITE to WRITE
Figure 17: WRITE Burst

T0
T1
T2
T3
CLK
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
COMMAND
WRITE
ADDRESS
BANK,
COL n
DQ
DONT CARE
DIN
n
NOP
NOP
NOP
DIN
n+1
DQ
DIN
n+1
DIN
b
DONT CARE
DONT CARE
NOTE:
DQM is LOW. Each WRITE command may be to any
bank.
NOTE:
BL = 2. DQM is LOW.
09005aef8140ad6d
DIN
n
BANK,
COL b
22
256Mb: x32
SDRAM
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a
READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 20.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued tWR after the
clock edge at which the last desired input data element
is registered. The two-clock write-back requires at least
one clock plus time, regardless of frequency, in auto
precharge mode.
In addition, when truncating a WRITE burst, the DQM
signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in
Figure 21 on page 24. Data n + 1 is either the last of a
burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP
is met. The precharge will actually begin coincident
with the clock-edge (T2 in Figure 21) on a one-clock
t
WR and sometime between the first and second clock
on a two-clock tWR (between T2 and T3 in Figure 21.)
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be
09005aef8140ad6d
Figure 19: Random WRITE Cycles

T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
DQ
DONT CARE
NOTE:
Each WRITE command may be to any bank. DQM is
LOW.
Figure 20: WRITE to READ

T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT
b
DOUT
b+1
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DONT CARE
NOTE:
The WRITE command may be to any bank, and the
READ command may be to any bank. DQM is LOW.
CL = 2 for illustration.
23
256Mb: x32
SDRAM
Figure 21: WRITE to PRECHARGE
T0
T1
T2
T3
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
PRECHARGE
The PRECHARGE command (Figure 23) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP)
after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only one bank is to be
precharged, inputs BA0 and BA1 select the bank. When
all banks are to be precharged, inputs BA0 and BA1 are
treated as Dont Care. Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
CLK
tWR = 1 CLK (tCK > tWR)
DQM
t RP
COMMAND
ADDRESS
WRITE
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR = 2 CLK (when tWR > tCK)
DQM
Figure 23: PRECHARGE Command

t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
BANK a,
COL n
CLK
ACTIVE
CKE
BANK a,
ROW
t WR
DQ
DIN
n
HIGH
CS#
DIN
n+1
RAS#
CAS#
DONT CARE
NOTE:
DQM could remain LOW in this example if the WRITE
burst is a fixed length of two.
WE#
A0-A9, A11
Figure 22: Terminating a WRITE Burst

T0
T1
All Banks
T2
A10
Bank Selected
CLK
BURST
TERMINATE
WRITE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DQ
BA0, BA1
NEXT
COMMAND
COMMAND
VALID ADDRESS
DONT CARE
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no
accesses are in progress (see Figure 24). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in either bank, this mode is
referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby.
The device may not remain in the power-down state
longer than the refresh period (64ms) since no
REFRESH operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS).
DONT CARE
NOTE:
DQM is LOW.
09005aef8140ad6d
BANK
ADDRESS
24
256Mb: x32
SDRAM
Figure 24: Power-Down
((
))
((
))
CLK
tCKS
Figure 26: CLOCK SUSPEND During

READ Burst
T0
> tCKS
T1
T2
T3
T4
T5
T6
CLK
CKE
((
))
COMMAND
((
))
((
))
NOP
NOP
tRCD
tRAS
All banks idle

Input buffers gated off
Enter power-down mode
CKE
ACTIVE
INTERNAL
CLOCK
tRC
Exit power-down mode
DONT CARE
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered LOW.
In the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored. Any data present on the DQ pins remains
driven. Also, burst counters are not incremented, as
long as the clock is suspended. (See examples in Figures 25 and 26.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DOUT
n+2
NOP
DOUT
n+3
READ with AUTO PRECHARGE

1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on
bank n, CAS latency later. The PRECHARGE to bank n
will begin when the READ to bank m is registered
(Figure 27).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on
bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 28).
DIN
n+2
DONT CARE
NOTE:
For this example, BL = 4 or greater, and DM is LOW.
09005aef8140ad6d
DOUT
n+1
NOP
CONCURRENT AUTO PRECHARGE

An access command to (READ or WRITE) another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
BANK,
COL n
DIN
n
DOUT
n
NOP
BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands result in the access of a single column location
(burst of one), regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
INTERNAL
CLOCK
DIN
BANK,
COL n
NOP
NOTE:
For this example, CL = 2, BL = 4 or greater, and DQM is
LOW.
CKE
ADDRESS
ADDRESS
NOP
DONT CARE
CLK
COMMAND
READ
DQ
Figure 25: CLOCK SUSPEND During

WRITE Burst
T0
COMMAND
25
256Mb: x32
SDRAM
Figure 27: READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
BANK n
READ - AP
BANK n
Page Active
NOP
READ - AP
BANK m
READ with Burst of 4
NOP
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
Internal
States
tRP - BANK m
t RP - BANK n
Page Active
BANK m
BANK m,
COL d
BANK n,
COL a
ADDRESS
Precharge
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CL = 3 (BANK n)
CL = 3 (BANK m)
DONT CARE
NOTE:
DQM is LOW.
Figure 28: READ With Auto Precharge Interrupted by a WRITE

T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Internal
States
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CL = 3 (BANK n )
DONT CARE
NOTE:
DQM is HIGH at T2 to prevent DOUT - a + 1 from contending with DIN - d at T4.
WRITE with AUTO PRECHARGE

3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on
bank n when registered, with the data-out appearing
CAS latency later. The PRECHARGE to bank n will
begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 29).
09005aef8140ad6d
4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on
bank n when registered. The PRECHARGE to bank n
will begin after tWR is met, where tWR begins when the
WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank m (Figure 30).
26
256Mb: x32
SDRAM
Figure 29: WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
Internal
States
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
BANK m,
COL d
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
DOUT
d+1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
DONT CARE
NOTE:
DQM is LOW.
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE

T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back

tWR - BANK n
Internal
States
BANK m
ADDRESS
DQ
Page Active
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DONT CARE
NOTE:
DQM is LOW.
09005aef8140ad6d
27
256Mb: x32
SDRAM
Table 7:
Truth Table 2 CKE
Notes 14
CKEn-1
CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
X
X
X
COMMAND INHIBIT or NOP
X
AUTO REFRESH
VALID
See Truth Table 3
5
6
7
Power-Down
Self Refresh
Clock Suspend
Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
NOTE:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or
NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
09005aef8140ad6d
28
256Mb: x32
SDRAM
Table 8:
Truth Table 3 Current State Bank n, Command To Bank n
Notes 111; notes appear below and on next page

CURRENT STATE
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS# WE#

X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
NOTES
7
7
11
10
10
8
10
10
8
9
10
10
8
9
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7) and after tXSR has been met (if the previous
state was self refresh).
2. This table is bank-specific, except where noted: i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Table 7, and according to Table 9.
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once
tRCD is met, the bank will be in the row active state.
Read with auto
precharge
enabled:
Starts with registration of a READ command with auto precharge enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write with auto
precharge
enabled:
Starts with registration of a WRITE command with auto precharge enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
09005aef8140ad6d
29
256Mb: x32
SDRAM
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
Refreshing:
Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the SDRAM will be in the all banks idle state.
Accessing mode
register:
Starts with registration of a LOAD MODE REGISTER command and ends when tMRD
has been met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed under Command (Action) include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
09005aef8140ad6d
30
256Mb: x32
SDRAM
Table 9:
Truth Table 4 Current State Bank n, Command To Bank m
Notes 117; notes appear below and on next page

CURRENT STATE
Any
Idle
Row Activating,
Active, or Precharging
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
Read
(With Auto Precharge)
Write
(With Auto Precharge)
CS#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS#
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
WE#
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
PRECHARGE
PRECHARGE
PRECHARGE
PRECHARGE
PRECHARGE
NOTES
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7, 8, 15
9
7, 8, 16
7, 8, 17
9
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7) and after tXSR has been met (if the previous
state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no regster accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet ter
minated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
Read with
auto precharge
enabled:
Starts with registration of a READ command with auto precharge enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
09005aef8140ad6d
31
256Mb: x32
SDRAM
7. READs or WRITEs to bank m listed under Command (Action) include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
by bank ms burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 9).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figures 12 and 13). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 20), with the data-out appearing CAS latency later. The last valid
WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 18). The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 28).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 29).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to
the WRITE to bank m (Figure 30).
09005aef8140ad6d
32
256Mb: x32
SDRAM
Absolute Maximum Ratings
Voltage on VDD, VDDQ Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V
Operating Temperature, TA . . . . . . . . . . . . . 0C to +70C
Storage Temperature (plastic) . . . . . . . . -55C to +150C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Operating Temperature, TA (IT) . . . . . . . . -40C to +85C
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Table 10: DC Electrical Characteristics and Operating Conditions

Notes 1, 6; notes appear on page 37
VDD, VDDQ = +3.3V 0.3V
PARAMETER/CONDITION
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
Any input 0V VIN VDD
(All other pins not under test = 0V)
Output Leakage Current: DQs are disabled; 0V VOUT VDDQ
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
SYMBOL
MIN
MAX
UNITS NOTES
VDD, VDDQ
VIH
VIL
II
3
2
-0.3
-5
3.6
VDDQ + 0.3
0.8
5
V
V
V
A
IOZ
VOH
VOL
-5
2.4
0.4
A
V
V
22
22
Table 11: Capacitance

Note 2
PARAMETER
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
09005aef8140ad6d
33
SYMBOL
MIN
MAX
UNITS
C I1
C I2
CIO
2.5
4.0
pF
2.5
4.5
pF
4.0
6.5
pF
256Mb: x32
SDRAM
Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes appear on page 37
-6
PARAMETER
Access time from CLK
(positive edge)
SYMBOL
MAX
UNITS
5.5
ns
(2)
7.5
ns
AC (1)
17
17
ns
CL = 3
CL = 2
tAC
CL = 1
AC (3)
Address hold time
MIN
-7
AH
MAX
MIN
ns
NOTES
Address setup time
AS
1.5
ns
CLK high-level width
tCH
2.5
2.75
ns
CLK low-level width
tCL
2.5
2.75
ns
ns
23
Clock cycle time
CL = 3
tCK
(3)
CL = 2
tCK
(2)
10
10
ns
23
CL = 1
tCK
(1)
20
20
ns
23
tCKH
ns
CKE hold time
tCKS
1.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
ns
Data-in hold time
tDH
ns
Data-in setup time
tDS
1.5
ns
CKE setup time
CL=3
tHZ
(3)
5.5
ns
10
CL = 2
tHZ
(2)
7.5
ns
10
CL = 1
tHZ
(1)
17
17
ns
10
Data-out High-Z time
Data-out Low-Z time
tLZ
ns
Data-out hold time
tOH
2.5
ns
ACTIVE to PRECHARGE command
tRAS
42
tRC
60
70
ns
RFC
60
70
ns
RCD
18
20
ns
ACTIVE to ACTIVE command period

AUTO REFRESH period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
Transition time
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
09005aef8140ad6d
42
64
REF
120K
64
ns
ms
RP
18
20
ns
RRD
12
14
ns
25
tT
0.3
ns
tWR
1 CLK+
1 CLK+
tCK
24
tXSR
6ns
12ns
70
7ns
14ns
70
ns
ns
27
20
PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command
120K
34
1.2
0.3
1.2
256Mb: x32
SDRAM
Table 13: AC Functional Characteristics
Notes appear on page 37
PARAMETER
SYMBOL
-6
-7
CCD
CK
17
tCKED
tCK
14
PED
CK
14
DQM to input data delay
DQD
CK
17
DQM to data mask during WRITEs
DQM
CK
17
DQM to data High-Z during READs
DQZ
CK
17
WRITE command to input data delay
tDWD
tCK
17
READ/WRITE command to READ/WRITE command

CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
Data-into ACTIVE command
UNITS
NOTES
CL = 3
tDAL
(3)
tCK
15, 21
CL = 2
tDAL
(2)
tCK
15, 21
CL = 1
tDAL
(1)
tCK
15, 21
Data-into PRECHARGE command
tDPL
tCK
16, 21
Last data-in to burst STOP command
tBDL
tCK
17
Last data-in to new READ/WRITE command
tCDL
tCK
17
Last data-in to PRECHARGE command
tRDL
tCK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command
tMRD
tCK
26
Data-out to High-Z from PRECHARGE command
09005aef8140ad6d
CL = 3
tROH
(3)
tCK
17
CL = 2
tROH
(2)
tCK
17
CL = 1
tROH
(1)
tCK
17
35
256Mb: x32
SDRAM
Table 14: IDD Specifications and Conditions
Notes appear on page 37 (VDD, VDDQ = +3.3V 0.3V)
MAX
PARAMETER/CONDITION
Operating Current: Active Mode; Burst = 2; READ or WRITE;
RC = tRC (MIN), CL = 3
Standby Current: Power-Down Mode; All banks idle; CKE = LOW
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Operating Current: Burst Mode; Continuous burst; READ or WRITE;
All banks active, half DQs toggling every cycle, CL = 3
tRFC = tRFC
Auto Refresh Current
CKE = HIGH; CS# = HIGH
(MIN)
SELF REFRESH current: CKE < 0.2V
SYMBOL
-6
-7
UNITS
NOTES
IDD1
210
190
mA
3, 18, 19, 26
IDD2
IDD3
1.2
40
1.2
40
mA
mA
3, 12, 19, 26
IDD4
165
145
mA
3, 18, 19, 26
IDD5
335
295
mA
3, 12, 18, 19,

26
IDD6
mA
09005aef8140ad6d
36
256Mb: x32
SDRAM
Notes
12. Other input signals are allowed to transition no
more than once in any two-clock period and are
otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
18. The IDD current will decrease as CL is reduced.
This is due to the fact that the maximum cycle rate
is slower as CL is reduced.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 143 MHz for -7; 166 MHz for -6.
22. VIH overshoot: VIH (MAX) = VDDQ + 1.2V for a
pulse width 3ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -1.2V for a pulse width 3ns,
and the pulse width cannot be greater than one
third of the cycle rate.
23. The clock frequency must remain constant during
access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. tCK = 7ns for -7; 6ns for -6.
27. Check factory for availability of specially screened
devices having tWR = 10ns. tWR = 1 tCK for 100
MHz and slower (tCK = 10ns and higher) in manual precharge.
1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f =
1 MHz, TA = 25C; pin under test biased at 1.4V. AC
can range from 0pF to 6pF.
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range (0C TA +70C
and -40C TA +85C for IT parts) is ensured.
6. An initial pause of 100s is required after powerup, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously.
VSS and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a monotonic manner.
Q
30pF
9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL =.25 and VIH =
2.75, with timing referenced to 1.5V crossover
point.
09005aef8140ad6d
37
256Mb: x32
SDRAM
Figure 31: Initialize and Load Mode Register
T0
CLK
((
))
tCKS
tCK
T1
Tn + 1
((
))
((
))
tCKH
tCH
((
))
((
))
To + 1
tCL
((
))
((
))
((
))
((
))
((
))
((
))
((
))
COMMAND
((
))
((
))
DQM 03
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
DQ
NOP
SINGLE BANK
ALL
BANKS
High-Z
Power-up:
VDD and
CK stable
Tp + 3
tCMS tCMH
((
))
PRECHARGE
((
))
ALL BANKS
((
))
((
))
((
))
T = 100s
(MIN)
tCMS tCMH
Tp + 2
((
))
CKE
tCMS tCMH
Tp + 1
AUTO
REFRESH
((
))
NOP
NOP
((
))
AUTO
REFRESH
((
))
NOP
NOP
((
))
LOAD MODE
REGISTER
tAS
NOP
tAH
ROW
CODE
tAS
ACTIVE
tAH
ROW
CODE
BANK
((
))
tRP
Precharge
all banks
tRFC
tRFC
AUTO REFRESH
AUTO REFRESH
tMRD
Program Mode Register 1, 2

DONT CARE
UNDEFINED
NOTE:
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. Outputs are guaranteed High-Z after command is issued.
09005aef8140ad6d
38
256Mb: x32
SDRAM
Figure 32: Power-Down Mode
T0
T1
tCK
CLK
T2
((
))
((
))
tCL
tCKS
tCH
CKE
tCKS
PRECHARGE
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQM 03
((
))
((
))
A0A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in

power-down mode
Precharge all
active banks
All banks idle, enter

power-down mode
All banks idle

Exit power-down mode
DONT CARE
UNDEFINED
NOTE:
Violating refresh requirements during power-down may result in a loss of data.
09005aef8140ad6d
39
256Mb: x32
SDRAM
Figure 33: Clock Suspend Mode
T0
T1
tCK
CLK
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tCMS tCMH
DQM03
tAS
A0A9, A11
tAH
COLUMN m 2
tAS
tAH
tAS
tAH
COLUMN e
A10
BA0, BA1
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. A9 and A11 = Dont Care.
09005aef8140ad6d
40
256Mb: x32
SDRAM
Figure 34: Auto Refresh Mode
T0
CLK
T1
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
((
))
( ( NOP
))
((
))
( ( NOP
))
ACTIVE
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
BANK
((
))
((
))
ALL BANKS
SINGLE BANK
tAH
BANK(S)
High-Z
tRP
tRFC
tRFC
Precharge all
active banks
09005aef8140ad6d
NOP
((
))
((
))
A10
DQ
AUTO
REFRESH
((
))
((
))
A0A9, A11
tAS
To + 1
((
))
((
))
((
))
DQM 03
BA0, BA1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
DONT CARE
41
UNDEFINED
256Mb: x32
SDRAM
Figure 35: Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
COMMAND
tCKS
tCKH
tCMS
tCMH
PRECHARGE
Tn + 1
((
))
((
))
((
))
((
))
((
))
NOP
((
))
((
))
AUTO
REFRESH
((
))
((
))
((
))
((
))
((
))
A0A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
SINGLE BANK
tAS
BA0, BA1
DQ
tAH
BANK(S)
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode

(Restart refresh time base)
CLK stable prior to exiting

self refresh mode
09005aef8140ad6d
AUTO
REFRESH
))
((
))
((
))
ALL BANKS
To + 2
tCKS
NOP ( (
DQM 03
A10
To + 1
42
DONT CARE
UNDEFINED
256Mb: x32
SDRAM
Figure 36: Single Read Without Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
PRECHARGE
tCMH
DQM /
DQML, DQMH
tAS
A0A9, A11
COLUMN m2
ROW
tAS
tAH
ROW
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
tAH
BANK
SINGLE BANK
BANK
BANK
BANK
tAC
DQ
tLZ
tRCD
tOH
DOUT m
tHZ
CAS Latency
tRP
tRAS
tRC
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE.
09005aef8140ad6d
43
256Mb: x32
SDRAM
Figure 37: Read Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
tCMH
DQM 0-3
tAS
COLUMN m 2
ROW
A0A9, A11
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
SINGLE BANK
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
BANK
tAC
tOH
tOH
tOH
DOUT m + 1
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
09005aef8140ad6d
44
256Mb: x32
SDRAM
Figure 38: Read With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM 03
tAS
A0A9, A11
tAH
ROW
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tAC
tOH
tOH
tOH
DOUT m + 1
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 4 and CL = 2.
09005aef8140ad6d
45
256Mb: x32
SDRAM
Figure 39: Alternating Bank Read Accesses
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM 03
tAS
A0A9, A11
tAH
COLUMN b 2
ROW
ROW
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 4
BANK 4
tAC
tOH
tAC
DQ
DOUT m
tLZ
tRCD - BANK 0
tAC
BANK 0
tAC
tAC
tOH
tOH
tOH
DOUT m + 1
DOUT m + 2
DOUT m + 3
tRP - BANK 0
CAS Latency - BANK 0
tAC
tOH
DOUT b
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 4
tRRD
CAS Latency - BANK 4
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 4 and CL = 2.
09005aef8140ad6d
46
256Mb: x32
SDRAM
Figure 40: Read Full-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM 03
A10
Tn + 3
((
))
((
))
tCMS
A0A9, A11
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
Dout m
DQ
DOUT m+1
tLZ
tRCD
CAS Latency
tAC
tOH
tAC ( (
))
tOH
((
))
DOUT m+2
((
))
tAC
tOH
DOUT m-1
tAC
tOH
DOUT m
tOH
DOUT m+1
tHZ
256 locations within same row
Full page completed

Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
DONT CARE
UNDEFINED
NOTE:
1. For this example, CL = 2.
3. Page left open; no tRP.
09005aef8140ad6d
47
256Mb: x32
SDRAM
Figure 41: Read DQM Operation
T0
T1
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM 03
tAS
A0A9, A11
tAH
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
BANK
BANK
tAC
DQ
tOH
DOUT m
tLZ
tRCD
tAC
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS Latency
DONT CARE
UNDEFINED
NOTE:
1. For this example, CL = 2.
09005aef8140ad6d
48
256Mb: x32
SDRAM
Figure 42: Single Write
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
NOP
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0A9, A11
tAS
A10
COLUMN m 3
ROW
tAH
ALL BANKS
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
SINGLE BANK
BANK
tDS
BANK
BANK
tDH
DIN m
DQ
tRCD
tRAS
t WR 2
tRP
tRC
DONT CARE
NOTE:
1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. tWR is required between <DIN m> and the PRECHARGE command, regardless of frequency.
09005aef8140ad6d
49
256Mb: x32
SDRAM
Figure 43: Write Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
tCMS tCMH
DQM 03
tAS
A0A9, A11
ROW
tAH
ALL BANKs
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
SINGLE BANK
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
BANK
tRP
tRC
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 4, and the WRITE burst is followed by a manual PRECHARGE.
2. Faster frequencies require two clocks (when tWR > tCK).
4. tWR of one CLK available if running 100 MHz or slower. Check factory for availability.
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SDRAM
Figure 44: Write With Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 03
tAS
A0A9, A11
tAS
A10
COLUMN m 3
tAH
ROW
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
tDS
tDH
DIN m
DQ
BANK
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tWR 2
tRCD
tRAS
tRP
tRC
DONT CARE
UNDEFINED
NOTE:
1. For this example, BL = 4.
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256Mb: x32
SDRAM
Figure 45: Alternating Bank Write Accesses
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM 03
tAS
A0A9, A11
tAH
COLUMN b 3
ROW
ROW
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR2 - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
DIN b + 1
tRP - BANK 0
tDS
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
tRCD - BANK 4
tWR - BANK 4
DONT CARE
NOTE:
09005aef8140ad6d
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256Mb: x32
SDRAM
Figure 46: Write Full-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
A0A9, A11
tAS
A10
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m 1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
Tn + 3
((
))
((
))
DQM 03
tAS
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tRCD
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
((
))
((
))
tDS
tDH
DIN m - 1
256 locations within same row
Full-page burst does

not self-terminate. Can
use BURST TERMINATE
command to stop.2, 3
Full page completed

DONT CARE
NOTE:
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
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SDRAM
Figure 47: Write DQM Operation
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 03
tAS
A0A9, A11
tAH
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DONT CARE
NOTE:
09005aef8140ad6d
54
256Mb: x32
SDRAM
Figure 48: 86-Pin TSOP (400 MIL)
22.22 0.08
0.61
0.50
TYP
SEE DETAIL A
2X 0.10
+0.07
0.20 -0.03
2X 2.80
11.76 0.20
10.16 0.08
2X R 0.75
PIN #1 ID
+0.03
0.15 -0.02
2X R 1.00
0.25
GAGE
PLANE
0.10
1.20 MAX
+0.10
0.10 -0.05
PLATED LEAD FINISH: 90% Sn, 10% Pb (TG) OR 100% Sn (P)

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC
PACKAGE WIDTH AND LENGTH DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25mm PER SIDE.
0.50 0.10
0.80
TYP
DETAIL A
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
09005aef8140ad6d
55
256Mb: x32
SDRAM
Figure 49: 90-Ball FBGA (8mm x 13mm)
0.65 0.05
SEATING PLANE
0.10 C
C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag (F5) OR
96.5% Sn, 3%Ag, 0.5% Cu (B5)
SOLDER MASK DEFINED BALL PADS: 0.40
90X 0.45 0.05

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS 0.42
SUBSTRATE MATERIAL: PLASTIC LAMINATE

MOLD COMPOUND: EPOXY NOVOLAC
6.40
0.80 TYP
BALL A1 ID
BALL A1 ID
BALL A1
BALL A9
0.80 TYP
11.20 0.10
CL
13.00 0.10
5.60 0.05
6.50 0.05
CL
3.20 0.05
1.00 MAX
4.00 0.05
8.00 0.10
NOTE:
1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.4mm 0.03mm.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
09005aef8140ad6d
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256Mb: x32

MT48LC8M32B2 - 2 MEG x 32 x 4 BANKS

Figure 1: Pin Assignment (Top View)

The # symbol indicates signal is active LOW.

Key Timing Parameters

Part Number Example:

*CL = CAS (READ) latency

2003 Micron Technology, Inc. All rights reserved.

Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

The SDRAM provides for programmable READ or

Pin Descriptions (TSOP)

25-27, 60-66, 24,

16, 71, 28, 59

44, 58, 72, 86

Supply Power Supply: +3.3V 0.3V.

Ball Descriptions (FBGA)

K9, K1, F8, F2

G8, G9, F7, F3, G1,

R8, N7, R9, N8, P9,

Supply Power Supply: Voltage dependant on option.

No Connect: These pins should be left unconnected. H3 is a No Connect for

In general, this 256Mb SDRAM (2 Meg x 32 x 4 banks) is

Accesses within a given burst may be programmed to

ORDER OF ACCESSES WITHIN

Figure 4: Mode Register Definition

WB Op Mode CAS Latency

Mode Register (Mx)

Write Burst Mode

Programmed Burst Length

Single Location Access

All other states reserved

Figure 5: CAS Latency

The CAS latency is the delay, in clock cycles, between

The normal operating mode is selected by setting M7

Write Burst Mode

7, 8, and 9) appear following Operations on page 15;

Truth Table 1 Commands and DQM Operation

CAS# WE# DQM

COMMAND INHIBIT (NOP)

WRITE (Select bank and column, and start WRITE burst)

LOAD MODE REGISTER

The mode register is loaded via inputs A0A11. See

The ACTIVE command is used to open (or activate) a

The READ command is used to initiate a burst read

Auto precharge is a feature which performs the same

A subsequent ACTIVE command to another bank can

Figure 6: Activating a Specific Row in a

Figure 7: Example: Meeting tRCD (MIN)

(MIN) = 20ns, tCK = 7ns

ENABLE AUTO PRECHARGE

Figure 9: CAS Latency

vided that I/O contention can be avoided. In a given

Data from any READ burst may be truncated with a

Figure 13: READ-to-WRITE with Extra

The DQM input is used to avoid I/O contention, as

Full-page READ bursts can be truncated with the

Figure 14: READ-to-PRECHARGE

During WRITE bursts, the first valid data-in element

for a fixed-length WRITE burst may be immediately

Figure 16: WRITE Command

ENABLE AUTO PRECHARGE