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Training Unit
Digital Technique 4
Theory
No: EE 091
Training Unit
Digital Technique 4
Theoretical Part
No.: EE 091
Edition:
2008
All Rights Reserved
Editor:
DIGITAL TECHNIQUE 4
CONTENTS
Page
MEMORY .....................................................................................................................4
1.1
General ................................................................................................................4
1.2
1.3
1.4
1.5
1.6
1.7
1.8
General ..............................................................................................................13
2.2
2.3
2.4
Delaying of pulses..............................................................................................14
2.5
General ..............................................................................................................16
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
Frequency dividers.............................................................................................18
3.4
Shift register.......................................................................................................18
CODES.......................................................................................................................20
4.1
General ..............................................................................................................20
4.2
4.2.1
4.2.2
4.2.3
4.2.4
Gray code.......................................................................................................21
4.2.5
4.2.6
4.3
4.3.1
ASCII-code.....................................................................................................23
4.3.2
Hex-ASCII-code .............................................................................................24
4.3.3
4.4
DIGITAL TECHNIQUE 4
LEARNING OBJECTIVES
DIGITAL TECHNIQUE 4
1.1
MEMORY
General
In digital technology, memories are circuits which are able to convert a shortly present
binary signal arbitrarily at the Input and whose contents can be interrogated. There are
several types of circuits whose basic principle is always a bistable device pair. They are
also known as "flip-flop".
In digital technology, the memory Inputs are called "R" and S".
R
reset
reset Input
set
set Input
reset output
QS
output
1.2
NAND-Iatch
Truth table
Operation:
QR
OS
QS.
0
1
1
1
0
1
1
0
Change of signals:
"0" signal on R, "1" signal an S.
QS and B lead "1" signal. QR and A lead "0" signal.
Change of signals:
If "1" signal is on the inputs R and S then the previous condition remains stored.
Change of signals:
If the "0" signal is on inputs then the QR and QS outputs lead the "1" signal.
1.3
NOR-latch
Truth table
R
QR
OS
0
1
0
1
0
0
0
1
Operation:
"1" Signal on R causes "0"
signal on QS
S and B also have the "0" signal
and output QR has "1" signal.
Change of signals:
"1" signal on S, "0" signal on R.
QR and A lead "0" signal, therefore: Qs has "1" signal.
B and S lead "1" signal, therefore: QR has "0" signal.
Change of signals:
If a "0" signal is on both inputs, then the previous condition remains stored.
Change of signals:
If a "1" Signal is on both inputs, then the QR and Qs outputs lead the "0" signal.
1.4
Because of the high operating speed of electronic systems and if a suitable design has
been made available, it is possible to set or reset binary storages already at the moment
of signal changes.
1.5
Edge- detector
These elements are connected in series with R-S memories. At the output they transmit a
short signal only if the input signal changes.
a)
Symbol
Signal diagram
b)
Symbol
(old
1.6
Symbol
Signal diagram
1.7
This is a special RS-ff where the undesired condition of QR and Qs = 1, and QR and Qs =
0 is prevented.
This is affected by an additional feedback from the output to the Input gates.
Circuit
J=
T=
pulse Input
K=
dynamic reset
Truth table
While during RS-NOR-ff in the R = S = 1 status the outputs QR and Qs have led the "0"
signal, the JK-ff changes into another state. This advantage is applied specially for
frequency dividers and counters. This circuit functions only when the Input Signal changes
are dynamic. The dynamic effect is obtained by RC components.
When the JK-ff is used as a flip flop which is supplied with clock pulses then a status
change can be obtained only when T has a "1" signal.
10
1.8
JK-Master-Slave-flip flop
Circuit
Symbol
11
Signal diagram
The output of the JK-MS-ff changes the state once in every clock pulse.
NOTE:
After 2 clock pulses the ff has returned to its original status.
Therefore, it is also called a binary counting element or 1:2 translator!
12
2.1
TIMING CIRCUITS
General
In digital technique, male monostable trigger elements are used as timing circuits. They
are also called monoflops.
Symbol:
The duration of the output pulse depends on an R-C combination which may be
connected either internally or externally.
2.2
Input pulses with different pulse widths are shortened so that the output pulses have the
same width.
13
2.3
Output pulses which are longer but which last for the same time are generated from short
input pulses.
2.4
Delaying of pulses
The output pulses should be delayed, but the delay time should always be the same.
14
2.5
Manufacturing systems
DTL-technology:
The IC is built from diodes and transistor = diodes - transistor - logic.
Circuits of this technology are particularly insensitive to faults.
TTL-technology:
Circuits can receive and supply relative big currents without getting particularly
hot = transistor - transistor - logic.
ECL-technology:
Shortest switching times and highest switching frequencies. The transistor emitters are
coupled with each other.
The IC consists of transistor and resistance = emitter-coupled logic.
Analogous IC:
They process continually changing signals (audio-frequency variations). Analogous IC's
are male with 3 to 6 amplifier stages.
Application:
Intermediate frequency amplifiers, radio and 1V sets, mixing stages, filter circuits,
operation amplifiers.
MOS-technology:
Logic modules built from MOS-FET in Integrated technology.
Very low control capacity, high packing density.
COS-MOS-technology:
Also CMOS technology, built from complementary MOS-FET's. Simplified circuit.
15
3.1
General
Binary pulses can be counted and displayed with flip flops by counters in any desired time
sequence.
Classification of counters according to
Clock pulses
Mode of counting
Modulo
Code display
forward
binary
asynchronous
backward
10
BCD
synchronous
forward/backward
12
7-segments
pre-selection
16
1 out of 10
3.2
Asynchronous counters
3.2.1
The JK-flip flops are switched as clock flip flops (inputs J and K remain open) and operate
as binary counter elements (binary circuit).
For a maximum counting capacity up to 8 (0-7) a total of 3 flip flops are required.
16
3.2.2
The flip flops are also switched as clock flip flops, except that Q is used for outputs.
3.2.3
Since the used flip flops additionally have static reset inputs it is easy to reduce the
counting capacity as opposed to the maximum possible rate.
A binary counter which should count only to 5 also needs 3 flip flops but the counter
reading 5 must be eliminated through an AND gate.
5 = QA = 1,
QB = 0,
Qc = 1.
When this combination is present all flip flops must be immediately reset. Since this
happens within a very short time this state never occurs; it cancels itself. The counter
counts only to 4.
17
3.2.4
A decade counter has a counting capacity of 10 (0-9). In digital technique, these, counters
are the ones which are most frequently used.
For a counting capacity of 10, 4 flip flops are needed.
3.3
Frequency dividers
Frequency dividers are a simple form of asynchronous counters. Here, the frequency
divider adds always a defined number of pulses and indicates when the total sum has
been reached,
It then flips back into the zero status.
3.4
Shift register
With the shift register, the entire stored word (number of binary characters) may be shifted
by one line, always per one clock pulse.
18
Exercise:
Prepare a logic circuit for an asynchronous forward counter from 0 - 999. The
counter must be resetable to zero at any desired count,
Circuit
19
CODES
4.1
General
The term "code" means symbols and their combination which are used for representing of
numbers, letters and words.
For coding of the decimals from 0 to 9 into the binary system, 4 bits are needed (one
tetrade) = 1001.
As 4 bits allow several and different possibilities while a combination of only 0 to 9 is
needed the numbers 10 to 15 will not be used.
These combinations are called pseudotetrads and may be used for the recognition of
errors.
4.2
4.2.1
This code is based on the binary system. There are two ways of coding multi-digit decimal
numbers:
-
Example: 243:
11110011
Advantage:
simple to calculate
Disadvantage:
very complex
binary-coded-decimal code:
Here, each decimal digit is coded in binaries, and the decimal structure is maintained.
Example: 243:
20
4.2.2
This is a binary code displaced by 3.That means the zero of this code starts from 0011
which is 3 in dual system (see table 4.2.6) Where the combinations 0000, 1111 which can
appear during disturbances, are omitted. Here, they are pseudotetrads and may be used
to recognize errors.
4.2.3
Aiken code
Here, the pseudotetrads are in the centre. The presence of the words 0000 and 1111 is a
disadvantage.
4.2.4
Gray code
What is important in this code is that only one code position changes at the transition of
any two neighbouring code words. It is called a unit-distance- or cyclic code.
It is used for length and angle measuring, with so-called encode rulers and encode disks.
21
4.2.5
This is a 5-bit code where two bits are always"1" and three bits always "0".
A logic circuit can easily watch the bit figure (0,1) and can activate an alarm in case of
erroneous numbers.
4.2.6
Dec.
Dual
Excess 3
Aiken
Gray
2 out of 5
0000
0011
0000
0000
00011
0001
0100
0001
0001
00101
0010
0101
0010
0011
00110
0011
0110
0011
0010
01010
0100
0111
0100
0110
01100
0101
1000
1011
0111
10100
0110
1001
1100
0101
11000
0111
1010
1101
0100
01001
1000
1011
1110
1100
10001
1001
1100
1111
1101
10010
22
4.3
Alphanumeric codes
These are codes whose character set comprises numbers, letters, and special characters.
Usually, they have 5 or 8 bit for each character.
4.3.1
ASCII-code
7 Bits are used for encoding of 128 characters; the eight bit is used as test bit. Here, the
code word is completed by the test bit to an even weight
- EVEN PARITY.
Bits
000
001
010
011
100
101
110
111
6-4
Bits
0000
NUL
DLE
SP
3-0
0001
SOH
DCI
0010
STX
DC2
"
0011
ETX
DC3
0100
EOT
DC4
0101
ENQ
NAK
0110
ACK
SYN
&
0111
BEL
ETB
1000
BS
CAN
1001
HT
EM
1010
IF
SUB
1011
VT
ESC
1100
FF
FS
1101
CR
GS
1110
SO
RS
1111
SI
US
ASCII-Code
23
DEL
4.3.2
Hex-ASCII-code
A hexadecimal character which is encoded in the ASCII code stands for each tetrad of the
dual word.
(hexadecimal system or sedecimal system = system of 16).
For the numbers 0 to 9, also the symbols 0 to 9 are used; from 10 to 15 the letters A to F
are used.
Dec.:
Hex.
10
11
12
13
14
15
Example:
1100
0100
- hexadeclmal coding
1000011
0110100
4.3.3
This is also a 7 bit code with a test bit - EVEN PARITY - and with a feed Crack. It is used
mainly for NC controls.
EVEN PARITY
FEED TRACK
- feed track
ODD PARITY
24
Code table for perforated paper tape according to DIN and /or ISO:
25
4.4
ENCODERS:
Encoders are logic circuits which convert numbers, letters or characters into any desired
code.
DECODERS:
Decoders are logic circuits which convert a certain code to numbers, letters or characters.
CODE CONVERTERS:
Code converters are logic circuits which convert a certain code to any other desired code.
26
Examples:
1.)
2,)
1000
0111
0011
0110
Aiken code:
1110
1101
0011
1100
Excess-3 code
1011
1010
0110
1001
Gray code:
1100
0100
0010
0101
2 of 5 code
10001
01001
01010
11000
draw the contour description and compare the workshop drawing with the
contour description.
Workshop drawing:
27
28
29
30
31
32
Program:
CR
IF
N9030
IF
N10
G94
N20
G01
N30
IF
Z10000
F5000
X6500 IF
N40
ZO
N50
XO
N60
X2000
IF
IF
WO
Z2500 IF
Z7500 IF
N80
X3000 IF
N90
X4500
Z5000 IF
N100
X3000
Z2500 IF
MM
X2000
IF
N120
X0
Z0
N130 M30
IF
IF
Contour description:
33
IF
EE 091
Digital Technique 4
Theoretical Test
34
DIGITAL TECHNIQUE 4
TEST 1
2. Draw the output signal Q of this edge -detector, with preparatory Input terminal.
35
EVEN PARITY.
ODD PARITY.
36
DIGITAL TECHNIQUE 4
TEST 2
1. Draw the RS flip-flop with NAND gate, and prepare the truth fable.
2. 2 Lamps shall be switched on via two pushbuttons, and both switched off via a third
pushbutton.
Lamp No. 2 cannot be switched on unless lamp No. 1 has already been switched on.
Design a logic scheme.
37
4. Design a logic circuit which, after the Input has been disconnected, for 5 seconds still
has the 1 -signal at output Q but the output should immediately activate after the Input
is applied
Draw also the signal diagram,
5. Design a logic circuit which, after switching on, gives a 1 -signal at the output, delayed
by 5 seconds. When switched off, the output must be immediately reset.
Draw the signal diagram.
38
8. Draw an RS flip-flop with dominating setting, that is, resetting is possible only when a
0 signal is present at the setting Input.
39
DIGITAL TECHNIQUE 4
TEST 1
(Solution)
1.
2.
3.
40
6. Clock pulse:
synchronous, asynchronous
3, 5, 10, 16,
Code display:
7.
8.
9.
1000
0110
0100
0010
41
DIGITAL TECHNIQUE 4
TEST 2
(Solution)
1.
2.
3.
42
4.
5.
6.
7.
43
8.
9. Numerical codes:
Alphanumerical codes:
10. Decoder:
Encoder:
Code converter:
44
KEY TO EVALUATION
PER CENT
MARK
88 100
75 87
62 74
50 61
0 49
45