Академический Документы
Профессиональный Документы
Культура Документы
Presented by
Anandarup Das
CEDT, IISc, Bangalore
Flow of presentation
Further refinement of the above space vector structure into multiple 12-sided
polygons with conventional 3-level inverters.
Modulation strategies and PWM timing calculation of the above schemes.
Discussion on experimental verification
Transient results with motor accelerated upto rated speed with open-loop V/f
control
2-level
3-level
5-level
3
2
6
7
1
8
12
9 10 11
Part-1
A Combination of Hexagonal and
Dodecagonal Voltage Space Vector Diagram
for Induction Motor Drives
2-level
3-level
5-level
1
8
12
9 10 11
OE: 1.225kVdc
Inverter Topology
C
D
R-phase
B
O
Pole voltage of overall inverter-vAO
Pole voltage of INV3- vBO
Pole voltage of INV2-vAB
Pole voltage of INV1-vCD
Pole voltage
Level
S11
S21
S31
1.366kVdc
1.0kVdc
0.366kVdc
0Vdc
10
Radius of dodecagon
radius= 1.225kVdc
11
Modulating waveform
12
13
Experimental Setup
A digital signal processor (DSP), TMS320LF2812 is used for experimental
verification.
For different levels of output in the pole voltage, three carriers are required.
However, it is difficult to synthesize three carrier waves in the DSP, as such only
one carrier is used and the modulating wave is appropriately scaled and level
shifted.
A 3.7kW induction motor was fed by the proposed inverter operating under
open loop constant V/f control at no load. The motor was made to run under
no load in order to show the effect of changing PWM patterns of the generated
voltage on the motor current, particularly during transient conditions.
In order to keep the overall switching frequency within 1 KHz, number of
samples is decided as follow:
Upto 20 Hz operation: 4 samples per sector.
20 Hz-40 Hz: 2 samples per sector.
Beyond 40 Hz: 1 sample per sector-extending up to final 12-step mode.
Individual inverters are switched less than half of the total cycle.
14
Experimental results-Operation at 10 Hz
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage
Phase current
Overall inverter
INV3
INV2
INV1
15
Experimental results-Operation at 30 Hz
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage
Phase current
Phase voltage and current waveforms
Overall inverter
[Space Vector]
INV2
INV2 switches
INV3
INV1
Pole voltage waveforms
[Inverter Topology]
16
Phase current
Phase voltage and current waveforms
Overall inverter
INV2
INV3
INV1
17
Phase current
INV3
INV1
Inverter Topology
18
Input phase
voltage
Input line
current
The input current to the inverter is not peaky in nature, because of the
presence of the star-delta transformers.
19
Phase
voltage
Phase
current
Transition of motor phase voltage and current
from 24 samples to 12 samples per cycle at 40Hz
Because of the suppression of the 5th and 7th order harmonics, the motor current
changes smoothly during the transition when the number of samples per sector is
reduced from two to one at 40Hz operation.
As the speed of the motor is further increased, the inverter switching states pass
through the inner hexagons and ultimately the phase voltage becomes a 12-step
waveform.
Under all operating conditions, the carrier is synchronized with the start of the
sector.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
20
30 Hz
48.25 Hz
50Hz
Voltage THD
57.59%
27.51%
14.67%
17.54%
Voltage WTHD
0.81%
0.7%
0.97%
1.04%
100
THD
V
n2
V1
Vn
n2 n
WTHD
V1
100
Current THD
12.31%
10.59%
15.6%
19.54%
Current WTHD
0.28%
0.45%
1.2%
1.5%
2
n
It is seen that voltage WTHD is quite low for all the operating conditions, as
such the torque pulsation and harmonic heating in the machine is minimized.
21
22
unit
Phase
voltage
WTHD
IGBT
Switching
loss
IGBT
Conduction
loss
Conduction
loss in antiparallel
diodes
Clamping
diode
conducti
on loss
Total
Loss
40 Hz
Linear modulation
3-level NPC
0.68
95
2180
272
240
2787
4-level NPC
0.46
61
2400
414
350
3225
Proposed Inv
0.46
96
1884
306
2286
48 Hz
Over modulation
3-level NPC
1.22
27
2370
165
130
2692
4-level NPC
0.89
20
2616
243
169
3049
Proposed Inv
0.55
25
1995
207
2227
50 Hz
3-level NPC
4.64
2511
184
2701
4-level NPC
4.64
12
2730
258
3000
Proposed Inv
1.04
10
2034
180
2224
23
Observations
The phase voltage WTHD for the proposed inverter shows considerable
improvement, particularly at higher modulation indices and the 12-step
mode of operation, because of the suppression or elimination of the 6n1
(n=odd) harmonics.
Conduction losses are more dominant than switching losses for IGBT made
inverters. As such, presence of the clamping diodes in NPC inverters
increases the total losses of the inverter. The proposed inverter does not
have any clamping diode and is devoid of any such losses. The switching
losses also remain low for the proposed inverter.
It is seen that the conduction losses in the proposed inverter are always less
than the conventional inverters. This is because in the proposed inverter, for
any level of pole voltage output, two current carrying switches remain in
conduction. This is not always the case in NPC inverters; e.g. for a four level
inverter, at higher modulation indices, three switches per phase carry the
phase load current when the total dc bus voltage is obtained at the pole.
Conduction losses in the proposed inverter are further less in overmodulation region because of the fact that the r.m.s. current in the inverter
is less compared to conventional NPC inverters, due to the suppression or
elimination of the 6n1 (n=odd) harmonics.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
24
Synopsis
At the same time, the linear range of modulation extends upto 96.6% of
base speed. Because of this, and the high degree of suppression of lower
order harmonics, smooth acceleration of the motor upto rated speed is
possible.
Apart from this, the switching frequency of the multilevel inverter output
is always limited within 1 kHz. The middle inverter ( high voltage inverter)
devices are switched less than 25% of the output fundamental switching
period.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
25
Part-II
Generation of Multilevel Dodecagonal Space
Vector Diagram
2-level
3-level
5-level
1
8
12
9 10 11
27
28
29
Inverter Structure
30
31
Vref sin
6
*T ;
V1T1
s
sin
6
V2T2
Vref sin
sin
6
T0 Ts T1 T2 ;
* Ts ;
32
V4, T2
V1, T0
V1, T1
V1, T1
Point Switched
for
Point
Switched
for
V1
T1
V1
T1= 2T1-TS
V2
T2
V4
T2 = 2T2
T0
V1
T0 = 2T0
Note:
T0 >= 0.
T1+T2+T0= T1+T2+ T0=TS.
33
34
C2 is discharged, C4 is charged.
C2 is discharged, C3 is charged.
C1 is discharged, C4 is charged.
C1 is discharged, C3 is charged.
The four switching multiplicities are complementary in nature in terms of capacitor balancing.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
35
undisturbed.
undisturbed.
Point-36: no multiplicity, no
capacitor disturbance
Point-14: no multiplicity, no
capacitor disturbance
36
Phase current
Phase current
Four samples are taken in each sector and switching takes place entirely in
the inner 12-sided polygon.
The phase voltage harmonics reside at 15x12x4=720 Hz, which is 48 times
the fundamental. However, the switching frequency of the pole voltage of
INV1 is (24x15=) 360Hz, while that of INV2 is (32x15=) 480Hz.
The higher voltage inverter switches about 50% of the cycle.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
37
Phase current
Phase current
Three samples are taken in each sector and switching takes place at the
boundary the inner 12-sided polygon. All the 6n1 harmonics, n=odd, are
absent from the phase voltage, while the rest are highly suppressed.
The switching frequencies of the pole voltage of INV1 and INV2 are
respectively (18x23=) 414Hz and (24x23=) 552Hz, with output phase voltage
switching frequency at 828Hz (=23x12x3).
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
38
Phase current
Phase current
Two samples are taken in each sector and switching takes place between the
inner and outer dodecagons.
This is also seen in the phase voltage waveform, since the outer envelope of the
waveform at lower frequency becomes the inner envelope at higher frequency.
The harmonic spectrum of the phase voltage and current shows the absence of
peaky harmonics throughout the range.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
39
Phase current
Phase current
40
Phase current
Pole voltage-low
voltage inverter
Phase current
41
Phase current
Pole voltage-low
voltage inverter
Phase current
This is the 12-step operation, where one sample is taken at the start of a
sector. The phase voltage and current is completely devoid of any 5th and 7th
order harmonics.
42
Voltage
WTHD
Current
THD
Current
WTHD
15Hz
75.4%
1.48%
24.49%
0.56%
23Hz
21.2%
0.54%
9.19%
0.48%
40Hz
24.85%
0.71%
12.08%
0.65%
48Hz
9.67%
0.33%
5.52%
0.26%
49.9Hz
7.26%
0.28%
4.68%
0.24%
50Hz
17.54%
1.04%
19.54%
1.5%
100
THD
2
n
n2
V1
Vn
n2 n
WTHD
V1
100
It is seen that voltage WTHD is quite low for all the operating conditions, as
such the torque pulsation and harmonic heating in the machine is minimized.
43
Phase
voltage
Phase
current
Transition of motor phase voltage and current
from inner to outer 12-sided polygon
In both the cases, the motor current changes smoothly as the motor
accelerates. This happens because of the use synchronized PWM and total
elimination of 6n1 harmonics, n=odd, from the phase voltage throughout
the modulation index.
44
Vc1, Vc2
Deliberate unbalancing
Capacitor unbalance is
done at steady state
with the motor running
at 20 Hz speed.
Both side capacitors are
deliberately unbalanced
and after some time
controller action is
taken.
Vc3, Vc4
45
Vc1, Vc2
Deliberate unbalancing
Vc3, Vc4
46
Synopsis
The entire space vector diagram is divided into smaller sized isosceles
triangles. PWM switching on these smaller triangles reduces the inverter
switching frequency without compromising on the output voltage quality.
47
Part-III
A Voltage Space Vector Diagram Formed By
Six Concentric Dodecagons
2-level
3-level
5-level
1
8
12
9 10 11
49
50
The power circuit of the inverter consists of 2 three level NPC inverters
feeding an open end induction motor.
These two inverters are fed from isolated dc voltage sources having voltage
ratio of 1:0.366. This ratio of voltages is obtained from a combination of star
delta transformers since 1:0.366= (3+1):1.
52
53
PWM timing calculations are done separately for type-1 and type-2 dodecagons.
[movie]
56
V4, T2
V3, T1
V1, T1
Point Switched
for
Point
Switched
for
V1
T1
V3(=k V1)
T1=T1/k
V2
T2
V4(=k V2)
T2=T2/k
T0
T0
Note:
T0 0
57
V4, T2
V3, T1
V1, T1
58
Points O,K and J are from type-1 polygon, while point F is on type-2 polygon.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
59
r4
r5
T0
T1
Point Switched
for
Point
Switched
for
T0
T0 = T0 / (1-k1)
T1
T1=T1- T0 . k1/2
T2
T2=T2- T0 . k1/2
k1 =
60
Experimental verification
A 3.7kW induction motor was fed by the proposed inverter under experimental
condition, operating under open loop constant V/f control at no load. The
motor was made to run under no load in order to show the effect of changing
PWM patterns of the generated voltage on the motor current.
In order to limit the switching frequency of the inverter, number of samples is
decided as follow:
Upto 10 Hz operation: 8 samples per sector.
10 Hz-30 Hz: 4 samples per sector.
30Hz-12step operation: 2 samples per sector leading to final 12-step mode.
The samples are always taken synchronized with the start of the sector.
A digital signal processor (DSP), TMS320LF2812 is used for experimental
verification. The DSP is used for calculating the PWM timing durations. The
actual gating signals to drive all the devices are generated using a SPARTAN
XC3S200 FPGA. The FPGA stores the look-up table for the switching state
combination of both the inverters for a particular space vector point.
63
Phase current
Phase current
64
Phase current
Phase current
Switching happens within the first and second dodecagonal space vectors.
4 samples are taken in a sector, so the first band of carrier harmonics
reside around 48 times the fundamental.
Because of the multilevel structure, all the harmonics are highly
suppressed.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
65
Operation at 24.5 Hz
66
Phase current
Pole voltage-low
voltage inverter
Phase current
67
Phase current
Pole voltage-low
voltage inverter
Phase current
68
Vectors numbered 37, 48, 50 and 60 switched at the positive peak of the
phase-A waveform have same projection on A-phase axis.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
69
Phase current
Pole voltage-low
voltage inverter
Phase current
70
Vectors numbered 49, 61 and 72 switched at the positive peak of the phase-A
waveform have same projection on A-phase axis.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
71
Phase current
Pole voltage-low
voltage inverter
Phase current
72
Because of the presence of the star-delta transformer at the input that forms
the dc bus ratio, the input current is more sinusoidal than what is observed in a
single transformer supplying an uncontrolled rectifier
73
Phase
voltage
Phase
current
Transition of motor phase voltage and current
from 20 Hz to 30Hz
In the first case, the reference vector starts from inside dodecagon E, crosses
through the boundary of it and finally settles below the D dodecagon.
In the second case, the number of samples per sector is changed from 2 to 1 at
12-step operation.
Correct calculation of the PWM timings and complete elimination of the 5th and 7th
order harmonics ensure that the motor current changes smoothly during the
transition.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
74
unit
Phase
voltage
THD
Phase
voltage
WTHD
Phase
current
THD
Phase
Current
WTHD
20 Hz
5-level Inv
28.76
0.68
10.73
0.54
Proposed Inv
22.26
0.51
8.53
0.42
24.5 Hz
5-level Inv
19.78
0.54
9.85
0.52
Proposed Inv
16.24
0.42
7.14
0.43
46 Hz
5-level Inv
19.91
0.77
16.05
0.89
Proposed Inv
15.69
0.57
12.62
0.62
49.9 Hz
5-level Inv
15.3
1.31
18.8
3.07
Proposed Inv
7.26
0.28
4.68
0.24
50 Hz
5-level Inv
30.54
4.64
52.47
9.55
Proposed Inv
17.54
1.04
19.54
1.5
75
The rms value of the flux ripple is calculated and plotted above under constant
V/f ratio and 24 samples in a fundamental period.
It shows that for most of the operating conditions, the flux ripple is around 1%
of the fundamental flux impressed on the machine, and thus restricts the
torque ripple in the machine.
76
Synopsis
A new space vector diagram for induction motor drive is proposed, which
divides the space vector plane into six concentric dodecagons.
Apart from this, the known benefits of dodecagonal space vector diagram
like the complete elimination of all 6n1 harmonics, (n=odd) from phase
voltage and the extension of linear modulation range, are also retained here.
The high voltage inverter having a voltage of about 3 times the lower one, is
switched almost 1/3rd compared to the low voltage inverter.
A comparison with 5-level inverter topology is also given which shows that
the present scheme produces less harmonic distortion in the phase voltage.
Because of the use of star-delta transformers for having the dc bus in the
ratio 1:0.366, the input current has lesser harmonics compared to the case
when a single transformer supplies the inverter.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
77
Conclusion
In one of the schemes, the space vector diagram consists of two concentric
dodecagons, with the radius of the outer one twice the inner one. This has the
benefit of reducing the device rating and dv/dt stress on the devices.
This is then further refined to distribute six dodecagons in the space vector
diagram. Switching on these closely spaced dodecagons will highly reduce the
harmonic content in the phase voltage, apart from totally eliminating all the 5th
and 7th order harmonics from the phase voltage.
With increased linear modulation range, less switching frequency and improved
harmonic spectrum, the proposed concepts may be considered as an interesting
addition to the field of multilevel inverters for high/medium voltage high power
applications.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
78
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, "A
Combination of Hexagonal and 12-sided Polygonal Voltage Space Vector PWM control for
IM Drives Using Cascaded Two Level Inverters", IEEE Trans. On Industrial
Electronics, vol. 56, no. 5, May 2009, pp. 1657-1664.
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, "A Pulse
Width Modulated Control of Induction Motor Drive Using Multilevel 12- sided Polygonal
Voltage Space Vectors", IEEE Trans. on Industrial Electronics, vol. 56, no. 7, July
2009, pp. 2441-2449.
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, "A High
Resolution Pulse Width Modulation Technique Using Concentric Multilevel Dodecagonal
Voltage Space Vector Structures", Proc. of ISIE 2009, Jul. 2009. (Best paper award
in the conference).
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar,
"Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor
Drive Using Conventional Three Level Inverters", Proc. of EPE 2009, Sep 2009, pp 1-8.
Anandarup Das, K. Sivakumar, Gopal Mondal and K. Gopakumar, "A Multilevel Inverter
with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor
Drive", Proc. of IECON 2008, Nov 2008, pp 1077-1082.
Anandarup Das and K. Gopakumar "A Voltage Space Vector Diagram Formed By Six
Concentric Dodecagons for Induction Motor Drives", communicated to IEEE Trans. on
Power Electronics.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
79