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Remember the Standard Vt Equation?

Short Channel MOS Transistor

Vt = V fb + 2 B +

2qN a si 2 B
Cox

Y. Taur, T. Ning, Fundamentals of Modern VLSI Devices,


Cambridge University Press, 2002.

Professor Chris H. Kim

Detailed derivation given in Taurs book


Basically, three terms

University of Minnesota
Dept. of ECE

Flat band voltage


2B: the magic number for on-set of inversion
Oxide voltage

chriskim@umn.edu
www.umn.edu/~chriskim/

Body Effect (Back Bias)

Body Effect (Back Bias)


Vt 0 = V fb + 2 B +

Cox

Vt = V fb + 2 B + Vsb +
Vt = V fb + 2 B +

Drain

2qN a si 2 B
2qN a si 2 B + Vsb
Cox

2qN a si 2 B + Vsb
Cox

Gate
Vsb

Source

Body
+ Vsb

Vsb > 0 : RBB


Vsb < 0 : FBB

Body effect degrades transistor stack performance


However, we need a reasonable body effect for post silicon
tuning techniques
Reverse body biasing, forward body biasing
3

Vt can be adjusted by applying FBB or RBB


Essential for low power and high performance
Will talk about body biasing extensively later on

Body Biasing for Process Compensation

Normalized leakage

Die count

100%
80%
60%
40%
20%
0%
6

Accepted
dies:
NBB

Short Channel Effect: Vt roll-off

110C
1.1V

Long Channel

Short Channel

n+ poly gate

ABB

n+ poly gate

n+ source

ABB

n+ source

n+ drain

depletion

Charge sharing

n+ drain

Charge sharing

p-type body

p-type body

Body bias:
controllability
to Vt

2
1

NBB

0
0.925

1
1.075
1.15
Normalized frequency

Ec

Ec

Ability of gate & body to control channel charge diminishes


as L decreases, resulting in Vt-roll-off and body effect
reduction

1.225

Short Channel Effect: Vt roll-off

Short Channel Effect: Drain Induced


Barrier Lowering (DIBL)
Long Channel

Short Channel

n+ poly gate

Vt

n+ source

n+ poly gate
n+ source

n+ drain

n+ drain

depletion

3 L variation

p-type body

p-type body

Ec

Leff
Vds

3 Vt variation increases in short channel devices

Ec

Vds

Increase in VDS reduces Vt and increases Vt-roll-off: DIBL


8

Short Channel Effect: DIBL

Short Channel Effect: Drain Induced


Barrier Lowering (DIBL)

Vds=2.0V

Vt

log(Ids)

Vt roll-off (Vds~0V)

log(Ids)

Vds=0.1V

DIBL+Vt roll-off
(Vds=Vdd)
Vgs (NMOS)

Leff

Vgs

Vt
DIBL coefficient d =
Vds

(PMOS)

DIBL increases leakage current


Dynamic Vdd can reduce leakage because of DIBL

Short Channel Vt Equation

Cox

0.7
0.6

(Long channel Vt equation)

PMOS

0.2

S. Thompson et al., 1998.

0.4
0

Xj
2W
1
b = 1 1 +

L
X
j

50
100
150
Junction Depth (nm)

0.1
200

Salicide
Poly-Si

[Ng, TED, 1993]

2
2.2m (Tox + 0.012 m)(Wsd + 0.15m)( X j + 2.9m)

0.3

0.5

[Poon, IEDM, 1973]

0.4

NMOS

130

0.2
L MET

0.15

R EXT

0.1

120

R EXT ( m)

2qN a si 2 B

0.5

L MET ( m)

Cox

0.8

2qN a s ( 2 B + Vsb ) dVds

IDP (mA/ m)

Vt = V fb + 2 B +

Transistor Scaling Challenges - Xj


IDN (mA/ m)

Vt = V fb + 2 B +

10

110
100

0.05
S. Thompson et al., 1998.

90
50
100
150
200
Junction Depth (nm)

S. Asai et al., 1997.

Salicide

2.7

d =

RC
RSE
11

Rsalicide
12

Effect of Series Resistance

Leakage Components

(10nm Device)

Weak Inversion Current,


Drain Induced Barrier Lowering
and Narrow Width Effect

Gate Oxide Tunneling

Gate

Source

Drain

n+

n+
Punchthrough

p-sub

Gate Induced Drain


Leakage (GIDL)

Reverse Bias Diode


& BTBT

Bulk
[Keshavarzi, Roy, and Hawkins, ITC 1997]
13

Sub-Threshold Current

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Sub-Threshold Current
q (V gs Vt )
qVds
k T
W
mkT
kT
(1 e
)
I d = eff Cox B (m 1) e
q
L

NPN BJT is formed in sub-threshold region


Only difference with a real BJT is that the base voltage is
controlled through a capacitive divider, and not directly
by a electrode
Like in a BJT, current is exponential to Vbe
15

16

Vdd and Vt Scaling

Sub-Threshold Swing

Performance vs Leakage:

Cdep
kT
ln 10 (mV
) , m = 1+
dec
q
Cox

log(IDS)

S= m

VT IOFF ID(SAT)
I OFF

Smaller S-swing is better


Ideal case: m=1 (Cox>>Csub)

Fundamental limit = 1 * 26mV * ln10


= 60 mV/dec @ RT
Can only be achieve by device geometry (FD-SOI)

Weff
Leff

I D ( SAT )

Weff
Leff

VT

K1e

mkT / q

IOFFL

K 2 (VGS VT ) 2

IOFFH
VTL VTH

I D ( SAT ) K 3Weff Cox SAT (VGS VT )

Typical case: m1.3


S = 1.3 * 26mV * ln10 80 mV/dec @ RT
At worst case temperature (T=110C), S 100 mV/dec

VGS

As Vt decreases, sub-threshold leakage increases


Leakage is a barrier to voltage scaling
17

18

Vdd and Vt Scaling

Gate Oxide Tunneling Leakage

Now, consider we scale the Vt to 100mV


Ioff=10A/m x 10-1 = 1 A/m

103 3
2

2.5nm
3.5nm

IGATE (A/cm2)

Vt cannot be scaled indefinitely due to increasing leakage


power (constant sub-threshold swing)
Example
CMOS device with S=100mV/dec has Ids=10A/m
@ Vt=500mV
Ioff=10A/m x 10-5 = 0.1 nA/m

100

10-7

2
3
4
5
6
7

5.1nm

IGATE

7.6nm

3.0nm

IOFF

C. Hu, 1996.

e-

10 12

Gate Voltage (V)


N+ Gate

Suppose we have 1B transistors of width 1m


Isub=1A/m x 1B x 1m = 100 A !!
19

P- Substrate

20

Gate Oxide Tunneling Leakage

Band-to-Band Tunneling Leakage


EC

Quantum mechanics tells us that there is a finite


probability for electrons to tunnel through oxide
Probability of tunneling is higher for very thin
oxides
NMOS gate leakage is much larger than PMOS
Gate leakage has the potential to become one of
the main showstoppers in device scaling

I gate = AEox e
2

Eox

q(Vbi+Vapp)
EV
EC

p(+)-side

n(+)-side

EV

S/D junction BTBT Leakage

V Vt
, Eox = dd
tox

Reversed biased diode band-to-band tunneling


High junction doping: Halo profiles
Large electric field and small depletion width at the junctions
21

Gate Induced Drain Leakage (GIDL)


Appears in high E-field region under gate/drain
overlap causing deep depletion
Occurs at low Vg and high Vd bias
Generates carriers into substrate from surface
traps, band-to-band tunneling
Localized along channel width between gate and
drain
Thinner oxide, higher Vdd, lightly-doped drain
enhance GIDL
High field between gate and drain increases
injection of carriers into substrate

22

Narrow Width Effect


Gate

Vt

width

W
Extra depletion
region

Channel

Side view of MOS transistor

23

Depletion region extends


outside of gate controlled
region
Opposite to Vt roll-off
Depends on isolation
technology
24

Leakage Components

[IEEE press, 2000]


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