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Data Sheet
March 4, 2010
FN3403.5
Features
Applications
Portable Instruments
Telephone Headsets
Meter Amplifiers
Medical Instruments
Pinouts
-INA
+INA
V-
OUTA
ICL7621
(8 LD PDIP, SOIC)
TOP VIEW
V+
OUTB
-INB
+INB
Ordering Information
TEMP.
RANGE
(C)
PART
NUMBER
PART
MARKING
ICL7621DCPA
7621 DCPA
ICL7621DCPAZ*
(Note 2)
E8.3
7621 DCPAZ 0 to +70 8 Ld PDIP D Grade - IQ = 100A
ICL7621DCBA
(Note 1)
7621 DCBA
ICL7621DCBAZ
(Notes 1, 2)
PACKAGE
PKG.
DWG. #
E8.3
0 to +70 8 Ld PDIP D Grade - IQ = 100A
M8.15
0 to +70 8 Ld SOIC D Grade - IQ = 100A
*Pb-free PDIPs can be used for through hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
NOTES:
1. Add -T suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL7621
Absolute Maximum Ratings
Thermal Information
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
JA (C/W)
JC (C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
120
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . +150C
Maximum Storage Temperature Range . . . . . . . . . . -65C to +150C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time.
4. The outputs may be shorted to ground or to either supply, for VSUPPLY 10V. Care must be taken to insure that the dissipation rating is not
exceeded.
5. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYMBOL
VOS
VOS/T
TEST CONDITIONS
RS 100k
RS 100k
IOS
IBIAS
TEMP.
(C)
MIN
MAX
(Note 6) TYP (Note 6) UNITS
+25
15
mV
Full
20
mV
25
V/oC
+25
0.5
30
pA
0 to +70
300
pA
-55 to +125
800
pA
+25
1.0
50
pA
0 to +70
400
pA
-55 to +125
4000
pA
VCMR
IQ = 100A
+25
4.2
VOUT
IQ = 100A, RL = 100k
+25
4.9
0 to +70
4.8
-55 to +125
4.5
+25
80
102
dB
0 to +70
75
dB
-55 to +125
68
dB
+25
0.48
MHz
+25
1012
AVOL
GBW
Input Resistance
IQ = 100A
RIN
CMRR
RS 100k , IQ = 100A
+25
70
91
dB
PSRR
RS 100k , IQ = 100A
+25
80
86
dB
eN
RS = 100, f = 1kHz
+25
100
nV/Hz
iN
RS = 100, f = 1kHz
+25
0.01
pA/Hz
ISUPPLY
+25
0.1
0.25
mA
Channel Separation
VO1/VO2
AV = 100
+25
120
dB
FN3403.5
March 4, 2010
ICL7621
Electrical Specifications
PARAMETER
SYMBOL
TEMP.
(C)
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
Slew Rate
SR
+25
0.16
V/s
Rise Time
tR
+25
Overshoot Factor
OS
+25
10
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Schematic Diagram
IQ
SETTING STAGE
INPUT STAGE
3k
QP5
QP3
QP7
V-
100k
QP2
V+
900k
3k
QP1
OUTPUT STAGE
QP6
QP4
6.3V
QP8
V+
+INPUT
QP9
QN1
QN2
CFF = 9pF
OUTPUT
VV+
CC = 33pF
-INPUT
QN9
QN7
QN4
V-
TABLE OF JUMPERS
ICL7621
C, E
IQ
100A
QN10
QN6
QN5
V+
QN3
QN8
QN11
6.3V
E
G
V-
FN3403.5
March 4, 2010
ICL7621
Application Information
Static Protection
Latchup Avoidance
Junction-isolated CMOS circuits employ configurations
which produce a parasitic 4-layer (PNPN) structure. The
4-layer structure has characteristics similar to an SCR, and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To
avoid this condition, no voltage greater than 0.3V beyond the
supply rails may be applied to any pin. In general, the op
amp supplies must be established simultaneously with, or
before any input signals are applied. If this is not possible,
the drive circuits must limit input current flow to 2mA to
prevent latchup.
Frequency Compensation
The ICL76XX are internally compensated, and are stable
for closed loop gains as low as unity with capacitive loads
up to 100pF.
Typical Applications
The user is cautioned that, due to extremely high input
impedances, care must be exercised in layout, construction,
board cleanliness, and supply filtering to avoid hum and
noise pickup.
+5
ICL76XX
VOUT
+5
VIN
ICL76XX
VOUT
RL 10k
TO CMOS OR
LPTTL LOGIC
100k
1M
1/2
ICL7621
1M
VOUT
1/2
ICL7621
1F
+
ICL76XX
1M
1M
VV+
DUTY CYCLE
680k
WAVEFORM GENERATOR
NOTE: Since the output range swings exactly from rail to rail,
frequency and duty cycle are virtually independent of power supply
variations.
FIGURE 4. TRIANGLE/SQUARE WAVE GENERATOR
FN3403.5
March 4, 2010
ICL7621
1M
+8V
VOH
VIN 10k
20k
2.2M
0.5F
+
1/2
ICL7621
10F
TO
SUCCEEDING
INPUT
STAGE
20k
1.8k = 5%
SCALE
ADJUST
OUT
VOL
V-
V+
1/2
ICL7621
+
COMMON
TA = +125C
V+
-8V
0.2F
0.2F
30k
160k
+
1/2
ICL7621
0.2F
680k
100k
51k
+
1/2
ICL7621
INPUT
360k
0.1F
360k
0.2F
NOTE 7
1M
0.1F
OUTPUT
1M
NOTE 7
NOTES:
7. Small capacitors (25pF to 50pF) may be needed for stability in some cases.
8. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4,
Passband ripple = 0.1dB.
FIGURE 7. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER
FN3403.5
March 4, 2010
ICL7621
Typical Performance Curves
104
10k
TA = +25C
NO LOAD
NO SIGNAL
1k
IQ = 100A
100
10
6
8
10
SUPPLY VOLTAGE (V)
12
14
-25
10
1.0
-25
0
25
50
75
FREE-AIR TEMPERATURE (C)
100
105
IQ = 100A
103
102
10
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
50
75
100
125
VSUPPLY = 10V
VOUT = 8V
100
RL = 100k
IQ = 100A
10
1
-75
125
-50
-25
25
50
75
100
125
TA = +25C
VSUPPLY = 15V
1.0
25
107
104
100
10
1000
VS = 5V
1
0.1
IQ = 100A
102
1000
106
103
1
-50
16
0.1
-50
V+ - V- = 10V
NO LOAD
NO SIGNAL
105
VSUPPLY = 10V
100
95
IQ = 100A
90
85
80
75
70
-75
-50
-25
25
50
75
100
125
FN3403.5
March 4, 2010
ICL7621
(Continued)
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
VSUPPLY = 10V
95
90
IQ = 100A
85
80
75
70
65
-75
-50
-25
25
50
75
100
125
600
TA = +25C
3V VSUPPLY 16V
500
400
300
200
100
0
10
100
1k
FREQUENCY (Hz)
TA = +25C
IQ = 100A
VSUPPLY
= 5V
6
4
2
0
100
VSUPPLY
= 2V
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0.1
IQ = 100A
1.0
10
10
12
14
16
8
INPUT AND OUTPUT VOLTAGE (V)
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE (VP-P)
0.01
VSUPPLY
= 8V
12
10
100k
16
14
10k
4
2
OUTPUT
0
-2
INPUT
-4
-6
20
40
60
80
100
120
TIME (s)
FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 100A)
FN3403.5
March 4, 2010
ICL7621
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
0.210
5.33
A1
0.015
0.39
A2
0.115
0.195
2.93
4.95
0.014
0.022
0.356
0.558
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
0.008
0.014
0.204
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
0.13
0.300
0.325
7.62
8.25
E1
0.240
0.280
6.10
7.11
0.100 BSC
eA
0.300 BSC
eB
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
D1
0.355
10.16
2.54 BSC
7.62 BSC
0.430
0.150
2.93
8
10.92
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN3403.5
March 4, 2010
ICL7621
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
B M
INCHES
SYMBOL
-B1
L
SEATING PLANE
-A-
h x 45
-C-
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
A1
0.0040
0.0098
0.10
0.25
0.013
0.020
0.33
0.51
0.0075
0.0098
0.19
0.25
0.1890
0.1968
4.80
5.00
0.1497
0.1574
3.80
4.00
B S
0.050 BSC
1.27 BSC
0.2284
0.2440
5.80
6.20
0.0099
0.0196
0.25
0.50
0.016
0.050
0.40
1.27
NOTES:
MILLIMETERS
8
0
8
8
7
8
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN3403.5
March 4, 2010