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626

DESIGN OF A TWO STAGE, 1 KW BATTERY CHARGER WITH POWER


FACTOR CORRECTION
F.Canales", D.Abud*, J.Arau** and G. Jimenez"

*
Centro Nacional de lnvestigacion y Desarrollo Tecnologico, Mexico
lnstituto de lnvestigaciones Electricas, Mexico
**

ABSTRACT
The fast and constant (evolution of the
electronic *s circuits in the last decade, require a
similar behavior from the power supply systems,
searching for more competitive electronic *s
equipment (with greater storage capacity, better
relationship of weight, volumc?, cost, etc.).
This paper present,, the results of the
implementation of a Two stages AC/DC preregulator".
using a BOOSTco,vverter /as a power
factor corrector), and a Full- Bridge ZVS-PWM
converter, in order to improve the dynamic
features of the DC bus, working as well as a
battery charger within the scheme of Distributed
Power Supply in which it will be used.

1. INTRODUCTION
Nowadays, it is not enough to increase the power
density (which implies the usi: of hgh frequency
conversion strategies, very elaborated mounting
techniques, etc,) to meet the requirements of
modularity, redundancy, battery backing which appear
to be necessary for the next generation of power
supplies.
Distributed architectures in a power supply system (fig.
1) solve part of the problem, introducing new challenges
and opening very attractive research areas. The most
interesting challenge in the primary stage of power
supply is probably the power factor correction.
ON-BOARD Cmveiles ,-\

Tradxional Distributed Power Supply

scheme.
This work was done under a collaboration program between
IIE and CENIDET.

2. ONE STAGE vs TWO STAGES SOLUTIONS


Since for the primary stage (AC/DC pre-regulator) it is
necessary to supply galvanic isolation, there are several
ways to incorporate the capacity of the power factor
correction.
There are plenty of references in the literature where the
problem is analyzed and different alternatives with
PWM topologies as well as resonants are proposed.
However, the principal characteristics are shown in the
block diagrams in fig 2a and 2b.
Hy E. . DC I DC
...: :... a
j 'WC'STAGE i j GALVANIC
AC I DC . .

iu

. , tmaglcr

: j iSOLATlON

A&anfa@a ' Disadvanlsws :

* Bctlsi &vnamr: characteristics. complex

..............

.~ .............. ,

Smaller OUlpUl GWPCIIOI Idtel.

Fieure.2 Implementation alternatives for an ACIDC


prs-regulator with PFC, a) One stage
solutions and b) Two stage solutions.

The paper presents the result of the implementation of


a "Two stages AC/DC Pre-regulator" (see fig. 3), using
a BOOST converfer (as a power factor corrector), and
a Full- Bridge ZVS-PW convener, in order to improve
the dynamic features of the DC bus, working as well as
a battery charger within the scheme of Distributed
Power Supply in which it will be used.
'Power Electronics and Vinable-Speed Drives: 26 - 28 October 1994. Conference Publicafion No. 399, Q) IEE, 1994

627
~

Figurc.3 Simplified diagram fbc thc selected solution

3. POWER FACTOR CORRECTION STAGE


The Power Factor Correction stage (PFC) was designed
based on a boost power topology [lO,ll], using peak
curretzf mode confrol (see figure 4) with the specific
purpose ML4812 IC. 'Ikzre are others power topologies
and control techniques which can be used to implement
the PFC feature [9], however, the BOOST topology was
chosen, based on its low harmonics injection
characteristic (non-pulsating input current) and input
current sensing facilities ( inductor current is the input
current).
~ ~~

Figure 4; Details of the BOOST power stage implemented ns a


Power Factor C(irrector.

3.1 Operation
Asuming that, the transistor is just tumed on, the
inductor current rises from its last value, to the current
reference level, in this moment the transistor is tumed
off and the inductor current decreases. When a complete
oscillation cycle finishes, the driver tums on the
transistor and a new cycle begins.
The current reference is a sine waveform which is a
sample of the rectified line voltage, multiplied by the
output of the error amplifier. The magnitude of' the
voltage error amplifier (VEA) is proportional to the
output power stage and reference voltages. If the output
voltage falls, the VEA rises and the current reference
too, so this cause an increment in the input line current.
On the other way, if the output voltage rises, the VEA
as well as the current reference decrease, causing a
decrement in the input line current.

3.2 Critical design considerations


When a boost topology is working as a PFC, emphasis
should he made on the following design considerations:
1. Dm < = 0.95, In order to minimiw losses in power
semiconductor.
The losses in a boost power topology are increased
when the duty cycle is greater than 95 A. In addition
large signal instability could he present in this condition
due non ideal parasitic elements which introduce new
concepts and prlcaution to be considered.
The maximum duty cycle can be fixed by choosing the
correct values of the oscillator elements (C, and R,[13].)
2. Ramp compensation must be included.
The characteristics of the peak current mode control,
makes necessary to implement a ramp compensation. In
the ML4812 this feature is implemented by placing a
single resistor (Rsc) in pin 7, according with the
following formula.
2.5 *Rm

Asc +Sm+RT*CT
RFC =

Where:
R, and C, are the oscillator components (131.
A, is the amount of slope compensation.
S,, The downslope as reflected to the input of the
PWM comparator.
3. Bandwidth must be in accordance with the line
frequency.
The voltage loop bandwidth should he set such that it
rejects the 100 Hz or 120 Hz ripple which is presented
at the output voltage typical bandwidth range in FPC
application is normaly bellow 15 Hz. Finally, the main
compromise is between transient response and
distortion.
4. Outout voltage Vout = 360 Vcd .
5. The voltage where the inductor dries out V,
(inductor design).
The first step and probably the most important premise

in calculating the inductor value is to determinate the


voltage at which the inductor dries out (V+) [13].
V+ = [ 1 -D<mcM*M VJ out = 20 V
6. An extra low freauencv (100 or 120 Hz) filter
capacitor must he included.
Because of the characteristic of the PFC system, the
output capacitor should be calculate at twice the line
frequency. But it is necessary to eliminate the high
frequency ripple so that a shunt capacitor of a low value
should be used, at the output, in order to eliminate this
high frequency ripple.
628

7. The minimum load rwuerimentL


It is necessary to determinate the amount of the
minimum load because this value will determinate the
inductor size of the power stage.
The minimum load condition, in this specific
application, is 200 Watts.
8. Current sense system.
In peak current mode control it is. necessary to take a
sample of the transistor current (inductor current when
Q1 is on, see figure 11). In order to improve the
efficiency of the PFC system a current transformer
should be use. Once the current transformer was chosen
the Rsense (Rs) can be calculated [13].
9. Wave form reference.
It is necessary to take a sample of the input voltage. In
the MU812 the sinewave reference input (Ic,,.*,) is a
current input so it is necessary to limit this current to a
maximum peak level of 0.5 mA b y using a resistor R1
(figure 11).
10.Power staee inductor calculation.
Considering that the minimum input voltage is 90 Vac
and the maximum 260 Vac, the switcbng frequency is
100 Khz and the maximum power output is lo00 W. the
input inductor can be calculated by the following
formula [13].
3.3 Circuit design
The minimum load condition occurs when the batteries
are full charged and only one rack, is COMeCted with its
minimum configuration. In this application the minimum
load is almost 200 W.
Considering that the output power of the P.F.
preregulator is equal to the input power. The minimum
input voltage is 90 Vac and the maximum 260 Vac.
The switching frequency was chosen at 100 Khz at
maximum duty cycle (D) of 0.95.
The first step in calculating the inductor value is to
determinate the voltage at which the inductor dries out
W,J ~ 3 1 .
Step 1. V , = 11 - Da(MU*L JV out = 20 V
Step 2. Find the minimum operating current
1" = 1.136
step 3.
The over voltage protection (OVP) was implemented
using a resistive voltage divider.
400 Vdc.

540bH

This value was set at


Voltage regulator component. A sample of the output
voltage (Vo) is taken through a resistive divider which
give a 5 volts at its output when Vo is equal to 360
volts.
It is also necessary to calculate the feedback capacitor
for and error amplifier. The voltage loop bandwidth
should be set such that it rejects the 120 Hz ripple
which is presented at the output voltage typical

bandwidth rage is from a few hertz to 15 Hz. The main


compromise is between transient response and
distortion.
Current sense.
In peak current mode control it is necessary to take an
example of the transistor current (inductor current when
Q1 is on, see figure 4). It has been used a sense resistor
in a low power application but in this case the output
power is lo00 watts so it is necessary to use a current
sense transformer. On the other hand the resistor will
dissipate to much power and the efficiency of the system
will be lower.
It is necessary to rake care of de magnetic flux of the
current transformer. This flux should be zero before a
new cycle begins.
Once the current transformer was chosen the Rsense
(Rs) is calculated as follow.
Step 1. Calculate the maximum input current.
The relation of the current transformer is 200: 1 and the
maximum permitted voltage at the current sense input is
5 volts so.
It is necessary to take a sample of the input voltage. In
the ML4812 the sinewave reference input is a
current input so it is necessary to limited this current to
a maximum peak level of 0.5 mA.
Rp=* = 750 KCI
~W"

Now R,., can be calculated by


629

'Ibe downslope as reflectec to the input of the PWM


comparator is given by:

vwl-v Rs

L Nc PS

s---t * -=0.109 In the MU812 the slope compensation is implemented


by putting a single resistor (Rsc) at pin 7, the value of
Rsc can be calculated by the following formula.
RW=- 2.5 r h

As1 : ,sr Rp e,
where:
RT and C, are the oscillator components (131.

& is the amount of slope compensation


ut canwitor.
The output capacitor should be calculated at 120 Hz.
But it is necessary to eliminate the high frequency ripple
so it is necessary to use a shunt capacitor, at the output
capacitor, of low value in order to eliminate this high
frequency ripple. Figure 4 shows a detailed diagram of
the PFC system.

3.4 Circuit implementation


Figure 4 shows some details about the power stage of
the PFC system. with its controls loops. The PWM
control was implemented with the Micro Linear
MU812CP Power Factor Controller, which includes all
the necessary features to implement the PF regulation,
aa a current input multiplier, programmable ramp
compensation, overcurrent and overvoltage protections,

etc.
Input line current and voltage, are shown in the figure
5, in which the PF compensation can be seen in the
input current waveform. Figure 6 shows load variations
effect on the prototype efficiency, for differents input
voltage conditions. Another important result is that the
line regulation is as well as 0.55 5%.

4. THE SOFT-SWITCHING FB-ZVS STAGE

During the last 4 years, resonant-mode operation has

been the preeminent innovation in switching power

supplies. By offering zero-voltage and zero-current


switching topologies, these techniques reduce switching
losses, which give rise to high density power supplies.
However, they generally require a wide range of
fresuency variation, making the optimization of the
filter components difficult.
When the total output power increases above 400 Watts,
topologies with more than one transistor are usually
employed, such as the full-bridge PWM converter.
Unfortunately, when this converter is operated at high
frequencies, the parasitics elements increment the
detrimental effects on the converter performance
[23,71*
Input wavefonnr on the PFC, 1) Input line cumnt and 2)
input line voltage.
iEFRQENcy

/p\

"1

VmU

VnOn
,

. . .............. ..... .. .... .._..."

.. .. I.

78% looK '


U LOAD

Onphicr of the efficiency v8 Load

A recently proposed new operating mode of the fullbridge

PWM converter, enable all the switching devices

to operate under Zero Voltage Switching (ZVS) by


using circuit parasitics to achieve resonant transition at
the commutation time [ l , 81. In order to achieve ZVS,
the two legs of the bridge (see fig. 7) are operated with
a phase shift. This operation allows a resonant
discharge of the output capacitance of the mosfets,
and subsequently, forces the conduction of each
mosfet's antiparallel diode prior to the conduction of
the mosfet. In other words, the drain-to-source voltage
of the mosfet switch is zero when the gate of each nchannel
fet is driven positive to turn it on.
The ZVS-PWM requires no additional active devices,
operates at fixed frequency and uses leakage
inductance of the power transformer to achieve ZVS.
It has a slightly higher "rms" current than the
conventional FB-PWM converter, but has much lower
"rms" current than the resonant converters. The ZVS
allows operation with much reduced switching losses
and component stress, and eliminates the need for
primary snubber.
As shown in figure 8, the falling edge of the drain-tosource
voltage, Vds, reaches zero prior to gate turn-on.
Thus represents a real zero voltage commutation,
which reduces the switching power losses.
630
Hah Dc bur

-i

PB-ZVS-PWM

convemx power atage.

Figure 9.1 shows the voltage ai: nodes A and B of the


bridge (referred to ground), in which the phase shift
can be seen. The corresponding primary transformer
voltage is shown in figure 9.2. Finally, the
transformer's primary current, i.5 shown in fig.10.

-40.0000 V I
-35.0000 U# -30.0000 YO
1.00 U8fdIV

&d&& Zem voltage commutation in Uie FB-ZVS-PWM convener,

1) V,

, and 2) V,

in S4.

re 9: Phase ahifi detail in the primary aide, 1) V, in S2, V, in

Finu s4, a d 3) Primary voltage.

tTi-II_I-1_Ll1.00 Y l i ~ l V
-40.0000 U0

Figure 10: Primary current in the FB-ZVS-PWM converter. 2


Mdiv

4.1 CRITICAL DESIGN CONSIDERATIONS


Since, it is impossible to exactly balance the positive
and negative volt-seconds across the transformer, it is
necessary to place a relatively large capacitor in series
with the primary. The capacitor C, is a blocking
capacitor to prevent any net DC voltage which
appearing across the transformer under unbalanced and
abnormal conditions and saturating it.
In the full-Bridge ZVS-PWM converter, the magnetizing
current has to be at certain level to facilitate ZVS when
the reflected load current to the primary is insufficient
to do so. For a given circuit design and output voltage,
the magnetizing current always has the same value at
the transition, no matter what is the input voltage [11.
The load current, however, can vary by large amount.
Therefore, to keep the sum of these current large
enough under ligth load conditions, it is necesary to
have a relatively large magnetizing current. The
magnetizing current can be abjusted by changing the
size of the transformer gap.
The mechanism by which achive a ZSV is different for
both legs of the bridg. For transistor S3 and S4, the
ZVS is provided by the resonance between the leakage
inductance, L., and the output capacitance of the
switch C,,,,. In order to ensure that S3 will turn-on with
zero voltage, a dead time is need between the turn-off
of S4 and turn-on of S3 to ensure that the MOSFET's
antiparallel diode conducts prior to turn-on of S3.
Knowing the elements that are involved in the process,
the dead time required to ensure the maximum possible
load range with ZVS can be determinate. The
resonance between L., C,, and C,, provides a
sinusoidal voltage across the capacitances that reaches
a maximum at one fourth of resonant period, as the
fallowing formula show.
Where C ,=C, + CTR
The full-bridge ZVS-PWM converter performance as a
baterry charger. It is used to charge sealed lead-acid
batteries. There are a variety of Charging methods
which can be used to charge batteries. In this case, the
constant voltage and limited current charging is the
method used. A constant voltage Charger permit to
restore batteries to a full charged condition in a short
63 1
period of time, and it does not permit to exceed
specified charge rates or charge voltages as the battery
is approaching a full charged condition. The charger
should have very stable output voltage and high current
capacity, as extremly large currents are allowed to flow
at the initial stage of charge.
In general, a commonly utilized constant voltage
charger has a device to limit initial current. The control
circuit for the FB-ZVS-PVVM Converter is based in the
ML4818 IC. This IC has i3 function that could performs
as limit current.
5. CONCLUSIONS
The need to comply with the appropiate EMC standards
in the European an American Market, is creating very
interesting research and development projects, related
with sophisticated control techniques and new power
topologies, which avoid the generation of high
magnitude low-order harmonics in the AC line voltage
and current waveforms.
This paper resumes the experimental results in the
implementation of a 1KW AC/DC Pre-regulator, using a
BOOST power topology as a PFC, and a Full-Bridge

-1S.0000 YO .JO.O~OO us

ZVS-PWM converter working as a DC bus conditioner


and battery charger. This prototype is part of a
Distributed Power Supply System (AC/DC preregulator),
which will be used in combination with
comercial DC/DC converters.
6. REFERENCES
1. R.Redl, N.Sokal and L.Balogh, A Novel SoftSwitching Full--Bridge DC/DC Converter: Analysis,
Design Consideration. and Experimental Results at
1.5Kw, 100 KHz. ", IEEE Power Electronics
Specialist Conf. Proc., 1990.
A New Sing/e
Phase AC to DC Zero Voltage Soft Switching
Converter -, IEEE Power Electronics Specialist Conf.
Proc., 1990.
3. F.Goodenough, Phase Modulation Cuts LargeSwitcher Losses ", Electronic Design, Abril 25,
1991.
4. R.Farrington, M.M.Jovanovic and F.C.Lee, "A New
Family of Isolated Zero-Voltage Switched Converters
", 9th Annual VPEC Power Electronics seminar,
Virginia Polytechnic Institute & State University,
Blacksburg, Virginia (1 991 ).
2. R.De Doncker and Venkataraman,
5. G.Hua, C.S.Leu and F.C.Lee, " Nove/Zero-VoltageTransition PWM Converters ", 9th Annual VPEC
Power Electronics Seminar, Virginia Polytechnic
Institute & State University, Blacksburg, Virginia
(1991).
6. Q.Chen, A.Lotfi and F..C.Lee, "Design Trade-offs for
An Off-Line ZVS-PWM Converter' 9th Annual VPEC
Power Electronics Seminar, Virginia Polytechnic
Institute & State University, Blacksburg, Virginia
(1991).
7. G.Hua and F.C.Lee, "UnOverviewofSoft-Switching
TechniGues for PWM Converters", 1 st International
Power Electronics Congress, CIEP'92, Cuernavaca,
8.
Mexico, Agosto 1992, pp. 73-90
J.A.Sabate, V.Vlatkovic, R.Ridely, F.C.Lee and

B. H . C ho ,

Design Considerations for High- Voltage

HighPower FcrllBridge NS-PWM Converter ", IEEE


Applied Power Electronics Conf. Proc.. 1990, pp.
275-284.
9. J.Sebastidn, J.Uceda, J.A.Cobos, J.Arau y
F.Aldana,

Imwovittg Power Factor in Distributed

Power SupprV Systems using PWM and ZCS-OR


SPK Topo/ogies ", IEEE Power Electronics
Specialist Conf. Proc., 1991.
H.L.Huy, J.P.Ferrieux and E.Toutain, " AnAC-DC
Converter with Low-Harmonics Input Current -,
EPE, pp.1201-1207. Proc. 1987.
1 1. L.H.Dixon Jr., -High Power Factor Preregulators
for Off-line Power Suppies", Unitrode Power
supply Design Seminar, pp.6.1-6.16, 1988.
12. "Sealed Lead-AcidBattedes technicalhandbook",
Panasonic , Co. Pp. 8-22.
Vower Factor Controler ML4812 Notes-, Micro
Linear, databook 1993, Pp 6-3 1,6-44.
10.
13.

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