Low-Voltage Bulk-Driven Self-Biased Cascode

Current Mirror using FD-SOI Technology

A Dissertation part II report submitted in partial fulfillment of the
requirements for the award of the degree of

MASTER OF TECHNOLOGY
IN
INFORMATION AND COMMUNICATION
TECHNOLOGY
(Specialization : VLSI Design)

Submitted by:

Mr. Umesh Jaiswal

Enrollment No. : 11/IEC/116
Supervised by:

Ms. Priyanka Goyal

Faculty Associate

SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY

GAUTAM BUDDHA UNIVERSITY, GREATER NOIDA-201 312,

GAUTAM BUDH NAGAR, UTTAR PRADESH, INDIA
May, 2016

SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY

GAUTAM BUDDHA UNIVERSITY, GREATER NOIDA, 201 312, U.P., (INDIA)

Candidates Declaration

I hereby certify that the work embodied in this dissertation (Part II) entitled Low-Voltage
Bulk-Driven Self-Biased Cascode Current Mirror using FD-SOI technology by Mr.
Umesh Jaiswal having Enrollment No. 11/IEC/116 in partial fulfillment of the requirements
for the award of the degree of M.Tech. in Information and Communication Technology (ICT)
with Specialization in VLSI Design submitted to the School of Information and
Communication Technology, Gautam Buddha University, Greater Noida is an authentic
record of my own work carried out under the supervision of Ms. Priyanka Goyal , School of
ICT. The matter presented in this dissertation has not been submitted by me in any other
University / Institute for the award of any other degree or diploma. Responsibility for any
plagiarism related issue stands solely with me.
Signature of the Student ____________________
This is to certify that the above statement made by the candidate is correct to the best of my
knowledge and belief. However, responsibility for any plagiarism related issue solely stands
with the student.
Signature of the Supervisor_____________________
Name with Designation______________________
Date:
Place: Greater Noida

MOS

METAL OXIDE SEMICONDUCTOR

CMOS

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

FG

FLOATING GATE

QFG

QUASI FLOATING GATE

BD

BULK DRIVEN

CM

CURRENT MIRROR

PIP

POLY POLY LAYER

OTA

OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

JFET

JUNCTION FIELD EFFECT TRANSISTOR

BJT

BIPOLAR JUNCTION TRANSISTOR

FD- SOI

FULLY DEPLETED SILICON ON INSULATOR

List of Abbreviations:

List of figures:
Figure
Fig.1

V-I characteristics of MOS Transistor

Page no.
10

Fig.2

Symbol of N-MOS and P-MOS

12

Fig.3

(a) MOSFET structure

13

(b) Regions in MOSFET

13

Fig.4

Current Mirror

15

Fig.5

Current to voltage converter

16

Fig.6

Voltage to current converter

17

Fig.7

BJT current mirror

18

Fig.8

MOSFET current mirror

18

Fig.9

Dynamic and leakage power consumption over time

19

Fig.10 Moores Law

20

Fig.11 Types of power

20

Fig.12 Techniques of low power design

21

Fig.13 Conventional MOS vs FD-SOI

23

Fig.14 Higher speed using less power

25

Fig.15 Power reduced using SOI

25

Fig.16 N-channel GD current mirror

28

Fig.17 (a) N-channel FG transistor

29

(b) N-channel FG Current mirror

Fig.18 (a) N-channel QFG transistor
(b) N-channel QFG CM
Fig.19 (a) N-channel BD MOS transistor
(b) Bulk driven Current Mirror
Fig.20 (a) N-channel BD-QFG transistor
(b) BD-QFG MOS Current Mirror
Fig.21 (a) BD Current Mirror
(b) Proposed Current Mirror
Fig.22 (a) Gate Driven CM
(b) Floating Gate CM

29
30
31
32
32
33

33
34
34
36
37

(c) Quasi-Floating Gate CM

37

(d) Bulk driven CM

37

(e) Bulk Driven QFG CM

38

(f) BD Cascode Form

38

(g) Final CM

38

Fig.23 Corner Window

39

Fig.24 ADE L

40

Fig.25 Setting Corner

41

Fig.26 Eldo Output Window

46

Fig.27 (a) Frequency response

48

(b) Input resistance

48

(c) Output resistance

49

BD VS PROPOSED CM
(d) Input Resistance

49

(e) Output Resistance

50

(f) Frequency response

50

(g) Transfer Characteristics

51

Table of Contents:
S.no
1.

2.

Content

Page no.

Introduction

1.1 Dissertation Preface

1.2 Motivation

1.3 Objective of work

1.4 Dissertation Organization

Theoretical Background

3.

2.1 Operation of Transistor

2.2 Current Mirror

14

2.2.1

Input stage to convert current to voltage

16

2.2.2

Output stage to convert voltage to current

17

2.2.3

Final circuit

17

2.3 Low Power Techniques

19

2.4 Low Power Technology

22

2.5 FD-SOI Technology

24

Design and Implementation (28nm)

26

3.1 Design

27

3.1.1

Design Technique

27

1. Gate Driven

27

2. Floating Gate Technique

28

3. Quasi-Floating Gate Technique

30

4. Bulk Driven Technique

31

5. Bulk Driven QFG Technique

32

6. Proposed Current Mirror

34

3.2 Implementation

36

Setting up corners

40

Eldo Simulation

41

Spice Netlist

42

Eldo Output

46

Simulation and Results

46

4.1 Results

47

5.

Conclusion

53

6.

References

55

4.

List of Tables:
TABLE.1

SMALL SIGNAL ANALYSIS RESULTS

PAGE.35

TABLE.2

COMPARITIVE ANALYSIS OF PERFORMANCE PARAMETERS

OF CURRENT MIRROR

PAGE.51

TABLE.3

BULK MOS VS FD-SOI

PAGE.52

TABLE.4

COMPARISON OF BULK, PD-SOI AND FD-SOI

PAGE.52

CHAPTER 1:
INTRODUCTION

1.1 DISSERTATION PREFACE

The demand for efficient portable electronic systems with high performance has
lead to the growth of low power circuits with high performance .The limitation
posed by lowering of geometry of devices is the threshold voltage of the MOS
transistor because the input supply voltage must be always equal to or greater than
threshold devices for the operation[1]. The lowering of the threshold voltage has
reached its limits so, it is necessary to have an alternative technique i.e. other than
conventional techniques to meet the industry demands. There may be many
methods that provide different advantages over the other and a trade- off must be
developed for application specific requirements like medical equipments, day-today life devices etc. For digital circuit realization, the rapid scaling has helped a
lot but in the case of analog circuit realization the lowering of device geometry
would not of much help. A current mirror is a basic building block whose function
is to copy or replicate the different biasing current required by other blocks in
integrated circuits technology [17]. To design efficient current mirror, different
techniques has been used like bulk driven (BD) [2], floating gate (FG) [4], quasifloating gate (QFG[3], bulk driven with quasi floating gate (BD-QFG)[2] first in
28nm technology which studies the effect only by lowering of the device
geometry and then these techniques are used in FD-SOI technology instead of
using the bulk MOS technology to study the effect of different technology[6]. The
FD-SOI technology has several advantages over the conventional technique
which is bulk MOS technique used to model the circuits like low power leakage,
fast switching speed, lower process variation effect etc[6]. At 20/28nm process,
the FD-SOI process is generally used replacing the bulk MOS technique. FD-SOI
stands for fully depleted silicon on insulator which means the region below the
gate is fully depleted of the charges when the FD-SOI transistors are in cut-off
state and hence, accounts for lower power leakage. It uses a silicon-insulatorsilicon substrate instead of silicon substrate to remove the parasitic device
capacitance and hence, increases the performance of the device. The FD-SOI
technology is designed by STMicroelectronics and Sony and all the necessary
1

libraries are provided by them only. The complete analysis has been carried out
by Cadence Virtuoso Schematic editor and Eldo simulator which is very accurate
analog simulator and the results are then compared with respect to different
technologies[6]. The techniques like bulk driven, floating and quasi-floating gate
have several advantages and disadvantages but the trade-off is maintained by to
get the desired functionality of the proposed design. The techniques are first
implemented individually in 28nm process and then the techniques are all
combined to derive a proposed design. Then, the techniques are implemented
using FD-SOI technology and then the comparative analysis shows whether the
bulk MOS technique is better or FD-SOI is better, out of the two technology.

1.2 MOTIVATION
The increasing market for consumer based portable equipments have always attracted
the major players worldwide to focus on the techniques that will revolutionize this
area and hence, here the need of low power, high performance efficient electronic
equipments comes into picture. Low power devices are very useful in medical
applications, automotive industry, military applications, industrial applications etc.
When lowering of supply voltage is done, threshold voltage of the MOS transistors
poses the biggest limitation because the supply voltage must be always equal or
greater than the threshold voltage for the operation of transistor.
The current mirror is one of the most basic building block in the integrated circuits
and its function is to copy the current fed to its input to other blocks at different
biasing levels as needed by the blocks. The reduction in power consumption is
achieved by placing the current mirror at one location and the current is supplied
throughout the circuit through this block. The most common example can be taken
from baising blocks in operational transconductance, op-amps, stabilization, current
amplification, active loading and level shifting.
The FD-SOI technology is very widely used at 20/28nm replacing the conventional
bulk MOS technology because of several advantages like low power leakage, faster
switching speed and no possibility for latch-up condition because every wall is
insulated with the insulator layer. The silicon on insulator is a manufacturing process
that is of two types: fully depleted and partially depleted. The fully depleted silicon
on insulator (FD-SOI) is a planar process technology which is widely used now-adays and in production also. This technology is also proved better than the Fin-fets in
variety of applications as it is susceptible to process variations. FD-SOI technology is
the only technology that doesnt alter the Moores Law and has best in class
speed/leakage trade-off. The technology used here is electro-static discharge protected
because this phenomenon sometimes leads to failure of the transistor and hence, have
this added functionality.

1.3 OBJECTIVE OF THE WORK

1. The main objective of this work is to realize our design using new technology and
techniques such that efficient low power portable system can be developed.

2. The design and implementation of each and every technique should be verified with
the results and the performance parameters be realized for every technique.

3. The performance parameters for every technique are then compared and the best
possible technique is given preference.

4. To ensure that the technology used will meet the industry requirements and will
provide the optimum results if scaled down further.

5. Using 28nm process in Bulk MOS technology and FD-SOI technology both will
ensure that further scaling down of device geometry is possible and ULSI can also
be achieved using this technology.

1.4 DISSERTATION ORGANIZATION

Chapter 1 of this dissertation deals with the dissertation preface and motivation
behind choosing this particular area as the area of research. It gives a brief
introduction about the topic and tells the scope of this topic in the further research.
This chapter describes the objectives of this dissertation.

Chapter 2 includes the theoretical background of the topic. It explores the topic in
detail and gives detailed information about the topic. It also includes many sub topics
that are related to the topic and explains them in the detail.

Chapter 3 deals with the designing and the implementation of the topic. It includes the
system and the software requirements needed for the implementation.

Chapter 4 discusses the result of the implementation. It discusses the graphs obtained
after the execution of the design and deals with them. It also deals with the
shortcomings of the method used and explains it.

Chapter 5 concludes the dissertation with the future scope of the topic.

LITERATURE SURVEY
[1] N. Raj, A.K. Singh and A.K. Gupta
A high performance, low voltage bulk driven cascode current mirror is proposed here.
The overall circuit performance gets increased by using the bulk driven technique
with quasi-floating gate technique. The small signal analysis of the circuit then
validates the advantage of the techniques used here. The proposed circuit has four
times smaller input resistance and extended bandwidth by about three times over the
same configuration using the conventional bulk mechanism. The circuit simulation is
done using HSpice tool in UMC 0.18m technology.
[2] F. Khateb, S. B. A. Dabbous, and S. Vlassis
This paper presents a detail on the technique used to achieve low power low voltage
driven circuits. The techniques used here are gate driven (GD), floating gate
technique (FG), Quasi floating gate (QFG), Bulk driven (BD) technique and then the
respective small signal analysis after the techniques are used in the circuit. The
techniques used bulk driven floating and quasi floating gate are combined to get the
high performance circuit delivering low power low voltage and then simulated using
UMC 0.18m technology with the help of HSpice simulator. The results shows that
the low voltage low power high performance circuits can be still possible using the
techniques and also provides the possibility of technology scaling.
[3] R. Gupta and S. Sharma
This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the
design of a low voltage current mirror and highlights its advantages over the floating
gate MOSFET (FGMOS). The use of resistive compensation has been shown to
6

enhance the bandwidth of QFGMOS current mirror. The proposed current mirror
based on QFGMOS has a current range up to 500@mA with offset of 2.2nA, input
resistance of 235@W, output resistance of 117k@W, current transfer ratio of 0.98,
dissipates 0.83mW power and exhibits bandwidth of 656MHz which increases to
1.52GHz with resistive compensation. in good agreement.
[4] S. Sharma, S. S. Rajput, L. K. Mangotra and S. S. Jamuar
This paper presents a high performance, resistively compensated low voltage current
mirror using floating gate MOSFETs (FGMOS).The compensation technique
desensitizes the output current and input compliance voltage with respect to the
process generated variations in the threshold voltages of the mirroring transistors..
The end results shows that high performance current mirror is designed using
FGMOS transistor and proves to be better than if conventional MOS in used. The
simulation has been carried out using PSpice simulator using 0.5m process and +/0.75V supply.
[5] F. Khateb, S. B. A. Dabbous, and S. Vlassis
Low power low voltage requirements in the integrated circuit technology has risen
sharply over the years. The battery operated devices reliability depends on various
factors from over-heating to regulated power. The non-conventional techniques such
as bulk driven(BD), floating gate(FG), Quasi-floating gate(QFG) pushed the supply
voltage near to the threshold voltage of the device. This paper presents the operation
principle, the advantages and disadvantages of each of particular techniques, enabling
circuit designers to maintain the trade-off between the techniques. Based on these
non-conventional techniques, three Operational transconductance amplifier with
supply voltage 0.4 V and the power consumption is 23.5 W.
[6] J.-L. Pelloie
Ultra low power electronics ensures the possibility of enhancing the portability
reliability and life time of the handheld and wireless devices .The low power
7

techniques cant only is sufficient for high performance devices and the need for
some alternative low power technology is the need of the hour. The technology used
here is a planar process technology with ultra-thin layer of insulator over the bulk of
the transistor which deliver small or negligible parasitic capacitance and can work at
sub-threshold voltage region near 0.3V with 97% reduction in switching energy as
compared to conventional techniques.

CHAPTER 2:
THEORETICAL BACKGROUND

2.1 OPERATION OF TRANSISTOR

MOSFET stands for metal oxide semiconductor field effect transistor which is
a majority carrier device and it is of two types: n-p-n and p-n-p. A mosfet is a
four terminal device having drain, source, gate and body as its terminal. It is
called as field effect device because the operation of transistor depends on the
voltage applied on the gate terminal. A n-p-n transistor have drain and source
terminal as n+ regions and bulk as p region. A p-n-p transistor have drain and
source terminal as p+ region and bulk as n region. The body terminal is tied to
the source terminal generally making the transistor as three terminal device and
by this method the body effect of the transistor is neglected. The voltages
applied at the terminals of the transistor is positive in the case of n-p-n
transistor and negative in the case of p-n-p transistor. The transistor that are off
at zero bias condition is called as enhancement type and that doesnt follow this
condition is called depletion type.
The transistor have generally three types of operating regions which is: cut-off,
triode or linear region and saturation region. The operation of the transistor
depends on the voltage applied at the gate terminal of the transistor and for the
transistor to work, the applied voltage must be always greater than or equal to
the some minimum voltage that initiates the channel formation between the
drain and the source terminal of the transistor. This voltage is termed as
Threshold voltage of the transistor ( V TH ). If the gate voltage is below the
threshold voltage of the transistor then, the transistor is in cut-off state that
means there will be no channel formation and no current will pass through the
transistor. We generally consider a nmos transistor because of some advantages
9

over the pmos transistor and the generalization is for the nmos only. For the
transistor to be working in the triode region or linear region, the drain-source
voltage must be smaller than the difference between the gate-source voltage
and the threshold voltage and for the transistor to be working in the saturation
region, the drain-source voltage must be greater than the difference between the
gate-source voltage and the threshold voltage of the transistor. The source is
taken as the reference for above stated conditions.
The conditions that were stated are as follows:
V gs <V th ,V th >0 , cutoff region (1)
V gs >V th ,V ds <V gs V th , triode regi on(2)
V gs <V th ,V ds V gs V th , saturationregion (3)
The equation for the current flowing through the transistor is as follows:
I ds = n

C ox ( V gsV th ) V ds

I ds =

n
2

V ds2
, linear regiontriode region (4)
2

C ox (V gs V th )2 , saturationregion (5)

10

Fig .1 V-I characteristics of MOS transistor

The useful terms associated with the transistor are:
Sub-threshold region When

V gs <V th

, theoretically there is no drain

current flowing through the transistor but practically some drain current flows
even when gate-source voltage is less than the threshold voltage of the device.
This is called sub-threshold region.
Channel length modulation When

V ds

is increased after a limit known as

saturation voltage then, the channel length of the transistor gets modulated and
as a result the drain current gets increased some modulation factor and this
phenomenon is called channel length modulation.
11

Punchthrough When

V ds

is increased after a certain limit the drain region

gets extended and grows towards the source region and as a result a nonuniform channel is made and the transistor conducts also when it is in cut-off
mode. This phenomenon is called as punchthrough.
Impact ionization When channel length is reduced by some factor then, the
electric field gets increased and as a result the electrons gets become hot while
gaining enough kinetic energy and dislodge the holes and appear as a substrate
current. This is impact ionization.
Body-effect The change in the threshold voltage of the transistor by
mismatch between the body and the source terminal of the transistor is termed
as body effect. If

V sb is zero then the body effect can be avoided so, we

short the terminals generally.

Drain-induced barrier lowering In shorter channel devices, the lowering of
the threshold voltages by increasing the drain current of the transistor is called
drain induced barrier lowering.
The above stated terms are the also called as second-order effects which effects
the performance of the transistor during operation. The parasitic capacitances
and other effects are also very common in shorter channel devices because of
the proximity of the elements inside a transistor.
The MOS transistor is the most common transistor used in the industry. It has
several advantages over other transistors like the BJT etc. It is most commonly
used in analog and digital circuits. The most common application of MOS
transistor is for switching and amplifying the electronic signals. The main
advantage of this is, it needs a very little current to turn on and drives much
higher current to a load.

12

Fig.2: Symbol for nmos and pmos.

The oxide layer used for insulation can be Si O2

or sapphire and depends

upon the type of application only. Generally, there are three regions in a
transistor and they are: accumulation, depletion and inversion.
Depletion With not so sufficient gate voltage, the charge carriers are scarcely
present near channel region and hence the valence region is driven far from the
Fermi level.
Inversion The inversion region is the region when there is much larger gate
voltage and the conduction band is near the Fermi level of the transistor and the
charge carriers are accumulated near the surface and the conduction is started.
Accumulation When there is negative voltage applied at the gate terminal, the
holes or positive charge carriers are attracted towards the negative voltage
applied at the gate and accumulates.

13

Fig.3 (a) MOSFET Structure

Fig.3 (b) Regions in MOSFET

14

2.2 CURRENT MIRROR

A Current Mirror is a circuit block whose function is to copy or replicate the
current in one active device to other active device. A very important feature of
the current mirror is its high output resistance which will keep the output
current constant regardless of load condition [17]. The current mirror also has
low input resistance which helps to keep the input current constant regardless
of the drive conditions. An ideal current mirror is simply an amplifier with a
gain equal to -1. The current mirror is used to provide the bias currents and
active load in subsequent amplifier stages [17]. The input signal is a current and
it gets converted to voltage and uses this voltage to control a current sink and
the output is a current sink. With the current sink as input, the input current is
converted to the voltage and then this voltage is used to control a current
source. So, a current mirror is composed of a current to voltage converter and
then connected to the voltage to current converter and the two converters can
have a linear relationship between the two.
Current mirrors are the basic building block in integrated circuits technology
because instead of using different current sources, a current mirror is fixed at
one location and then used to provide different biasing currents to different
blocks according to the requirements and this method save power and used
generally.
Current mirror is one type of current source capable of replicating current.
Load currents ( I L ) provided through current mirrors essentially do not
depend on the load, but are proportional to the reference current ( I REF ), i.e.
I L .K = K I REF . I REF

can be adjusted using an independent resistor R.

Current mirrors must use transistors whose properties match their own
properties. All transistors inside a current mirror have to work in their preferred
regions for smooth functioning. For BJT its the active region and for FET its

15

the saturation region, where the base-gate current/voltage is used to control the
amplified current/voltage. BJT in active region:
IC

) (e V BE 1 / V T

I S e V BE / V T

I CE 1 / I CE 2 = ( I S 1 / I S 2

/ e V BE 2 / V T ) (6)

when Q1 is the same as Q2 :

I CE 1 / I CE 2 = e ( V BE 1V BE 2 )/ V T

(7)

When biasing is the same:

I CE 1 / I CE 2 =
if Q1 = Q2 then

I S 1 / I S 2 (8)
I CE 1 /

I CE 2 (9)

FET in saturation region:

I ds =

n
2

C ox (V gsV th )2

(10)

When biasing is the same:

I ds1 / I ds2

K1 / K2

I ds2 (11)

16

if FET1 = FET2 then

I ds1

Fig.4 Current Mirror[17]

The above figure shows a basic current mirror with transistors

Q1 , Q2 ,Q3

and a reference current which is replicated at the output node. The current
mirror have some gain with which it also amplifies the reference current.
2.2.1 INPUT STAGE TO CONVERT CURRENT TO VOLTAGE
A configuration where an active element of choice, a transistor, works as the desired
current-to-voltage converter. However, the transistor is a unidirectional device, in the
case of BJT the

V BE controls the collector current flowing through the circuit and

for the FET, the

V GS

controls the drain current. Producing the opposite where the

V BE

is not possible in the device that uses common emitter

IC

controls

amplifier. The best way possible is to use negative feedback for it. In this case
V BE V GS

needs to be adjusted, so that the collector or drain current is

=(

V 1 - V BE )/R. For this case, we simply connect the collector to the base or gate to
drain. The result is 100% parallel negative feedback. As a result, with this reversed
transistor, the

I C (collector current) serves as the input quantity while the

V BE 1

(base-emitter voltage) serves as the output quantity with a logarithmic transfer

17

function. The input node of the current mirror using BJT is just a bipolar transistor
with 100% parallel negative feedback. Similarly, a diode connected enhancement
mode MOSFET (gate tied to drain) will serve as a similar I-V converter with

V GS

(gate-source voltage) as the output quantity rather than V BE (base-emitter voltage).

Fig.5 Current to Voltage Converter [17]

2.2.2 OUTPUT STAGE TO CONVERT VOLTAGE TO CURRENT
A bipolar junction transistor can be driven by a voltage or by a current. If we consider
the

V BE (base-emitter voltage) as the input and the

I C (collector current), as the

output, we can think of a transistor as a non-linear V-I converter having an

exponential characteristic. The base can be directly found out using voltage output of
the I-to-V converter in the input stage of the current mirror. The collector provides the
output terminal of the current mirror: The output V-I converter stage of the simple
current mirror is just a transistor acting as a non-linear (exponential for BJT) V-I
converter and if a FET were used for the input stage, the output stage will be a MOS
transistor in which gate serving as the voltage input and the drain serving as the
current output.

18

Fig.6 Voltage to Current Converter [17]

2.2.3 FINAL CIRCUIT
In the final circuit the previous two stages are combined such that the output of the
first stage is connected to the input of the second stage i.e. the base-emitter junction
of Q1 is connected to the base-emitter junction of Q2. The I-V part i.e. input part is
connected to the V-I part of the circuit to get the final circuit.

Fig.7 BJT Current Mirror

19

Fig.8 MOSFET current mirror

Factors affecting the output of current mirrors:
1. Mirror Gain
2. Incremental output resistance
3. Voltage drop across the output.
4. Output compliance
5. Temperature stability
6. Frequency response

2.3 LOW POWER TECHNIQUES

The progress of silicon process technology grows on relentlessly as more and
more number of components are getting integrated on a chip. The number of
transistors on a chip gets doubled every 2 years and this growth shows how the
Moores Law has been violated over the years. The success in engineering has
evolved new industries such as personal computers with the peripherals,
20

consumer electronics and revolutionized other industries also with them. The
problem associated with finding the techniques for the improvement in this
industry is that technical challenges are overcome by many resources and the
problem becomes more troublesome when most of the devices are battery
powered and hence, they require less power and durability in order to get
succeeded.
Low power consumption is directly linked to the operating duration of the
device and hence, low power consumption is focused in each of the battery
powered devices while achieving high performance. The reduction in power is
also directly linked to the device success and hence, it is considered very
critical now a days. The power consumption of devices are dependent on many
factors and it is of two types: dynamic power and static power.

Fig.9 Dynamic and Leakage power consumption over time

The dynamic power is due to the charging and discharging of the capacitor
during switching and accounts to nearly 30% of the total power dissipation.
Static power is the power when there is no circuit activity and it accounts to
15-20% of the total power dissipation.

21

Leakage power is the power leaked from the device during operation and when
the device was in off mode.
Short circuit power dissipation is the power dissipation when there is a short
circuit path between the supply and the ground terminal.

Fig.10 Moores Law

Fig.11 Types of power

22

Fig.12 Techniques of low power design

All these techniques shown in the figure are widely used for low power
consumption depending upon the end to end product. The biggest limitation is
posed by the threshold voltage of the transistor because in lowering the supply
voltage there is a limitation on it. The supply voltage must be always equal to
or greater than the threshold voltage of the transistor.
The low power techniques is widely focused because low power consumption
directly relates to the success of the product and durability increases as it matter
the most in battery powered devices. With scaling down of device geometry,
second order effects also come into place and hence, the trade-off is needed
between the techniques in order to get optimal performances.

2.4 LOW POWER TECHNOLOGIES

23

The conventional techniques used for low power devices are lowering the supply
voltage but the threshold voltage of the devices limits this possibility in high scale
of

integration

in

devices.

The

conventional

techniques

suffer

low

transconductance and also experience lower bandwidth and in nanometer scaling

level the conventional techniques also suffer short channel effects which also
results in offset, low gain stages with decreased impedance etc.
Integrated circuit (IC) technologies leap towards lowering of the minimum feature
size of MOS transistors, and thus more electronic components per unit area are
achieved. However, increasing the device density of the IC means in its turn
higher power dissipation along with overheating. Hence it is very useful to
decrease the power leakage in the integrated circuits to ensure device
functionality as well as reliability of low voltage and low power operation could
be obtained either by new technologies or by design techniques. The main
advantages and disadvantages of the low voltage and low power technologies and
some of the most popular techniques are discussed; three main technologies are
used for low-voltage and low-power IC design:
1. Bi-CMOS technology is a very advanced semiconductor technology, which
combines bipolar junction transistor (BJT) and CMOS transistor in a single
integrated circuit, and combines the advantages of both transistor types. This
technology enhances speed over purely bipolar technology, offers lower
power dissipation over purely CMOS, high analog performance, smaller size
and more reliable Integrated circuits. However, this technology requires much
extra fabrication steps which will eventually increase the process cost.
2. SOI (Silicon on insulator) technology: In this technology, a layer of silicon
dioxide ( SiO 2 ) is implanted below the surface by the oxidation of Si or by
oxygen implantation into Si. The insulation provided by the oxide layer which
is called buried oxide (BOX) helps to remove the parasitic capacitances, and it
will improve the performances of the device. This technology offers ideal
24

device isolation and smaller layout area, high switching speed and lowerpower consumption. However, fabrication of this technology is more costlier
and also higher self-heating because of poor thermal conductivity of the
insulator and as a result we can also use different oxide material for this but it
is dependent on the end to end application of the device. But at 28/20nm node,
this technology is much preferred and this technology also removes the
possibility of the latch-up during operation because of the insulating walls and
no direct connection between the supply and the ground is established.
3. CMOS Technology: Complementary metal oxide field effect transistor is a
combination of both pmos and nmos working as pull up and pull down
network. CMOS technology is used in fabrication of conventional microchip
and it has several advantages over Bi-CMOS and SOI technology in terms of
performance, lower power dissipation and good switching speed. CMOS
technology is also easy to fabricate and this trend is widely used in industry.
4. FinFET Technology: FinFET technology is a result of extreme level of
integration which is the result of components that doubles every 2 years. The
name fin comes in this because when viewed it looks like the set of fins in
FinFET structure. FinFET has a conducting channel that is wrapped around
the fin and the thickness of it determines the channel width and length. The
structure of FinFETS typically has a vertical fin over a substrate which works
between a larger drain and source area. This is aligned vertically above the
substrate as a fin.The FinFETs removes the possibility of short channel
effects with deep sub-micron size transistors. The advantage associated with
the improved structure of FinFETs is that it offers much lower power
consumption and it can operate at much lower power supply. It was earlier
supposed to be limited until 20nm node but the even further scaling can be
achieved and static leakage current gets reduced by 90% and the speed of
operation gets reduced by approximately 30% of the non-FinFET versions.

2.5 FD-SOI TECHNOLOGY

25

FD-SOI technology is a type of silicon on insulator technology which involves

the use of silicon-insulator-silicon substrate to help reduce the shorter channel
effects in place of silicon substrate in the bulk MOS technology. FD-SOI stands
for fully depleted silicon on insulator and it refers to a planar transistor
architecture which the industry wants to achieve over the decade and it has a
very thin silicon layer on the insulator layer and this technology provides less
power, performance and smaller chip area at very competitive cost.
The implementation of FD-SOI technology is one of the leading manufacturing
strategies which allows the continued miniaturization of microelectronic
devices extending the Moores Law.

Fig.13 Conventional MOS vs FD-SOI

The advantages of SOI technology over the bulk MOS technology is:1. With the isolation from the bulk silicon, lower parasitic capacitance.
2. Due to complete isolation of n and p well structures, no latch up condition.
3. Can operate at much lower power supply.
4. No doping, so no temperature dependancy.
5. Higher density and wafer utilization.
6. Lower leakage current with better switching speed.
7. Reduced antenna issues and suitable for 28/20nm node.
26

Fig.14 Higher speed using less power

Fig.15 Power reduced using SOI

27

CHAPTER 3:
DESIGN & IMPLEMENTATION

28

3.1 DESIGN
In this report, a current mirror is proposed with some design techniques along with
the technologies used for obtaining a low power bulk driven self-biased cascode
current mirror using FD-SOI technology.
The first step in designing the current mirror is to come up with different techniques
and studying the effect of the technique in terms of the performance of the current
mirror. The parameters of the current mirror like gain, input resistance, output
resistance, power consumption, bandwidth, voltage supply, impedance etc. are
calculated by each technique implemented.
The design of the current mirror is resolved after achieving a trade-off between the
techniques and the design is first implemented using the conventional bulk MOS
technique in 28nm feature size and then the design is implemented using different
technology which is better in terms of performance than bulk MOS technology.
3.1.1 DESIGN TECHNIQUES
1. GATE DRIVEN TECHNIQUE:
The conventional gate driven technique is a technique used for simple current mirror
in which the gate is driven by the same power supply to that of drain and the output is
taken directly through the drain of another transistor. The drain-source voltage is
equal to the gate-source voltage and hence, the input part transistor is in saturation
region and some current will pass through the transistor at the input side and therefore
working as I-V converter. The output is taken from the transistor at the output side
which works as V-I converter.
1
R
=
,
GD
Input Resistance,
gm 1 + gds 1
Output Resistance, Rout =g ds2

29

(13)

(12)

2 C gs 1,2
g
s+
Current Gain,
gm2
2C gs 1,2
A I ,GD =

gm 1,2
Dominant Pole, s GD= 2 C gs1,2

(14)

(15)

Fig.16 N-channel GD current mirror [1]

2. FLOATING GATE TECHNIQUE:

With the floating gate technique, the design can work at much lower power
supply and the advantage is that the input coupling capacitor divider results in
attenuation of the input signal and increases the linearity.
We can see the architecture of N-channel FGMOS in the fig.13, the floating
potential of gate M1 under the DC analysis and the input capacitance formed by
the second layer of poly-silicon over poly layer of the gate and it is called as (PIP)
capacitor. The floating gate charge is given by:

30

V FG =

The trapped charge

Q0

1(CV + CGS V S +C GD V D + CGB V B +Q 0 )

CT

(16)

and the input gate voltage attenuation are the main

obstacles with this technique.

Fig.17(a) N-channel FG Transistor [3]

Input Resistance,

R, FG =

1
kgm 1 + gds 1,FG

Output Resistance, Rout , FG=g ds2, FG

C 2 C gs1,2
kg
s+
Current Gain,
k gm 2
C 2 C gs1,2
A I , FG=

K g m 1,2
Dominant Pole, s FG = C 2 C gs 1,2

31

(17)

(18)

(19)

(20)

Fig.17 (b) N-channel FG current mirror [3]

3. QUASI-FLOATING GATE TECHNIQUE:

The Quasi-floating gate technique utilizes the property of capacitor divider to get
more enhanced characteristics while designing low power current mirror with the
only difference which lies in conversion of floating gate by placing a large valued
resistor

Rlarge

which is realized by reverse-biased p-type MOS transistor

which operates in cut-off region and hence drives no current and hence, works as
a large valued resistor. FGMOS and QFGMOS technique have lower
transconductance and transient frequency as compared to GD approach but it is
very useful to design transconductor, filter, operational transconductor amplifier,
Gm-c filter etc.

V QFG=

1(CV +C GS V S +CGD V D +C GB V B +Q0)

1+ s Rlarge CT

32

(21)

Fig.18 (a) N-channel QFG transistor [4]

Input Resistance,

R, QFG=

1
k 1 g m 1+ g ds ,QFG

Output Resistance, Rout ,QFG =gds 2,QFG

(22)

(23)

C 2 C gs1,2 +C gd , MP
k1 g
s+
Current Gain,
k 1 g m 1,2
C 2 C gs1,2 +C gd ,MP
A I , FG=

k 1 gm 1,2
s
=
QFG
Dominant Pole,
C 2C gs 1,2 +C gd , MP

33

(24)

(25)

Fig.18 (b) N-channel QFG current mirror [4]

4. BULK DRIVEN TECHNIQUE:

In a bulk driven technique, the transistor being a four terminal device in which
bulk terminal is connected to either the positive supply or the negative supply for
N-channel or P-channel transistor respectively and by connecting the bulk to the
signal input instead of connecting to the source terminal or the supply, the
threshold voltage limitation can be removed. This technique have small body
transconductance and transient frequency and it is also very sensitive to the
process variation and device mismatch and hence, it creates stability issues during
positive feedback.

gm=n g m
2 f V SB

gmb= 2

(26)

where is the body effect coefficient, f is the Fermi-potential and V SB is the

source-bulk voltage.
Input Resistance,

R, BD =

1
gmb 1 + gds 1, BD

Output Resistance, Rout , BD=g ds2, BD

2 C sb1,2
g
s+
Current Gain,
gmb 2
2 C sb1,2
A I , FG=

34

(29)

(28)

(27)

gmb 1,2
s
=
BD
Dominant Pole,
2C sb 1,2

(30)

Fig. 19(a) N-channel BD MOS transistor [5]

Fig. 19(b) Bulk driven Current Mirror [5]

5. BULK-DRIVEN QUASI FLOATING GATE TECHNIQUE
In BD-QFG technique, both the properties of bulk-driven and quasi-floating gate
technique are combined to get high performance design of current mirror. The
small signal characteristics like transconductance and bandwidth are enhanced
and this technique is very useful for battery operated portable devices as it
requires much lower power supply and also prevents latch-up during operation. It
work as a simple BD technique under DC conditions and in the case of AC
conditions, it works as an BD and QFG technique both. This technique is
generally used for current conveyor and many such circuits.

35

Fig. 20(a) N-channel BD-QFG transistor [5]

Fig. 20(b) BD-QFG MOS CM [5]

1
R
=
,
BDQFG
Input Resistance,
k 1 gm1 +gmb 1 +gds 1,BD
Output Resistance, Rout , BDQFG=g ds2, BD

36

(32)

(31)

k
( 1 gm1,2 + gmb 1,2 )
C 1,2 2 C gs1,2 +2 C sb 1,2+ 2C gd , MP
Current Gain,
k 1 gm 2 + gmb 2
C 2 C gs1,2 +2 C sb 1,2+ 2C gd , MP
A I , FG= 1,2

s+

k 1 g m 1,2+ g mb 1,2
Dominant Pole, s BD QFG = C 1,2 2 C gs 1,2+ 2C sb 1,2 +C gd , MP

(33)

(34)

6. FINAL CURRENT MIRROR

The schematic is shown in Figs.1 a and b .The proposed CM

contains four bulk driven N-channel electro-static discharge
protected FD-SOI transistors and two of them are configured as
QFG with their bulk terminal tied to their gate inputs. The
transistors MP1 and MP2 which are P-channel transistors, along
with capacitors C1 and C2 respectively form the QFG for
transistors M3 and M1. The transistors M4 and M2 are simple BD
with their gate tied to the supply at this terminal. The resistance
R plays the role of reducing the minimum output voltage so that
the transistors M2 and M1 are kept in saturation, this improves
the output voltage swing. Current is used to overcome the
current mismatch effect which caused by the effect of non-linear
behavior of transistors at much lower power supplies and this
current is in order of few micro amperes.

37

Fig. 21 (a) BD CM (b) Proposed CM [5]

With the small signal analysis of Fig.1b, calculating bandwidth
I out
I

AI =

gm4 ( k g m 3+ g mb 3 )
gm 4
s +(
)
C gs 4
C gs 4 ( C sb1 +C sb 3 )
gm 2 ( k g + gmb 1 )( g m4 + s C gs 4 )

C gs 4 ( C sb1 +C sb 3 )( g m 2+ s C gs 2 ) s2 +

(35)

m1

AI =

gm 2 ( k gm 1 + gmb 1 )
gm 2
) s +(
)
C gs2
C gs2 ( C sb 1+C sb 3 )
g m2( k g + gmb 1 )

C gs 2 ( C s b 1 +C sb3 ) s 2+(

m1

38

(36)

I out
I

In equation (1), k is the effective capacitance ratio of input to the total capacitance
seen at the QFG of M3 and M1.It is assumed that M3, M1 are matched and M4,
M2 are matched,
i.e.

gm 2=gm 4 ; g m 3=gm 1 ; g mb 1=gmb 3C gs 2=C gs 4

0,
=

gm 2 ( k g m 1+ g mb1 )
C gs 2 (C sb1 +C sb 3)

(37)

From (2) and (3),it can be seen that by replacing M5 and M6 in Fig.1a by QFG
based MOS transistors M3 and M1, effective transconductance is increased from
gmb 1 (kg m 1+ g mb1 ) and hence, the bandwidth is increased.
Small signal analysis of Fig. 21(a) for input and output resistances shows that
input resistance is inversely proportional to the transconductance of M6, whereas
the output resistance is strongly dependent on M8, and thats why the effective
increase in transconductance in Fig.21(b) makes the input resistance very low.
The small signal results are shown in the Table 1. There is some slight variation in
output resistance because of the adverse effect by the increased conductance of
M1.
Table 1: Small signal analysis results
Techniques

BD CM (Fig.1a)

Input resistance
R+

Output resistance

Bandwidth(

gm 8 + gmb 8

PROPOSED CM(Fig. 1b)

1
g mb5

ro 6 ro 8

g m 8 gmb 6
C gs 8 (C sb 5+C sb 6 )

39

R+

1
Kgm 3 + g mb3
gm 2 + gmb 2

r o 1,qfg r o 2
kg mb 6+ g mb 1

gm 2

The design is first implemented using conventional bulk MOS technology and
then, the design is implemented using FD-SOI technology and then, the results are
compared and the best technique with best technology is chosen considering the
results.

3.2 IMPLEMENTATION
All the designs are implemented using bulk MOS technology first and then all
these designs are implemented using FD-SOI technology in 28nm node in both
the cases. This technology is considered as costly in terms of fabrication but when
it comes to 28/20nm node then, this technology is considered.
1. STEP 1: RUNNING THE SETUP

2. STEP 2: CREATING THE SCHEMATIC USING CADENCE VIRTUOSO

EDITOR

40

Fig.22 (a) Gate-Driven CM

(b) FG CM

(c) QFG CM
41

(d) BD CM

(e) BD-QFG CM

(f) BD Cascode Form

42

(g) Proposed CM
The schematic of all the designs first use the conventional MOS transistors in the
design in 28nm process and then, it uses the esdeglvtnfet_b (electrostatic
discharge protected FD-SOI transistor) in 28nm process.
The term esdeglvtnfet_b means the transistor is electrostatic discharge protected
which means the transistor cant be susceptible to the effect of transistor
breakdown when electrically charged particle are in contact with each other and
hence, provides better protection as compared to normal transistors. lvt means
low voltage transistor and this transistor is specially designed for low voltage
applications and hence, it has lower threshold and can work at low voltage supply.
3. RUNNING SIMULATIONS
Launching Analog Design Environment

43

Fig.23 Corner Window

SOFTWARE TOOL REQUIREMENTS- ELDO Simulator, Cadence Virtuoso

Schematic Editor and cadence spectre.
OPERATING SYSTEM REQUIREMENTS- UNIX, Linux.
The DC and AC simulations are performed to get transfer characteristics,
frequency response, input and output resistance curves and parameters like power,
bandwidth, gain are calculated using calculator tool in virtuoso.

SETTING UP CORNERS
44

Fig.24 ADE L

45

Fig. 25 Setting corners

ELDO SIMULATION
Mentor Analog Simulators
The views associated with the analog simulation using mentor tools are Design
Architect-IC (DA-IC) and the second one is the one involving the direct
invocation of the simulator. If starting from the within the DA-IC, there are two
parts of the analog simulation environment which is the simulation kernel (or
engine) that is Eldo and the other user interface within DA-IC. Eldo is the type of
simulator that uses the same netlist format and its options are same to that of the
SPICE simulator. The user interface within the DA-IC creates a netlist file and a
46

control file and also writes the results of simulation to the disc and after the
simulation has been finished then, plotting the results in EZwave to view the
results which is also specified by the results. DA-IC is customized for IC design
and thats why the schematics drawn doesnt need off the shell logic or
transistor components. It also has the dedicated user interface for creating and
modifying the the netlist and control files that are much needed during the
simulation and while writing the results in the disc.

SPICE NETLIST
The circuit simulation programs didnt have any graphical user interface type of
functionality and in the past, complex set of commands and statements were
written in the text editor itself and these command were part of the netlist to fully
describe the circuit, circuit components and the type of simulation and calculating
the parameters associated with the circuit. During the start of the simulation, the
simulator engine will read the netlist file as part of the input and extracting all the
information regarding simulation from this netlist. All the necessary information
regarding the simulation is specified in the netlist with basic design elements as
the subcircuit that acts as the sub-routine in normal programming and likewise the
subcircuit can also be used more than one more time in the input netlist file.
1. Eldo syntax netlist files are not case sensitive.
2. Lines beginning with an asterix-* specifies the comment.
3. The subcircuit names are synonyms to their functionality generally and hence,
easy to use in the design.
4. The Eldo files are generally in the format of .cir, .spi etc.
5. The spice netlist specifies the connection of the terminals and the subsequent
sub-circuit definition is also needed where the sub-circuit level of netlist is
defined with all the connection of the terminals.
47

48

49

ELDO OUTPUT
50

Fig.26 Eldo Output Window

51

CHAPTER 4:
SIMULATION RESULTS

4.1 RESULTS

52

Fig.27 (a) Frequency Response

(b) Input Resistance

53

(c) Output Resistance

BD VS PROPOSED CM

(d) Input Resistance

54

(e) Output Resistance

(f) Frequency Response

55

(g) Transfer Characteristics

Table 2. Comparative analysis of Performance metrics of CM

TECHNIQUE

INPUT()
RESISTANCE

OUTPUT(k)
RESISTANCE

BANDWIDTH(MHz)

GD

280

1.12

78

58.8

FG

122

1.18

54

52.2

QFG

120

0.50

47

41.4

BD

22

0.42

156

16.8

BD-QFG

17.98

0.4

225

12.3

Table.3 BULK MOS VS FD-SOI

PARAMETERS

FD-SOI

56

BULK MOS

POWER(W)

Supply(V)

0.3

0.3

Input Range(A)

0-200

0-200

Input Resistance (k)

0.8

7.34

Output Resistance (k)

27.24

16.62

65

26

0.3

11.12

28nm

28nm

Bandwidth(MHz)
Minimum output
voltage(mV)
Technology

Table.4 COMPARISON OF BULK, PD-SOI AND FD-SOI

57

CHAPTER 5:
CONCLUSION

The conclusion of this work suggests on the fact the low power design
methodologies are still possible in nanometer scale and further. The 35% decrease
58

in total power dissipation in FD-SOI technology as compared to bulk MOS

technology have clearly indicated

towards

the possibility of usage of this

technology in further lower geometries at production scale.

FD-SOI technology along with low power design techniques to the basic building
block i.e. current mirror have shown that the performance parameters getting
increased and only the bandwidth is effected while implementing it in 28nm
technology.
The electrostatic discharge protected, low voltage transistors of FD-SOI
technology also provides the necessary protection, if the transistor comes in
contact with other charged devices.
All the low power techniques manufactured in classical Bulk CMOS technology
can be directly shifted to FD-SOI. Body biasing is the special case which can be
efficiently adapted to FD-SOI using ultra-thin BOx wafers. The threshold voltage
adjustment can also be adjusted using doping concentration but here in FD-SOI
no, doping is eliminated and hence, it is advantageous in this aspect.
FD-SOI technology have better electrostatic control over the FinFETs and thats
why the planar technology is considered over other aspects.
FD-SOI technology applications can be extended to markets such as:1. The range is from high performance, low power SoC to ultra-low power
applications.
2.

Mobile Internet Devices (Smartphones, Tablets, Netbooks ).

3. Imaging (Digital Camera, Camcorders), Cellular Telecom, Mobile

Multimedia, Home Multimedia (Set Top Box, TV, Automotive Infotainment).

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61