CH 04

Chapter 4
Wafer Manufacturing
and Epitaxy Growing
Hong Xiao, Ph. D.
hxiao89@hotmail.com
Hong Xiao, Ph. D.
www2.austin.cc.tx.us/HongXiao/Boo
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Objectives
Give two reasons why silicon dominate

List at least two wafer orientations
List the basic steps from sand to wafer
Describe the CZ and FZ methods
Explain the purpose of epitaxial silicon
Describe the epi-silicon deposition process.
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Crystal Structures
Amorphous
No repeated structure at all
Polycrystalline
Some repeated structures
Single crystal
One repeated structure
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Amorphous Structure
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Polycrystalline Structure
Grain
Boundary
Grain
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Single Crystal Structure
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Why Silicon?
Abundant, cheap
Silicon dioxide is very stable, strong
dielectric, and it is easy to grow in thermal
process.
Large band gap, wide operation temperature
range.
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Name
Silicon
Symbal
Si
Atomic number
14
Atomic weight
28.0855
Discoverer
Jns Jacob Berzelius
Discovered at
Sweden
Discovery date
1824
Origin of name
From the Latin word "silicis" meaning "flint"
Bond length in single crystal Si
2.352
Density of solid
2.33 g/cm3
Molar volume
12.06 cm3
Velocity of sound
2200 m/sec
Electrical resistivity
100,000 cm
Reflectivity
28%
Melting point
1414 C
Boiling point
2900 C
Hong Xiao, Ph. D.
Source:
http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html
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Unit Cell of Single Crystal Silicon

Si
Si
Si
Si
Si
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Crystal Orientations: <100>

z
<100> plane
y
x
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10

z
<111> plane
<100> plane
x
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z
<110> plane
y
x
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<100> Orientation Plane

Basic lattice cell
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Atom
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<111> Orientation Plane

Basic lattice cell
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Silicon atom
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<100> Wafer Etch Pits
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<111> Wafer Etch Pits
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Illustration of the Defects

Impurity on substitutional site
Silicon Atom
Impurity in
Interstitial Site
Silicon
Interstitial
Vacancy or Schottky Defect

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Frenkel Defect
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Dislocation Defects
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From Sand to Wafer
Quartz sand: silicon dioxide

Sand to metallic grade silicon (MGS)
React MGS powder with HCl to form TCS
Purify TCS by vaporization and condensation
React TCS to H2 to form polysilicon (EGS)
Melt EGS and pull single crystal ingot
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From Sand to Wafer (cont.)
Cut end, polish side, and make notch or flat

Saw ingot into wafers
Edge rounding, lap, wet etch, and CMP
Laser scribe
Epitaxy deposition
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From Sand to Silicon

Heat (2000 C)
SiO2
Sand
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C
Carbon
Si
MGS
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CO2
Carbon Dioxide
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Silicon Purification I
Hydrochloride
Si + HCl
TCS
Reactor,
300 C
Silicon
Powder
Condenser
Filters
Purifier
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Pure TCS with

99.9999999%
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Polysilicon Deposition, EGS

Heat (1100 C)
SiHCl3
TCS
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H2
Hydrogen
Si
EGS
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3HCl
Hydrochloride
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Silicon Purification II
H2
Process
Chamber
EGS
H2 and TCS
Liquid
TCS
TCS+H2EGS+HCl
Carrier gas
bubbles
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Electronic Grade Silicon
Source: http://www.fullman.com/semiconductors/_polysilicon.html
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Crystal Pulling: CZ method

Single Crystal Silicon Seed
Quartz Crucible
Single Crystal
silicon Ingot
Molten Silicon
1415 C
Heating Coils
Graphite Crucible
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CZ Crystal Pullers
Mitsubish Materials Silicon

Source: http://www.fullman.com/semiconductors/_crystalgrowing.html
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CZ Crystal Pulling
Source: http://www.fullman.com/semiconductors/_crystalgrowing.html
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Floating Zone Method

Poly Si
Rod
Heating Coils
Movement
Molten Silicon
Heating
Coils
Single Crystal
Silicon
Seed Crystal
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Comparison of the Two Methods

CZ method is more popular
Cheaper
Larger wafer size (300 mm in production)
Reusable materials
Floating Zone
Pure silicon crystal (no crucible)
More expensive, smaller wafer size (150 mm)
Mainly for power devices.
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Ingot Polishing, Flat, or Notch
Flat, 150 mm and smaller

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Notch, 200 mm and larger
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Wafer Sawing
Coolant
Orientation
Notch
Crystal Ingot
Saw Blade
Ingot
Movement
Diamond Coating
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Parameters of Silicon Wafer
Wafer Size (mm)

50.8 (2 in)
76.2 (3in)
100
125
150
200
300
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Thickness (m)
279
381
525
625
675
725
775
Area (cm 2)
20.26
45.61
78.65
112.72
176.72
314.16
706.21
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Weight (grams)
1.32
4.05
9.67
17.87
27.82
52,98
127.62
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Wafer Edge Rounding

Wafer
Wafer movement
Wafer Before Edge Rounding
Wafer After Edge Rounding

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Wafer Lapping
Rough polished
conventional, abrasive, slurry-lapping
To remove majority of surface damage
To create a flat surface
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Wet Etch
Remove defects from wafer surface
4:1:3 mixture of HNO3 (79 wt% in H2O),
HF (49 wt% in H2O), and pure CH3COOH.
Chemical reaction:
3 Si + 4 HNO3 + 6 HF 3 H2SiF6 + 4 NO + 8 H2O
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Chemical Mechanical Polishing

Pressure
Slurry
Wafer
Wafer Holder
Polishing Pad
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200 mm Wafer Thickness and

Surface Roughness Changes
76 m
After Wafer Sawing
914 m
76 m
914 m
After Edge Rounding
After Etch
12.5 m
814 m
<2.5 m
750 m
After CMP
Virtually Defect Free

725 m
After Lapping
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Epitaxy Grow
Definition
Purposes
Epitaxy Reactors
Epitaxy Process
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Epitaxy: Definition
Greek origin
epi: upon
taxy: orderly, arranged
Epitaxial layer is a single crystal layer on a
single crystal substrate.
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Epitaxy: Purpose
Barrier layer for bipolar transistor
Reduce collector resistance while keep high
breakdown voltage.
Only available with epitaxy layer.
Improve device performance for CMOS and

DRAM because much lower oxygen,
carbon concentration than the wafer crystal.
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Epitaxy Application, Bipolar

Transistor
Emitter
p+
n+
Base
Collector
AlCuSi
SiO2
n+
n-Epi
p+
Electron flow
n+ Buried Layer
P-substrate
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Epitaxy Application: CMOS

Metal 1, AlCu
W
STI
BPSG
n+
n+
P-Well
USG
p+
p+
N-Well
P-type Epitaxy Silicon

P-Wafer
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Silicon Source Gases

Silane
SiH4
Dichlorosilane
DCS
SiH2Cl2
Trichlorosilane
TCS
SiHCl3
Tetrachlorosilane
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SiCl4
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Dopant Source Gases

Diborane
B2H6
Phosphine
PH3
Arsine
AsH3
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DCS Epitaxy Grow, Arsenic Doping

Heat (1100 C)
SiH2Cl2
DCS
Si
Epi
2HCl
Hydrochloride
Heat (1100 C)
AsH3
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As
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3/2 H2
46
Schematic of DCS Epi Grow and

Arsenic Doping Process
SiH2Cl2
AsH3
H2
HCl
Si
AsH3
As
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Epitaxial Silicon Growth Rate Trends

Temperature (C)
Growth Rate, micron/min
1300 1200 1100 1000

1.0
900
800
700
0.5
0.2
SiH4
Mass transport
limited
0.1
SiHCl3
0.05
0.02
Surface reaction limited

SiH2Cl2
0.01
0.7
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0.8
0.9
1000/T(K)
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1.0
1.1
48
Barrel Reactor
Radiation
Heating
Coils
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Wafers
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Vertical Reactor
Wafers
Heating
Coils
Reactants
Reactants and
byproducts
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Horizontal Reactor
Heating Coils
Wafers
Reactants
Reactants and
byproducts
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Epitaxy Process, Batch System
Hydrogen purge, temperature ramp up

HCl clean
Epitaxial layer grow
Hydrogen purge, temperature cool down
Nitrogen purge
Open Chamber, wafer unloading, reloading
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Single Wafer Reactor

Sealed chamber, hydrogen ambient
Capable for multiple chambers on a mainframe
Large wafer size (to 300 mm)
Better uniformity control
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Single Wafer Reactor

Heat
Radiation
Heating Lamps
Wafer
Reactants
Reactants &
byproducts
Susceptor
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Quartz
Lift
Fingers
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Quartz
Window
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Epitaxy Process, Single Wafer

System
Hydrogen purge, clean, temperature ramp up

Epitaxial layer grow
Hydrogen purge, heating power off
Wafer unloading, reloading
In-situ HCl clean,

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Why Hydrogen Purge
Most systems use nitrogen as purge gas

Nitrogen is a very stable abundant
At > 1000 C, N2 can react with silicon
SiN on wafer surface affects epi deposition
H2 is used for epitaxy chamber purge
Clean wafer surface by hydrides formation
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Properties of Hydrogen
Name
Symbol
Atomic number
Atomic weight
Discoverer
Discovered at
Discovery date
Origin of name
Molar volume
Velocity of sound
Refractive index
Melting point
Boiling point
Thermal conductivity
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Hydrogen
H
1
1.00794
Henry Cavendish
England
1766
From the Greek words "hydro" and "genes" meaning
"water" and "generator"
11.42 cm3
1270 m/sec
1.000132
-258.99 C
-252.72 C
0.1805 W m-1 K-1
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Defects in Epitaxy Layer

Stacking Fault from
Surface Nucleation
Dislocation
Stacking Fault form

Substrate Stacking Fault
Impurity Particle
Hillock
Epi Layer
Substrate
After S.M. Zses VLSI Technology

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Future Trends
Larger wafer size

Single wafer epitaxial grow
Low temperature epitaxy
Ultra high vacuum (UHV, to 10-9 Torr)
Selective epitaxy
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Summary
Silicon is abundant, cheap and has strong,
stable and easy grown oxide.
<100> and <111>
CZ and floating zone, CZ is more popular
Sawing, edging, lapping, etching and CMP
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Summary
Epitaxy: single crystal on single crystal
Needed for bipolar and high performance
CMOS, DRAM.
Silane, DCS, TCS as silicon precursors
B2H6 as P-type dopant
PH3 and AsH3 as N-type dopants
Batch and single wafer systems
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Chapter 4

Give two reasons why silicon dominate

Hong Xiao, Ph. D.

Hong Xiao, Ph. D.

Hong Xiao, Ph. D.

Hong Xiao, Ph. D.

Single Crystal Structure

Hong Xiao, Ph. D.

Hong Xiao, Ph. D.

Jns Jacob Berzelius

From the Latin word "silicis" meaning "flint"

Bond length in single crystal Si

Hong Xiao, Ph. D.

Unit Cell of Single Crystal Silicon

Hong Xiao, Ph. D.

Crystal Orientations: <100>

Crystal Orientations: <111>

Crystal Orientations: <110>

<100> Orientation Plane

Hong Xiao, Ph. D.

<111> Orientation Plane

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<100> Wafer Etch Pits

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<111> Wafer Etch Pits

Hong Xiao, Ph. D.

Illustration of the Defects

Vacancy or Schottky Defect

Hong Xiao, Ph. D.

From Sand to Wafer

Quartz sand: silicon dioxide

From Sand to Wafer (cont.)

Cut end, polish side, and make notch or flat

From Sand to Silicon

Hong Xiao, Ph. D.

Pure TCS with

Polysilicon Deposition, EGS

Hong Xiao, Ph. D.

Electronic Grade Silicon

Crystal Pulling: CZ method

Mitsubish Materials Silicon

Floating Zone Method

Comparison of the Two Methods

Ingot Polishing, Flat, or Notch

Flat, 150 mm and smaller

Notch, 200 mm and larger

Parameters of Silicon Wafer

Wafer Size (mm)

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Wafer Edge Rounding

Wafer Before Edge Rounding

Wafer After Edge Rounding

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Chemical Mechanical Polishing

200 mm Wafer Thickness and

After Wafer Sawing

After Edge Rounding

Virtually Defect Free

Hong Xiao, Ph. D.

Hong Xiao, Ph. D.

Improve device performance for CMOS and

Epitaxy Application, Bipolar