What is an Interface

An interface is a concept that refers to a point of

interaction between components, and is applicable
at the level of both hardware and software.
This allows a component, (such as a graphics card
or an Internet browser), to function independently
while using interfaces to communicate with other
components via an input/output system and an
associated protocol.
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Example Block Diagram

Address Lines

8085

Data Lines

Memory

Control Lines
Interface
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8085 Interfacing Pins

Higher Address Bus

8085

Lower Address/Data Bus

ALE

A15 A8
AD7 AD0

IO/ M

RD

WR

READY
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Address Bus of 8085

Address Bus
Used to address memory & I/O devices
8085 has a 16-bit address bus

A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Data Bus

Used to transfer instructions and data

8085 has a 8-bit data bus
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Higher Order Address Bus

The higher order address bus is a unidirectinal
bus.
It carries most significant 8-bits of a 16-bit
address of memory or I/O device.
Address remains on lines as long operation is
not completed.

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Lower Order Address/Data Bus

This bus is bidirectional and works on time
division multiplexing between address and
data.
During first clock cycle, it serves as a least
significant 8-bits of memory/ I/O address.
For second and third clock cycles it acts as
data bus and carries data.

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De-multiplexing Address/Data Lines

8085 identifies a memory location with its 16
address lines, (AD0 to AD7) & (A8 to A15)
8085 performs data transfer using its data
lines, AD0 to AD7
Lower order address bus & Data bus are
multiplexed on same lines i.e. AD0 to AD7.
De-multiplexing refers to separating Address &
Data signals for read/write operations.
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Need for Demultiplexing

RD

20H
05H

A15 A8
AD7 AD0

Memory

4FH

2005H

8085

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Demultiplexing Address/Data Lines

Data

Memory

74LS373

8085

AD0-AD7

A0 A7
ALE

Chip

Control
A8-A15

A8-A15

Memory Interface
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Generating Control Signals

IO/ M

RD=0
WR=1

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=0

1
1
1
0
0
1
0
0

Memory Read
Memory Write
I/O Read
I/O Write
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Generating Control Signals

IO/ M

RD=1
WR=0

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=0

1
0
1
1
0
0
0
1

Memory Read
Memory Write
I/O Read
I/O Write
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Generating Control Signals

IO/ M

RD=0
WR=1

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=1

0
1
0
0
1
1
1
0

Memory Read
Memory Write
I/O Read
I/O Write
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Generating Control Signals

IO/ M

RD=1
WR=0

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=1

0
0
0
1
1
0
1
1

Memory Read
Memory Write
I/O Read
I/O Write
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8085 Interfacing with Memory chips

Data

Program

74LS373

8085

AD0-AD7

A0 A7
ALE

A8-A15
I/O/
M
RD

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Memory

A8-A15
CS
RD

Memory
Interface

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Interface with two memory chips

A1
A0

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11

11

10

10

01

01

00

00

Memory 1

Memory 2
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Interface with two memory chips

A1
A0

A3

11

011

11

111

10

010

10

110

01

001

01

101

00

000

00

100

CS

CS

Memory 1
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Memory 2
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Interface with Multiple Chips

In case of multiple chips simple circuit
like NOT gate will not work.
In this case normally decoder circuits like
3-to-8 decoder circuit 74LS138 are used.
These circuit are called address decoders.

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Address decoders
2 to 4 decoder

A12
A11

S1
S0

O0
O1
O2
O3

E
A13

CS

Memory 1

CS

Memory 2

CS

Memory 3

CS

Memory 4

A10 - A0
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The Overall Picture

A15- A10

Chip Selection
Circuit

8085
CS

A15-A8
ALE
AD7-AD0

WR RD I/O/M

Latch

A9- A0
A7- A0

1K Byte
Memory
Chip

D7- D0
RD WR

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Types of Address Decoding

There are two types of address decoding
techniques
Full Decoding
Partial Decoding

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 In this type of scheme all the 16 bits of the

8085 address bus are used to select a
particular location in memory chip.
Advantages:
Complete Address Utilization
Ease in Future Expansion
No Bus Contention, as all addresses are unique.

Disadvantages
Increased hardware and cost.
Speed is less due to increased delay.
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 In this scheme minimum number of address

lines are used as required to select a memory
location in chip.
Advantages:
Simple, Cheap and Fast.

Disadvantages:
Unutilized space & fold back (multiple mapping).
Bus Contention.
Difficult future expansion.
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 Using I/O devices data can be transferred between

the microprocessor and the outside world.
This can be done in groups of 8 bits using the entire
data bus. This is called parallel I/O.
The other method is serial I/O where one bit is
transferred at a time using the SID and SOD pins on
the Microprocessor.
There are two ways to interface 8085 with I/O
devices in parallel data transfer mode:
Memory Mapped I/O
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I/O Mapped I/O

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 It considers them like any other

memory location.
They are assigned a 16-bit address within
the address range of the 8085.
The exchange of data with these devices
follows the transfer of data with memory.
The user uses the same instructions used
for memory.
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 It treats them separately from memory.

I/O devices are assigned a port number
within the 8-bit address range of 00H to
FFH.
The user in this case would access these
devices using the IN and OUT instructions
only.

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Memory Mapped I/O

I/O Mapped I/O

I/O is treated as memory.

16-bit addressing.
More Decoder Hardware.
Can address 216=64k
locations.
Less memory is available.

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I/O is treated I/O.

8- bit addressing.
Less Decoder Hardware.
Can address 28=256
locations.
Whole memory address
space is available.

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 Memory Mapped I/O I/O Mapped I/O

Memory Instructions are
used.
Memory control signals
are used.
Arithmetic and logic
operations can be
performed on data.
Data transfer b/w register
and I/O.
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Special Instructions are

used like IN, OUT.
Special control signals
are used.
Arithmetic and logic
operations cannot be
performed on data.
Data transfer b/w
accumulator and I/O.

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 Draw and explain an Memory mapped

I/O interfacing with 8085 microprocessor
having eight push button switches on
0000H memory location and a common
LED seven segment display at 0001H
memory location.
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 Design an 8085 microprocessor system

such that it should contain 2KByte of
EPROM and 2KByte of RAM with starting
addresses 0000H and 6000H respectively.

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 Design an 8085 microprocessor system

such that it should contain 16KByte of
EPROM and 4KByte of RAM using two
8KByte of EPROMs(2764) and two 2KByte
of RAMs(6116).

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