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Comparative Analysis of Different

Architectures of CMOS Comparator


Jatin Jajal1, Mehul L. Patel2
AbstractDue to rapid growth of technology on high speed
applications, balance should be maintained between analog and
digital world. For that, an Integrated Chip (IC) required data
converter block includes nonlinear components like comparator,
multiplier etc. In this paper, different architectures of
comparator are compared for high speed data converters are
presented. Prerequisite parameters are discussed to achieve the
proper design of comparator to meet the required specifications.
Performance parameters of dynamic, double tail and fully
differential pair dynamic latch architectures are compared.
Above all mostly used architecture has been concluded.
Key words : Complementary Metal-Oxide Semiconductor
(CMOS), analog-to-digital converter (ADC), comparator
I.

INTRODUCTION

ecently, where demand for handheld devices are


increasing, a major push towards for high speed
applications and low power methodologies.
Relaxation between high speed and low power
applications achieved by reducing the size. As we reduce
the size variation and non-idealities are affect the
performance of the device. One such application high
speed, low power consumption and low noise are
required. For that, the function of comparison is a
important, and often a crucial component in the design of
high speed data conversion system caused by its finite
accuracy, comparison speed and power consumption [9].
The critical element in an Analog-to-Digital Converter
(ADC) is the comparator. It is a circuit that compares
analog signal with a reference voltage which is also
analog signal and gives the outputs a binary signal based
on the comparison. Comparator also is called as 1-bit
ADC. Depending on the nature and functionality of
inputs, comparators are classified into different types i.e.
voltage/current comparators, continuous/discrete time
comparators etc. Some applications of comparators are
ADC, memory design, signal detection and neural
networks etc.
Basically, two stage operational
amplifiers(op-amps) can be used as a comparator which
required high gain, low power dissipation, minimum
propagation delay and amplify minimum input change
voltage (Vmin). Due to trade-off between gain and
bandwidth that limit the performance of comparator.
Overcome this performance limitation new architectures
has been developed [1].

Manuscript received June 20, 2016). Comparative Analysis of


Different Architectures of CMOS Comparator
J. A. Jajal is with the Marwadi Education Foundation Group[ of
Institutions, Rajkot, Gujarat, India (phone: 94268554451; e-mail:
jatinjajal11@gmail.com).
M. Patel is with the Marwadi Education Foundation Group[ of
Institutions, Rajkot, Gujarat, India (phone: 8238089155; e-mail:
mehulkumar.patel@marwadieducation.edu.in).

Gain, sensitivity, input offset, response time, overdrive


recovery
time,
latching
compatibility,
power
consumption, power supply rejection and hysteresis are
the key parameters that characterize the comparator. To
design a comparator some of the key points like
comparator gain required more than 80db, offset should
be less than 1 LSB(Least Significant bit), accuracy
should be meet the requirements, settling time make it as
small as possible and metastability should not be
occurred. There is offset cancelation, regenerative,
latched, switched-capacitor based, fully differential and
multistage comparator etc., architectures to meet the
requirements for different applications [2].
Comparator can be used as a voltage sense amplifier, in
memory elements and voltage sense amplifier etc., the
most use of comparator in ADCs. As per the requirement
of high speed ADCs that includes ADC architectures like
flash, Successive Approximation Register(SAR),
pipeline, folding and interpolating ADCs. Most of the
ADCs required comparator to digitize the analog signal.
These high speed ADC can be used in signal processing
applications, radio frequency applications, military and
space applications [3].
In the past, pre-amplifier based comparators has been
used for ADC architectures such as pipeline and flash.
The main negative aspect of pre-amplifier based
comparators is the more offset voltage. To defeat this
problem, dynamic comparators are often utilized that
make a comparison once every clock period and require
much less offset voltage. However, these dynamic
comparators experience from large power dissipation
compared to pre-amplifier based comparators [8].
Orientation of this paper is as follows: Section I gives
the brief introduction of Comparators for high speed
applications. Section II consists of various comparator
architectures designed. Section III gives the brief
comparison of all the performance parameters mentioned

in section II. Section IV points out the best architecture


based upon the comparison table and finally section V
shows future scope.
II.

COMPARATOR ARCHITECTURES

Comparator has mainly three stages pre-amplifier,


latch and output buffer as shown below.

Figure 1 Block Diagram of Voltage Comparator [4]


Where, vp and vm are positive and negative voltage
respectively, iop and iom are positve and negative
currents of the pre-amplifier stage and vop,vom and vout
are positive and negative output voltage of decision
circuit and output logic level respectively [4].
A. Dynamic comparator\
Figure 2 illustrates the conventional double tail
comparator proposed in [5].

VDD, start to discharge with different discharging rates


depending on the corresponding input voltage (INN/INP)
[5].
The discharge time (t0) is given by
t0 =

| |
2

| |

.[5]

Due to parasitic capacitance of input transistors do not


directly affect the switching speed of the output, it is
possible to minimize offset large input transistor
required. Another important problem of this structure is
that there is only one current path through tail transistor
Mtail1, which defines the current for the differential
amplifier and the latch (cross-coupled inverters). While
one would like a small tail current to keep the differential
pair in threshold region and obtain a long integration
interval and better Gm/I ratio, a large tail current would
be desirable to enable regeneration latch [5].
The maximum sampling frequency, delay,
regeneration time, kickback noise voltage, input-referred
offset voltage are compared in Table-I.
B. Double-Tail Comparator
The behavior of the double-tail comparator shown in
Fig 3. During the reset period (CLK = 0V), transistors M7
and M8 pre-charge the Di nodes to VDD, which in turn
cause M10 and M11 to discharge outputs node to ground
(so there is no need for reset transistors at output nodes).
At the Di nodes, the common mode voltage then drops
monotonically with a rate defined by IM2/CDi and on the
top of this, an input dependent differential voltage V Di
will build.

Figure 2: Schematic diagram of conventional dynamic


comparator [5]
In this design, authors has analyzed conventional
dynamic comparator to achieve input impedence as high
as possible, full scale output swing, and no static power
consumption.
The operation of the comparator is as follows. During
the reset phase when Clock(CLK) = 0 and Mtail is off,
reset transistors (M7-M8) pull both output node outn and
outp to VDD to define a start condition and to have a
suitable logical level during reset. In the comparison
phase, when CLK = VDD where VDD is supply voltage,
transistor M7 and M8 are off, and Mtail is on. Output
voltages (Outn, Outp), which had been pre-charged to

Figure 3: Schematic diagram of Double-tail


Comparator [6]

Optimization of double tail topology has improved that


enables better optimization of the speed, offset, power
and commonmode voltage. Also, it has better isolation
between input and output and is well suited to operate at
low supply voltages [6].

From the above architectures, there is always tradeoff between high speed and low power and to reduce this
trade-offs there are compensation technique used but it
may affect the performance of comparator [10].
III.

Double tail comparators different


parameters are compared in Table I.
C. Fully-Differential Comparator

performance

In the design shown in Fig. 5, a fully differential


dynamic latch comparator based on cross-coupled
differential pair which is taken of the design of LewisGray dynamic comparator [7] .

Results obtained by employing various architectures


discussed in section II, are compared in this section.
Below table shows the detailed comparison of above
techniques.
Table I: Comparison of Different CMOS Comparator
Architectures
Parameter
Technology
CMOS*
Supply Voltage(V)
Maximum Sampling
Frequency

In Figure 5, transistors M0, M3, M5 and M7 are


utilized as the input circuit. The overall latch circuit have
of transistors M1, M8 to M15. This topology, the latch
circuit is directly connected to the source coupled
transistors M3 and M5 and the supply voltages M1, M8 to
M15, which makes the current source can switch. To reset
the S-R latch at output of the comparator, a digital signal
power down (PD) is used. When the Comparator is off,
Vlatch = low, the current source transistors M12 is
switched off, and no current path exist from the supply
voltage. The PMOS transistors M1, M8, M10 and M15 reset
the outputs VON and VOP and the nodes n1 and n2 to VDD.
On the comparison phase, when Vlatch = high, the
outputs are disconnected from the positive supply and
switching current source M12 starts to conduct. M12
determines the bias current of the input transistors M0,
M7, M3, and M5. The cross-coupled pair M3 and M5 is
utilized in the proposed topology to produce positive
feedback that allows the output to switch faster.

[5]

[6]

[7]

180nm

180nm

180nm

0.8
900
MHz
940
ps/dec.

0.8

1.8
50
MHz

1.8 GHz
358
ps/dec.

4.2 ns

215nV

221nV

51.3
mV

5.3mV

0.3p

0.27p

0.7
fj/conv

Input-referred Offset
Voltage (mV)

7.89

7.91

3.44

Power

158.5
W

Delay

Figure 4: Schematic diagram of Fully differential


dynamic latch comparator [7]

COMPARISON

Peak transient noise


voltage at
Regeneration time
Kickback noise
voltage
Energy per
conversion(J)

IV. CONCLUSION
Having being studied and compared various
architectures, it can be concluded that double-tail
comparator presented in [6] gives the increase in
sampling frequency, reduce delay and kickback noise
voltage requirements for high speed applications as
shown in table I. Apart from the offset voltage required
all parameters satisfy the requirements for an high speed
application. Further it can be analyzed to reduce its area
which will further be helpful to use in different
applications.

V.

FUTURE SCOPE

With the help of integrated technology, comparator can


be designed on single IC. With this it is possible to shrink
the down the size as well as to reduce the power
consumption of Comparator. Further it can be used to
build voltage sense amplifier, data receivers, memory
sense amplifier etc.

VI.
[1]

[2]
[3]
[4]
[5]

[6]

[7]

[8]
[9]
[10]

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(M14). Currently doing Master


of Engineering in VLSI System Design
from Marwadi Education Foundation
Faculty of P.G Studies & Research in
Engineering and Technology, Rajkot,
Gujarat, India. Has completed B.E in
the year of 2013.
1Jatin

2Mehul

Patel is currently working as


Senior Assistant Professor in Marwadi
Education Foundations Group of
Institutions, Rajkot, Gujarat, India. His
Research Interests includes Analog
Circuit Design and Optimization.