International Conference on Magnetics, Machines & Drives (AICERA-2014iCMMD)

Implementation of High Performance Dynamic

Flash ADC
Titu Mary Ignatius, Jobin.K.Antony, Silpa Rose Mary
Rajagiri School of Engineering and Technology, Kochi, Kerala, India
titu.mathew2011@gmail.com, jobinka@rajagiritech.ac.in, silparosemary@gmail.com

input signal is greater than reference or not. If Vin > Vref ,

then output of comparator is logic 1, else logic 0. The output
generated by a set of comparators is thermometer code, where
a group of 0s are followed by a group of 1s. The thermometer
code is converted to binary code using encoders. The Fig.2
shows a 3-bit Flash ADC, which requires 8 resistors and 7
comparators.

AbstractDynamic Flash ADC has lot of applications in real

time systems and mixed signal systems, where analog signals
are converted to digital signals and then processed. In the
present work, a new high performance dynamic Flash ADC
is designed, which employs fast thermometer encoder and low
power open loop comparator. Subsequently, a dynamic Flash
ADC using standard cells such as NAND, NOR and INVERTER
is also designed and implemented. Various parameters of the
new dynamic Flash ADCs are analysed and it is found that these
designs are best suited for low power applications. These dynamic
Flash ADCs are designed in 180nm technology and post layout
simulation is performed using Cadence Spectre tool.
Index Termsdynamic Flash ADC; dynamic thermometer
encoder ; Open loop comparator; Cadence Spectre; post-layout;

I. I NTRODUCTION
In nature all signals are analog and it is difficult to process
and analyse analog signals directly. Moreover analog signals
are more prone to noise and interference of side band signals.
Design and verification of analog circuits are more difficult
compared to digital circuits and scaling down of analog
circuit deals with several design issues. In almost all practical
applications it is required to convert analog signal to digital
signals using suitable ADC and which is the key component
in modern electronic systems and mixed signal systems. The
general block diagram (Fig.1) of an analog to digital converter
has an anti-aliasing filter, sample and hold circuit and Flash
ADC[6-7]. Anti-aliasing filters are used to prevent aliasing
effect. Sample and hold circuits are used for sampling, which
convert analog signal to discrete signal. Sampling is done at
Nyquist rate, fs = 2f m . Flash ADC quantizes and convert
discrete signal to digital signal.

Fig. 2. Circuit level representation of Flash ADC

There is a wide selection of comparators such as conventional comparator, comparator 1[2] and open loop comparator
[9] and thermometer encoders such as XOR encoder [3]and
Wallace tree encoder [8] in the literature. Most of the systems
use conventional comparator[2], which require large number
of transistors. Traditional comparators are replaced by low
power comparators such as comparator 1[2] and open loop
comparator[9]. Open loop comparator[9] is best suited for low
power application.
In the present work a high performance dynamic Flash ADC is
designed and implemented using the fast dynamic thermometer encoder and low power open loop comparator. It has been
observed that the new dynamic flash ADC is area-efficient,
as the number of transistors is reduced by 50%. Also it is
best suited for low power applications. Later-on a dynamic
standard cell Flash ADC has been designed and implemented.
The above mentioned ADC is technology independent, since

Fig. 1. Block Diagram of a Practical ADC

Many flash ADCs architectures [4-7] are reported in the

literature. N-bit Flash ADC, has 2N resistors in resistor ladder,
which produces the reference voltages, and 2N 1 comparators, which compare the applied input signal with reference
voltage and produce either 1 or 0, depending on whether
c
978-1-4799-5202-1/14/$31.00 2014
IEEE

International Conference on Magnetics, Machines & Drives (AICERA-2014iCMMD)

this design involves only digital logic gates. The design issues
while scaling down from one technology to other technology
will be less, since the analog comparator is replaced with
logic gates such as NAND, NOR and NOT. Also standard
cell dynamic Flash ADC is easy to fabricate. These dynamic
Flash ADCs are designed in 180nm technology using Cadence
Spectre. Post-layout simulations are also performed.

TABLE I
A NALYSIS OF THE VARIOUS PARAMETERS OF OPEN LOOP COMPARATOR
Power
Delay
Gain
Bandwidth (BW)
Gain Bandwidth Product (GBP)
SlewRate at 1MHz

III.

II. I MPLEMENTATION OF COMPARATOR

41.74 uW
37.46nS
46.811 dB
496 MHz
4.96 GHz
345.6 V/uS

DYNAMIC THERMOMETER ENCODER

In ADC, a series of resistors and comparators produce an

output, which is a group of 1s followed by a group 0s for a
particular analog voltage given as input. The outputs of the
comparators are converted to binary code, using thermometer
encoders. Digital thermometer encoders are of two types
XOR thermometer encoder[3] and Wallace tree encoder [8].
In the XOR thermometer encoder[3], the thermometer code
is first converted to Gray code, which is then converted to
binary digital code.Gray code is an intermediate code,while
converting thermometer code to binary digital code, which
minimize the effect of the metastability and bubble errors.
XOR gates replace the AND/NAND gates due to the special
format of the thermometer code itself,which improves the
reliability of the encoder.
The Wallace tree thermometer encoder[8] uses several full
adders connected in parallel. Due to the tree structure,
the numbers of transistors are reduced compared to the
XOR encoder.Wallace tree method can correct higher order
bubbles.The wallace tree method are used in implementation
of high speed multipliers in computer arithmetic units is the
most efficient. It is used in the thermometer encoder in Flash
ADCs where the number of 1s is counted.

Comparator is one of the key blocks for high speed

operation of an ADC. For a voltage comparator, it will
produce output 1 when the analog input voltage is greater
than the reference voltage and vice-versa.The conventional
comparator [2] consist of three stages - input stage, decision
stage and output stage. The input stage is a differential
amplifier with active loads, which convert input voltages to
output currents, which is used to drive the decision circuit.
The decision circuit is a bistable cross coupled circuit,to
improve the performance efficiency.The output stage is used
to convert the output voltage of the decision circuit into
digital logic signal. Comparator 1 [2]consists of 2 stages.
1st stage is differential amplifier and 2nd stage is a common
source amplifier, which provides high gain and high stability.
It also lowers the output impedance.
Open Loop Comparator[9] consists of two stages: input stage
and output stage, as shown in Fig 3. The input stage is a
differential pair with current mirror, which provides high gain
and the output stage is a buffer which provides large output
swing and high stability. The advantage of this circuit is that
the circuit consumes minimal number of transistors and thus
the overall circuit area is small. Open loop comparator is best
suited for low power applications, and requires only lesser
area and has the highest performance [2].

TABLE II
T RUTH TABLE FOR 4-B IT T HERMOMETER E NCODER
Thermometer Code
000000000000000
000000000000001
000000000000011
000000000000111
000000000001111
000000000011111
000000000111111
000000001111111
000000011111111
000000111111111
000001111111111
000011111111111
000111111111111
001111111111111
011111111111111
111111111111111

Fig. 3. Schematics of open loop Comparator.

Bit3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Bit2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Bit1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Bit0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

The truth table of a 4-bit Dynamic encoder is depicted

above. From Table.2 Bit 3, Bit 2, Bit 1 and Bit 0 can be
evaluated. The equations for 4-bit dynamic thermometer
encoder are derived from its truth table.

A transient analysis is carried out and its functionality is

verified. Also various parameters of the open loop comparator
are tabulated in Table.1.
2

International Conference on Magnetics, Machines & Drives (AICERA-2014iCMMD)

Bit3 = In7
7 + In11
Bit2 = In3 In

7 + In9 In
11 + In14
Bit1 = In1 In3 + In5 In

5 + In6 In
7+
Bit0 = In0 In1 + In2 In3 + In4 In

In8 In9 + In10 In11 + In12 In13 + In14

Dynamic thermometer encoders are designed using dynamic
logic style for obtaining highest performance and lowest area.
As the number of bits (resolution) of ADC increases, the
maximum frequency of operation decreases. The dynamic
CMOS circuit consists of single PMOS transistor and a bunch
of NMOS transistors. In dynamic thermometer encoder, shown
in Fig. 4, Fig. 5 and Fig. 6, the thermometer code is converted
to binary output code without any intermediate stage. The
number of transistors used is reduced to half when compared
with CMOS logic, since PMOS network is replaced by a single
PMOS transistor.
The circuit operates in two phases - pre-charge and evaluation.
During the pre-charge phase, when CLK = 0 output node is
pre-charged to VDD by the pull-up PMOS transistor. The pulldown network is turned off during this time, independent of the
logic implemented. During the evaluation phase, when CLK
=1, the pre-charge PMOS transistor is turned off and the footed
NMOS is turned on. The output is evaluated during this time
depending upon the NMOS transistor conditions in the pull
down network, which depend on the logic. The inverter in the
output stage will invert the state and will give logic low or
logic high value.
The Total power dissipation in dynamic circuits are due to
static power dissipation and dynamic power dissipation. The
power dissipation occurring at the time of switching is called
dynamic power dissipation,which contribute to the major part
of the total power dissipation. Static power dissipation occurs
when both pull up and pull down network are on. When both
Pull Up and Pull down network are turned on, current flows
from VDD to GND which dissipates a power in the circuit
which leads to static power dissipation. The static Power
dissipation is reduced in dynamic circuits, due to the presence
of footed NMOS.

Fig. 5. Bit1 of a 4-Bit Dynamic Thermometer Encoder

Fig. 6. Bit0 of a 4-Bit Dynamic Thermometer Encoder

From the simulation results, shown in Table.3, it is clear

that, the output depends on the clock frequency. As the
frequency increases the switching power increases, thereby
increasing the total power, but static power is less, due to
the presence of a footed NMOS transistors. Input should
be stable for at least 1 clock cycle, for obtaining correct output.

TABLE III
C OMPARISON OF DIFFERENT PARAMETERS OF VARIOUS T HERMOMETER
ENCODERS

Thermometer
Encoder
XOR encoder
Wallace encoder
Dynamic encoder

No:of
transistors
252
168
56

Static Power
(nW)
1.64
2.75
0.29

Total Power
(nW)
226
488.3
138

Delay
(ps)
380.6
210.7
152.2

It was found that dynamic thermometer encoder has the

highest performance, with respect to all parameters. It requires
only one-third the number of transistors compared to Wallace
tree encoder and one-fifth the number of transistors compared
to XOR encoder. Hence the area is reduced drastically.
Due to the presence of footed NMOS and lesser number of
transistors, the static power is also reduced to 0.2927 nW.
The Dynamic Thermometer Encoder has the highest speed
among all the three.
IV. H IGH P ERFORMANCE DYNAMIC F LASH ADC
The High-Performance dynamic Flash ADC [Fig. 7] is
designed using the new dynamic thermometer encoder. Its

Fig. 4. Bit3 and Bit2 of a 4-Bit Dynamic Thermometer Encoder

International Conference on Magnetics, Machines & Drives (AICERA-2014iCMMD)

functionality is verified from its output waveform shown in
Fig. 8. The overall area and power is reduced drastically. The
3-bit, 4-bit and 5-bit dynamic Flash ADCs were designed and
its various parameters were analysed.

input analog signal. The threshold voltage of the gate serves

as the reference voltage for each particular gate to which
analog input is compared. The Threshold voltage of each gate
VGT H is given by equation below[1].
VGT H =

VDD VT H +M.VT H
M +1

, where M is the no:of transistors

NAND gate have higher threshold than the INVERTER

and NOR gate have lower threshold than INVERTER. In
NAND gate as the number of inputs increases, threshold
increases and for NOR gate as the number of input increases,
threshold decreases.
.
Fig. 7. 4-bit Dynamic Flash ADC

.
Fig. 8. Output Waveform of a 4-Bit ADC

Fig. 9. 3-bit Dynamic Flash ADC using standard cells

Dynamic standard cell ADC shown in Fig. 9 is completely

digital, so it is easy to fabricate and scale down from one
technology to another. It requires lesser area than dynamic
Flash ADC and higher performance. But the main drawback
of standard cell dynamic ADC is non-uniform step size.

TABLE IV
C OMPARISON OF PERFORMANCES OF 3- BIT, 4- BIT AND 5- BIT DYNAMIC
F LASH ADC

ADC
3-Bit
4-Bit
5-Bit

No:of
transistors
85
176
331

Static Power
(nw)
3.42
7.31
15.08

Total Power
(nW)
128.3
152.6
161.9

Delay
(nS)
111.0
170.6
296.4

VI. C ONCLUSION
A high performance dynamic Flash ADC using new
area-efficient dynamic thermometer encoder and low power
open loop comparator is implemented and its performance
is verified. It has been observed that the power dissipation
and propagation delay is optimum for the new design. The
number of transistors is reduced by 50%, which results in an
area efficient implementation.

From the Table. 4, it is seen that even though the area,

power and delay of dynamic flash ADC is lesser than usual
flash ADC, as the number of bits of dynamic flash ADC
increases, the number of transistors increases logarithmically
and static power doubles as the resolution increases by a bit.
Thus, Delay and Total Power increases drastically as number
of bits dynamic Flash ADC increases.
V.

DYNAMIC

Subsequently a threshold based standard cell dynamic Flash

ADC has been implemented, which is best suited for digital
IC fabrication, since analog comparators are replaced with
logic gates. Moreover technology scaling can be performed
more easily for the design. Post-Layout simulations of RC
extracted circuit, Design Rule Check (DRC) and Layout
Versus Schematic (LVS) of a proposed dynamic Flash ADCs
have also been performed.

F LASH ADC USING STANDARD CELLS

In dynamic Standard cell ADC [1] and [4] analog

comparators, designed using differential amplifiers are
replaced with logic gates such as NAND and NOR,
configured as inverters having different threshold voltage. All
their inputs connected to a common input node. Output of
logic gates in ADC is a thermometer code, depending on the
4

International Conference on Magnetics, Machines & Drives (AICERA-2014iCMMD)

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