Prepared by: Er.

Sarbesh Chaudhary

INRODUCTION TO MICROPROCESSOR, UNIT 6

UNIT 6
INTRODUCTION TO GENERAL PURPOSE
PROGRAMMABLE PERIPHERAL DEVICES
8255 PROGRAMMABLE PERIPHERAL INTERFACE (PPI)
A programmable peripheral interface is a multiport device. The port may be programmed in a variety of ways as
required by the programmer. The device is very useful for interfacing peripheral devices. It has three 8- bit ports,
namely port A, port B and port C. The port C has been further divided into two of 4-bit ports, and port C upper and
port C lower. Thus a total of 4 ports are available, two 8-bit ports and two 4-bit ports. Each port can be programmed
either as an i/p port or an o/p port.
Architecture of INTEL 8255

INTEL 8255 is a 40 pin IC which operates on 5V supply. The pins for various ports are as follows

1.PA0 PA7 - 8 pins of port A

3.PC0 PC3 - 4 pins of port Clower

2.PB0 PB7 - 8 pins of port B

4. PC4 PC7 - 4 pins of port Cupper.

The important control signals for 8255 are as follows:

(CS): This is Chip Select signal. A LOW signal on this input pin enables the communication between the 8255A &
CPU.
(RD): when this Read signal is LOW it enables the 8255A to send the data or status information to the data bus of
CPU. In essence, it allows the CPU to READ from the input port of 8255A.
(WR): When this Write signal is LOW on the input pin it enables the CPU to write data or control words into the
output port of 8255.
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(A0 and A1): These are Port Select 0 and Port Select 1 input signal. These Input signals, in conjunction with the RD
and WR Input controls the selection of one of the three ports or the control word registers. They are normally
connected least significant bits of the address bus (A0 and A1).

Operating modes of 8255:

8255 has 3 modes of operation which are selected by software.
Mode 0 - Simple input/output
Mode 1 Strobed input/output
Mode 2 Bidirectional port.
Mode 0: In this mode of operation, a port can be operated as a simple o/p or i/p port. Each of the four ports of
8255 can be programmed to be either an i/p or o/p port.
Mode 1: Mode 1 is strobed input/output mode of operation. The port A and port B both are designed to operate in
this mode of operation. When port A and port B are programmed in mode 1, six pins of port C are used for their
control. PC0, PC1 and PC2 are used for control of port B which can be used as input or output port. If the port A is
operated as an input port then PC3, PC4, and PC5 are used for its control. The remaining pins of port C, i.e PC6 and
PC7 can be used as either input or output. When port A is operated as an output port, pins PC3, PC6 and PC7 are
used for its control. The pins PC4 and PC5 can be used either as input or output.
Mode 2: Mode 2 is strobed bidirectional mode of operation. In this mode port A can be programmed to operate as
a bidirectional port. The mode 2 operation is only for port A. When port A is programmed in mode 2, the port B can
be used in either mode 1 or mode 0. For mode 2 operation PC3 to PC7 are used for the control of port A.

CONTROL WORD
A port can be programmed to be an input or output port. For programming the ports of 8255 ,a control word is
formed. This control word is written into control word register of 8255. The control word bit can be 0 or 1. If the bit
is 1, then the port will be input port & if the bit is 0, then the port will be output port. The control word register
format is shown in the figure below.
The detailed description of the bits of the control word is as follows:
1.BIT 0: It is for Port Clower. If 0, Port Clower is output port. If 1, Port Clower is input port.
2.BIT 1: It is for Port B. If 0, port B is output port. If 1, port B is input port.
3.BIT 2: It is for the selection of the mode for the Port B. If 0, Port B operates in Mode 0. If 1, B operates in Mode 1.
4.BIT 3: It is for Port Cupper. If 0, Port Cupper is output port. If 1, Port Cupper is input port.
5.BIT 4: It is for Port A. If 0, port A is output port. If 1, port A is input port.
6.BIT 5 & BIT 6: These bits are to define the operating mode of the port A. For the various modes of Port A these bits
are defined as follows:
Mode of Port A Bit no. 6 Bit no. 5
Mode 0
0
0
Mode 1
0
1
Mode 2
1
0 or 1
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7.BIT 7: It is set to 1, if Port A, B, & C are defined as input or output port. It is set to 0, if the individual pins of the
Port c are to be set or reset.

8254(8253) PROGRAMMABLE COUNTER/INTERVAL TIMER

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer
system design. It is used for the timing and counting functions such as, BCD/binary counting, generation of accurate
time delay, generation of square wave of required frequency etc. INTEL 8253 & 8254 are programmable interval
timer.8253 is compatible with 8085 Microprocessor while 8254 is compatible with 8085, 8086 & 8088
Microprocessors. The 8254 is a superset of the 8253.
It is a 24 pins IC which operates at 5v supply. It provides three independent 16-bit counters, each capable of
handling clock inputs up to 10 MHz. It consists of six counter modes and all modes are software programmable. The
pin description of 8253 is as follows:
A0-A1: These are connected to address bus & used to select one of the three counters.
CLK0, CLK1, CLK2: These are clocks for counter0, counter1 & counter 2 respectively.
GATE0, GATE1 & GATE2: These are input gate terminal of counter0, counter1 & counter2 respectively.
OUT0, OUT1 & OUT2: These are the output terminals of counter 0, counter 1 & counter 2 respectively.
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8253 also contains a data bus buffer which is of 8-bits & used to interface 8253 to the system bus via data lines. It
also contains read/write logic which takes input from system bus & generates control signals for operation of 8253.
The control word register and counters are selected according to the signals on lines A0 and A1.

Control Word Register : This register is accessed when lines A0 and A1 are at logic 1. It is used to write a command
word which specifies the counter to be used (binary or BCD), its mode, and either a read or write operation.

SC (select Counter)

SCO
0
0
1
1

SC1
0
1
0
1

M (Mode)
M2 M1
0
0
0
0
X
1
X
1
1
0
1
0

FUNCTION
Select Counter 0
Select Counter 1
Select Counter 2
Read-Back Command
(see Read Operations

RW1
0
0
1
1

RW0
0
1
0
1

RW (Read/Write)
OPERATION

Counter Latch Command

Read/Write least significant byte only
Read/Write most significant byte only
Read/Write least significant byte first,
then most significant byte
BCD

M0
0
1
0
1
0
1

MODE SELECTION
MODE0
MODE1
MODE2
MODE3
MODE4
MODE5

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0 Binary Counter 16bits

1 Binary Coded Decimal
(BCD) Counter

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Operating modes of 8253:

1.MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is used for generation of accurate time delay under software control. This mode is set by loading the
control word into control word register. In Mode 0 operation the output will be initially low after the mode set
operation. After the count is loaded into the selected count Register the output will remain low and the counter will
count. 3) When the terminal count is reached (i.e. count reaches zero) the output will go high and remain high until
the selected count is reloaded. Gate = 1 enables counting. Gate = 0 disables counting. Gate has no effect on OUT.

2. MODE 1: PROGRAMMABLE ONE-SHOT

The output will be initially high. The output will go low on the CLK pulse following the rising edge at the gate input.
The output will go high on the terminal count and remain high until the next rising edge at the gate input. The one
shot is re-triggerable, hence the output will remain low for the full count after any rising edge of the gate input.

3. MODE 2: Rate generator

The output will be initially high. The output will go low for one clock pulse before the terminal count. The output
then goes high, the counter reloads the initial count and the process is repeated. The period from one output pulse
to the next equals the number of input counts in the count register. If Gate = 1 it enables a counting otherwise it
disables counting (Gate = 0 ). If Gate goes low during an low output pulse, output is set immediately high. A trigger
reloads the count and the normal sequence is repeated.

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4. MODE 3: Square Wave Rate Generator

a) Initially output is high.
b) For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the counter reaches
terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole
process is repeated.
c) If the count is odd and the output is high the first clock pulse (after the count is loaded) decrements the count by
1. Subsequent clock pulses decrement the clock by 2. After timeout, the output goes low and the full count is
reloaded. The first clock pulse (following the reload) decrements the count by 3 and subsequent clock pulse
decrement the count by two. Then the whole process is repeated. In this way, if the count is odd, the output will be
high for (n+1)/2 counts and low for (n-1)/2 counts.
d) If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while output is low, output is set high
immediately. After this, When Gate goes high, the counter is loaded with the initial count on the next clock pulse
and the sequence is repeated.

5. MODE 4: Software Triggered Strobe

The output will be initially high. The output will go low for one CLK pulse after the terminal count (TC). If Gate is one
the counting is enabled otherwise it is disabled. The Gate has no effect on the output.

6. MODE 5: Hardware triggered strobe (Retriggerable)

The output will be initially high. The counting is triggered by the rising edge of the Gate. The output will go low for
one CLK pulse after the terminal count (TC). If the triggering occurs on the Gate input during the counting, the initial
count is loaded on the next CLK pulse and the counting will be continued until the terminal count is reached.

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8259 PROGRAMMABLE INTERRUPT CONTROLLER

It is used when several I/O devices transfer data using interrupt & they are connected to some interrupt line of
Microprocessor. INTEL 8259 is a single chip programmable interrupt controller. It is compatible with 8085, 8086 &
8088 Microprocessors. It is a 28 pin IC which uses NMOS technology. It requires 5v supply to operate.
Architecture of INTEL 8259

The detailed pin description of INTEL 8259 is given below.

CS (Chip select): A LOW signal on this pin indicates that chip has been selected.
WR (Write): If WR signal is LOW then INTEL 8259 will be enable to accept command word from CPU.
RD (Read): A LOW signal on this pin enable a 8259 to send status signal on data bus to CPU.
D7-D0 (Data lines): It is bidirectional data bus. Control, status & interrupt vector information are transferred via this
bus.
CAS0-CAS2: These are cascaded lines, which are used when more than one 8259 IC are to be connected.
SP/EN (Slave Program/Enable): It is related to cascade control. It is used to differentiate between master and slave
controller.
INT (Interrupt): this signal is used to interrupt CPU.
INTA (Interrupt Acknowledgement): Microprocessor acknowledges the requested interrupt through this pin.
IR0-IR7 (Interrupt Request): I/O devices send interrupt request through these lines.
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A0 (Address Line): It is in conjunction with RD, WR & CS. INTEL 8259 uses it to interrupt command words the CPU
writes & the status which CPU wants to read.
OPERATION OF 8259
Eight I/O devices can be connected to 8259 through IR0-IR7 lines. One or more I/O devices can send interrupt
request at the same time to the interrupt controller. Depending upon the priority of interrupt the request of I/O
device which has highest priority is sent to the Microprocessor on INT line. In return Microprocessor sends an
acknowledgement signal via INTA line. On receipt of INTA signal all the interrupts of lower priority are discarded.
And the address of the interrupt service subroutine (ISS) for the concerned I/O device is sent by 8259.
If there are more than eight devices to transfer data using interrupt then two 8259 chips can be connected in series,
such connection is known as cascading. The 8259 IC which is connected to the processor is known as Master & the
IC which is connected to the master is known as Slave.
INTERNAL REGISTERS OF 8259
1.Interrupt Request Register (IRR): It stores the interrupt request & keeps information about all the interrupt.
2.Interrupt Service Register (ISR): The information of the interrupt which is being serviced is stored in ISR.
3.Interrupt Mask Register (IMR): It contains a specific bit for each interrupt line. It is used to disable or enable an
interrupt.

Intel 8251 UNIVERSAL SYNCHRONOUS ASYNCHROUNOUS RECEIVER TRANSMITTER (USART)

INTEL 8251 is used for serial data transmission. It is also known as Programmable Communication Interface. It can
be interfaced with 8085, 8086 & 8088 Microprocessors. It can transmit or receive serial data. It accepts the data in
parallel format from Microprocessor and converts into serial data for transmission. It also receives serial data &
converts that in parallel form & send to CPU.
Architecture of Intel 8251

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Detailed pin description of Intel 8251 is as follows:

C/D (Control/Data): when this signal is low, data is transmitted from data bus. When it is high control signal is
transmitted.
DSR: Data Set Ready
DTR: Data Terminal Ready
CTS (Clear to Send): A low signal on this pin enables 8251 to transmit serial data.
RTS: Request To Send
TxD: Line for serial data transmission.
TxRDY: When the transmitter is ready this signal will be HIGH. Or else LOW.
TxE: Transmitter empty.
TxC: Transmitter clock. It controls rate of data transmission.
RxD: line for receiving data.
RxRDY: Receiver Ready.
RxC: It controls the rate at which character are received.
OPERATION OF INTEL 8251
A high signal on TxRDY line informs CPU that transmitter is ready to accept data. After receiving data from CPU, this
line becomes low. 8251 sends serial data on TxD line when CTS is low & transmitter is enabled serial data are
received on RxD line when RxRDY is low. After receiving data 8251 makes RxRDY high & informs CPU that is ready to
send data.
There are four modem control signals, they are: DSR, DTR, RTS & CTS. These are connected to corresponding lines of
MODEM. 8251 sends DTR signal to MODEM in order to indicate that it is ready to send data. When MODEM &
USART both are ready for data transmission the 8251 sends a low RTS signal to start the data transmission.
MODEM sends the acknowledgement of this request by making CTS low which will enable transmission logic of
8251.

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