G 04 LOGIC - MIXED - MODE13 1P8M FSG INTERCAP Ver.1.4 - P1 PDF

* BEGIN *
0.13um Logic and Mixed-Mode 1P8M FSG Process

Interconnect Capacitance Model
(Ver. 1.4_P. 1)
Single-Poly 8-Metal (1P8M)
P-Sub, Logic and Mixed-Mode Process
DSM NO. :
G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP
Total Pages :
30 (INCLUDING THIS COVER PAGE)
Approve Date : 2009/12/08
TECHNICAL INFORMATION CENTER

UNITED MICROELECTRONICS CORPORATION GROUP
No. 3 Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
Tel:+886-3-578-2258 Fax:+886-3-577-8271
ALL RIGHTS STRICTLY RESERVED ANY PORTION IN THIS DOCUMENT SHALL NOT BE
REPRODUCED COPIED OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION.
DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Ver:1.4 Phase:1 Approved Date: 12/08/2009
1. Contents
Page
1. Contents
2. Revision History
3. Interconnect Capacitance Model
4. Process Parameters
13
5. Capacitance Look-Up Table
25
Page: 2
UMC CONFIDENTIAL NO DISCLOSURE

2. Revision History:
Ver. Phase Approved
Date
From
To
Remark
(Purpose)
Original
0.1
02/27/2002
0.2
04/15/2002 1.best,worst cases definition

2.Process Parameters:thickness
contain typical, max&min
3.capacitance look-up
Tables:best case,worst
case(name&content)
1.minimum,maximum cases
definition
2.Process parameters:thickness
just contain typical
3.capacitance look-up
Tables:minimum case,maximum
case(name&content)
0.3
06/27/2002 1.clarify chapter3 Ctotal

definition:
a.3.1Ctotal is total capacitance
taking into consideration by
raphael simulation.
b.3.2Ctotal is total capacitance
raphael simulation.
2.color the two pictures of
chapter3.
3.add the dielectric parameter
table of typ. min.&max cases.
4.correct the raw data of file in
lookup table---capacitance
related to Al-RDL .(the layer of
IMD8D is not into calculation).
1.clarfy chapter3 Ctotal

definition:
a.3.1 Ctotal is total capacitance
Raphael simulation : capacitance
of center block to neighbor four
blocks and capacitance of center
block to bottom plane.
b.3.2 Ctotal is total capacitance
Raphael simulation : capacitance
of center block to neighbor four
blocks and capacitance of center
block to bottom plane and
topplane.
2.color the two pictures of
chapter3.
3.add the dielectric parameter
table of typ. min.&max cases.
4.correct the raw data of file in
lookup table---capacitance
related to Al-RDL .(the layer of
IMD8D is taking into calculation).
0.4
11/01/2002 1.4.1 Thickness, Width and Min. 1.Add metal width offset :
Spacing of Each Conductor
mask ---> wafer
Layer : Only provide the mask
M1
0.16
0.2
drawn value .
M2~M6
0.2
0.26
2.5. Capacitance look-up table : 2.5. The dimension in the files
The dimension in the files are the are the real wafer dimension .
dimension on the mask design.
Page: 3
1.
To match
the real
wafer and
model .

Ver. Phase Approved

Date
From
To
0.5
11/15/2002 1.
3.1 Ctotal
3.2 Ctotal
3.
5.Lookup table
1.
3.1 Add Ctotal =Csum+2*Cc2
3.2 Add Ctotal =Csum+2*Cc2
3.
5.Lookup table
The simulation has been
modified the process variation
into the data
0.5
12/10/2002 A.
A.
3.1/3.2 Ctotal definition
3.1/3.2 Ctotal definition
Ctotal=Csum+Cc2 : Ctotal is
Ctotal :Ctotal is total capacitance
total capacitance taking into
consideration by Raphael
Raphael simulation .
simulation : capacitance of
(including the two blocks that far
center block to neighbor four
from the center)
blocks and capacitance of center The difference between Csum
block to bottom plane.
and Ctotal is the effect of the
coupling capacitance from the
two blocks that far from the
B.
center.
3.3 space definition in Min,/Max. B.
case
3.3 space definition in Min,/Max.
Min.case
case
Space = (typical space) + (|width Minimum Case :
variation|)
minimum width = typical width - |
Max.case
variation |
Space = (typical space) (|width Space = Pitch minimum width
variation|)
Maximum Case:
maximum width = typical width +
| variation |
C.
Space = Pitch maximum width
C.
4.table in process parameter
4.table in process parameter:
change the table value to simple
equation
Width(on Si) = Drawing width +
bias
0.6
03/06/2003 (i) 4.2 Dielectric thickness

variation:
Gate Oxide 12.5%.
(ii) Capacitance look-up table is
not correct on simulation the
capacitance that related to
Al-RDL by missing one dielectric
layer between Al-RDL and
Metal8
Remark
(Purpose)
1.
To more
specify
Ctotal
definition
(i) 4.2 Dielectric thickness

variation:
Gate Oxide : Please refer to
each DRM-EDR as reference
(ii) Capacitance look-up table
update.
Page: 4

Ver. Phase Approved

Date
1.1
From
To
07/07/2003 5. Capacitance look-up table.
5. Capacitance look-up table.
Please refer to file

LG130_1P8M_GF_V061.ZIP
Please refer to file

LG130_1P8M_GF_V111.ZIP
LG130_1P8M_GF_V061.typ
LG130_1P8M_GF_V061.min
LG130_1P8M_GF_V061.max
LG130_1P8M_GF_V061.cmp
LG130_1P8M_GF_V111.typ
LG130_1P8M_GF_V111.min
LG130_1P8M_GF_V111.max
LG130_1P8M_GF_V111.cmp
4.1 Thickness
4.1 Thickness
Typ
1.2
Typ/Min/Max
07/29/2004 1.
1. G-04-LOGIC/MIXED_MODE
G-04-MIXED_MODE/RFCMOS 13-1P8M-FSG-INTERCAP
13-1P8M-MMC/FSG-INTERCAP
2.
G-04-LOGIC13-1P8MCU_FSG-INTERCAP
Page: 5
Remark
(Purpose)
Version
update for
one lot
reliability
Qual
OK.Only
change
version
no.,the
contents
are same
with V061
except 4.1
add
Thickness
Max/Min
data as
Q&RA's
request
In this
version,
the
document
includes
two
intercap
model as
A.
G-4A-LOG
IC/MIXED
_MODE13
-1P8M-M
MC/FSG/T
OP_META
L8K/L130
E-INTERC
AP
V1.2_P1
and B.
G-4B-MIX
ED_MOD
E/RFCMO
S13-1P8M
-MMC/FS
G/TOP_M
ETAL20K/
L130E-INT
ERCAP
V1.2_P1

Ver. Phase Approved

Date
1.3
From
To
Remark
(Purpose)
11/01/2004 1. There are not

1. Add two models as
1. Drawing
G-4C-LOGIC/MIXED_MODE13- G-4C-LOGIC/MIXED_MODE13- width 1X ~
1P8M-FSG/TOP_METAL8K/L13 1P8M-FSG/TOP_METAL8K/L13 4X are
0E-INTERCAP and
0E-INTERCAP and
considered
G-4D-MIXED_MODE/RFCMOS1 G-4D-MIXED_MODE/RFCMOS1 in this
3-1P8M-FSG/TOP_METAL20K/L 3-1P8M-FSG/TOP_METAL20K/L version.
130E-INTERCAP in this model. 130E-INTERCAP.
2. Add
2. In section 4.2: Field Oxide :
2. In section 4.2: Field Oxide :
WEE tables
10.0%.
Please refer to each DRM-EDR and
3. There is not the section 3.1
as reference.
verification
Scope.
3. Add the section 3.1 Scope.
plots into
4. Remove section 3.3 Process 4. Add the section 3.4 Corner
this
tolerance - Minimum Case and Methodology.
document.
Maximum Case Methodology.
5. Update for lookup tables of
3. In this
5. Lookup tables of G4A and
G4A and G4B.
version,
G4B.
6. Add section 3.5 Model
add G-4C
6. No section 3.5 Model
Verification Plots.
and G-4D
Verification Plots.
7. Add section 4.3 WEE table.
as
7. No section 4.3 WEE table.
8. In section 4.1: Revision the
G-4C-LOGI
8. In section 4.1: The tables of tables of G4A and G4B.
C/MIXED_
G4A and G4B.
9. In section 4.2: Modify the
MODE13-1
9. In section 4.2: Dielectric
description.
P8M-FSG/T
thickness varairion description. 10. In section 4.4: Add new cross OP_METAL
10. In section 4.4: Remove the section of G4A and G4B.
8K/L130E-I
cross sections of G4A and G4B. 11. In section 5: Add description NTERCAP
11. In section 5: No description for 1X width ~ 4X width lookup and
for 1X width ~ 4X width lookup table files.
G-4D-MIXE
table files.
D_MODE/R
FCMOS131P8M-FSG/
TOP_MET
AL20K/L13
0E-INTERC
AP.
Page: 6

Ver. Phase Approved

Date
1.4
12/08/2009
From
To
1.Add a new subset:

G-4E-LOGIC/MIXED_MODE131P7M-FSG/TOP_METAL8K/L13
0E-INTERCAP V1.4_P1
Page: 7
Remark
(Purpose)

3. Interconnect Capacitance Model

3.1 Scope
There are four intercap model subsets in this document as follows:
G-4A-LOGIC/MIXED_MODE13-1P8M-MMC/FSG/TOP_METAL8K/L130E-INTERCAP
G-4B-MIXED_MODE/RFCMOS13-1P8M-MMC/FSG/TOP_METAL20K/L130E-INTERCAP
G-4C-LOGIC/MIXED_MODE13-1P8M-FSG/TOP_METAL8K/L130E-INTERCAP
G-4D-MIXED_MODE/RFCMOS13-1P8M-FSG/TOP_METAL20K/L130E-INTERCAP
G-4E-LOGIC/MIXED_MODE13-1P7M-FSG/TOP_METAL8K/L130E-INTERCAP
The subsets are classfied by with/without MMC and top metal thickness = 8K/20K for Logic/Mixed-Mode/RF
applications as follows.
G-4A: with MMC, with tk=8K top metal.
G-4B: with MMC, with tk=20K top metal.
G-4C: without MMC, with tk=8K top metal.
G-4D: without MMC, with tk=20K top metal.
G-4E: without MMC, with tk=8K top metal.
3.2 "Array Above A Ground Plane" Model
Interconnect capacitances are summarized to look-up tables for different kinds of conductor spacing.
The sum capacitance (Csum) can be derived from Ca, Cf and Cc.
Csum = Ca + 2*Cf + 2*Cc (unit: fF/um)
where
W : Conductor width (unit: um).
S : Conductor spacing (unit: um).
Ca : Parallel plate area capacitance (unit: fF/um).
Cf : Fringing capacitance to bottom plane (unit: fF/um/side).
Cc : Coupling capacitance to adjacent conductor (unit: fF/um/side).
Ctotal = Csum + 2*Cc2 (unit: fF/um)
where
Cc2 : Coupling capacitance to outer conductor (unit: fF/um/side).
The difference between Csum and Ctotal is the effect of the coupling capacitance from the
two blocks that far from the center.
Page: 8

3.3 "Array Between Ground Planes" Model

The sum capacitance (Csum) can be derived from Catop, Cabot, Csu, Csd and Cc.
Csum = (Catop + Cabot) + 2*( Csu + Csd ) + 2*Cc (unit: fF/um)
where
W
: Conductor width (unit: um).
S
: Conductor spacing (unit: um).
Catop : Capacitance of center conductor to top ground plane (unit: fF/um).
Cabot : Capacitance of center conductor to bottom ground plane (unit: fF/um).
Csu : Side-wall up capacitance coefficient (unit: fF/um/side).
Csd : Side-wall down capacitance coefficient (unit: fF/um/side).
Cc
: Coupling capacitance to adjacent conductor (unit: fF/um/side)
Ctotal = Csum + 2*Cc2 (unit: fF/um)
where
Cc2 : Coupling capacitance to outer conductor (unit : fF/um/side).
The difference between Csum and Ctotal is the effect of the coupling capacitance from the two blocks that far
from the center.
Page: 9

3.4 Corner Model Methodology

The corner models (typical case, minimum case and maximum case) are based on a fixed pitch and the
variations of metal width and top/intra/bottom dielectric thickness. Metal width is separated to typical metal width,
minimum metal width and maximum metal width. The top/intra/bottom dielectric thicknesses are separated to
typical top/intra/bottom dielectric thickness, minimum top/intra/bottom dielectric thicknesses and maximum
top/intra/bottom dielectric thicknesses. So, the metal width and dielectric thickness for each corner model are
listed as follows:
A. Typical Case:
1. Metal Width : typical metal width

2. Dielectric Thickness : typical thicknesses of top/intra/bottom dielectric
B. Minimum Case: 1. Metal Width : minimum metal width
2. Dielectric Thickness : minimum thicknesses of intra dielectric,
maximum thicknesses of top/bottom dielectric
C. Maximum Case: 1. Metal Width : maximum metal width
2. Dielectric Thickness : maximum thicknesses of intra dielectric,
minimum thicknesses of top/bottom dielectric
Where typical metal width = physical metal width
minimum metal width = physical metal width metal width variation
maximum metal width = physical metal width + metal width variation
typical dielectric thickness = physical dielectric thickness
minimum dielectric thickness = physical dielectric thickness dielectric thickness variation
maximum dielectric thickness = physical dielectric thickness + dielectric thickness variation
Page: 10

Dielectric thickness variation is calculated by Array Between Ground Planes structures of metal groups (M1
metal, M2~M6 metal ). For this 0.13um intercap model, the structures are M1 between Poly/M2, M3 between
M2/M4 and M7 between M6/M8. Each structure of metal group can determine a total.
For example of M3 between M2/M4, dielectric layers between M2 and M4 can be separated to 7 dielectric
layers. T1 ~ T7 are represented for each dielectric thickness respectively. So, total for the structure of M3
between M2/M4 is described as following equation.
total =
(Tj process variation)
The dielectric thickness variation of M3 between M2/M4 structure is described as following equation.
Dielectric thickness variation of M3 between M2/M4 = total
Tj process variation
(Tj process variation)
j
Then the dielectric thickness variation of M1 between Poly/M2 and M7 between M6/M8 structures can be
calculated as dielectric thickness variation of M3 between M2/M4 structure.
Finally, the dielectric thickness variation for this intercap model is an average value of dielectric thickness
variations of M1 between Poly/M2, M3 between M2/M4 and M7 between M6/M8 structures. For this intercap
model, the dielectric thickness variation is about +/- 9.65%.
Page: 11

3.5 Model Verification Plots

The simulation result obtained from Raphael are plotted together with the measurement result for comparison.
The measurement result are based on 4 wafers mapping data. The wafers are #03, #13, #14 and #24 of QG15L
from Fab8D. The Wd and Sd in the plots refer to drawing width and drawing space respectively.
(1) Metal1 between Poly1 and Metal2:
Page: 12

(2) Metal3 between Metal2 and Metal4:
Page: 13

(3) Metal7 between Metal6 and Metal8:
Page: 14

4. Process Parameters
4.1 Thickness and Width of Each Conductor Layer
A. G-4A-LOGIC/MIXED_MODE13-1P8M-MMC/FSG/TOP_METAL8K/L130E-INTERCAP V1.3_P1
Conductor
poly1
metal1
metal2
metal3
metal4
metal5
metal6
metal7
metal8
MMCBP
MMCTP
Al-RDL
Typ
0.160
0.320
0.320
0.320
0.320
0.320
0.320
0.800
0.800
0.090
0.060
1.200
Thinkness (um)
Min
0.1446
0.2891
0.2891
0.2891
0.2891
0.2891
0.2891
0.7228
0.7228
NA
NA
1.0842
Max
0.1754
0.3509
0.3509
0.3509
0.3509
0.3509
0.3509
0.8772
0.8772
NA
NA
1.3158
Width (um)
Physical metal width
Metal width variation
drawing width
0.012
drawing width + W
0.0201
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.0368
drawing width + W
0.0368
drawing width
0.510
drawing width
0.390
drawing width
0.300
Note: The value of W is based on WEE table of each conductor.

B. G-4B-MIXED_MODE/RFCMOS13-1P8M-MMC/FSG/TOP_METAL20K/L130E-INTERCAP V1.3_P1
Conductor
Thinkness (um)
Width (um)
Typ
Min
Max
poly1
0.160
0.1446
0.1754
drawing width
0.012
metal1
0.320
0.2891
0.3509
drawing width + W
0.0201
metal2
0.320
0.2891
0.3509
drawing width + W
0.02607
metal3
0.320
0.2891
0.3509
drawing width + W
0.02607
metal4
0.320
0.2891
0.3509
drawing width + W
0.02607
metal5
0.320
0.2891
0.3509
drawing width + W
0.02607
metal6
0.320
0.2891
0.3509
drawing width + W
0.02607
metal7
0.800
0.7228
0.8772
drawing width + W
0.0368
metal8_20K
2.000
1.807
2.193
drawing width
0.15
MMCBP
0.090
NA
NA
drawing width
0.510
MMCTP
0.060
NA
NA
drawing width
0.390
Al-RDL
1.200
1.0842
1.3158
drawing width
0.300
Page: 15

C. G-4C-LOGIC/MIXED_MODE13-1P8M-FSG/TOP_METAL8K/L130E-INTERCAP V1.3_P1
Conductor
poly1
metal1
metal2
metal3
metal4
metal5
metal6
metal7
metal8
Al-RDL
Typ
0.160
0.320
0.320
0.320
0.320
0.320
0.320
0.800
0.800
1.200
Thinkness (um)
Min
0.1446
0.2891
0.2891
0.2891
0.2891
0.2891
0.2891
0.7228
0.7228
1.0842
Max
0.1754
0.3509
0.3509
0.3509
0.3509
0.3509
0.3509
0.8772
0.8772
1.3158
Width (um)
drawing width
0.012
drawing width + W
0.0201
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.0368
drawing width + W
0.0368
drawing width
0.300

D. G-4D-MIXED_MODE/RFCMOS13-1P8M-FSG/TOP_METAL20K/L130E-INTERCAP V1.3_P1
Conductor
poly1
metal1
metal2
metal3
metal4
metal5
metal6
metal7
metal8_20K
Al-RDL
Typ
0.160
0.320
0.320
0.320
0.320
0.320
0.320
0.800
2.000
1.200
Thinkness (um)
Min
0.1446
0.2891
0.2891
0.2891
0.2891
0.2891
0.2891
0.7228
1.807
1.0842
Max
0.1754
0.3509
0.3509
0.3509
0.3509
0.3509
0.3509
0.8772
2.193
1.3158
Width (um)
drawing width
0.012
drawing width + W
0.0201
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.02607
drawing width + W
0.0368
drawing width
0.15
drawing width
0.300

E. G-4E-LOGIC/MIXED_MODE13-1P7M-FSG/TOP_METAL8K/L130E-INTERCAP V1.4_P1
Conductor
poly0
poly1
metal1
metal2
metal3
metal4
metal5
metal6
metal7
metal8
AL-RDL
Typ
0.08
0.16
0.32
0.32
0.32
0.32
0.80
0.80
0.80
0.80
1.20
Thickness (um)
Min
0.07
0.14
0.29
0.29
0.29
0.29
0.72
0.72
0.72
0.72
1.08
Max
0.09
0.18
0.35
0.35
0.35
0.35
0.88
0.88
0.88
0.88
1.32
Width (um)
Physical width
drawing width
drawing width
drawing width +W
drawing width +W
drawing width +W
drawing width +W
drawing width +W
drawing width +W
drawing width +W
drawing width +W
drawing width
Variation
0.016
0.012
0.0201
0.02607
0.02607
0.02607
0.0368
0.0368
0.0368
0.0368
0.300
Page: 16

4.2 Dielectric thickness variation

Dielectric thickness variation is determined by process variation of each dielectric layer. The process variations for
dielectric layers are listed as follows.
Process variation:
Gate Oxide : Please refer to each DSM-EDR as reference.
Field Oxide : Please refer to each DSM-EDR as reference.
Other Dielectric layer : 20.0%.
The final dielectric thickness variation based on above process variation can be determined as about +/- 9.65%.
Please refer to 3.4 Corner Model Methodology for detailed calculation.
4.3 WEE table
The width bias (W) of each conductor width is listed as following Width Enlargement Effect (WEE) tables. The
tables include drawing width (Wd) and drawing space (Sd) for 1X rule ~ 4X rule of each metal layer.
(1) Metal1:
Sd \ Wd
0.16
0.32
0.48
0.64
0.16
0.041
0.04
0.033
0.033
0.32
-0.024
0.001
0.001
0.001
0.48
-0.032
0.001
0.001
0.001
0.64
-0.032
0.001
0.001
0.001
0.6
0.04
0.052
0.052
0.05
0.8
0.04
0.044
0.041
0.039
(2) Metal2 ~ Metal6:(for G-4A ~ G-4D)

Metal2 ~Metal4:(only for G-4E)
Sd \ Wd
0.2
0.4
0.6
0.8
0.2
0.0607
0.05
0.052
0.05
0.4
0.0415
0.045
0.043
0.042
(3) Metal7 and Metal8 (Not include tk=20K top metal):(for G-4A ~ G-4D)
Metal5 ~ Metal7 (only for G-4E)
Sd \ Wd
0.4
0.8
1.2
1.6
0.4
-0.032
-0.0517
-0.0517
-0.0517
0.8
-0.0517
-0.0517
-0.0517
-0.0517
1.2
-0.0517
-0.0517
-0.0517
-0.0517
1.6
-0.0517
-0.0517
-0.0517
-0.0517
Page: 17

4.4 Cross Section :

Part (A1):
Page: 18

Part (A2):
Page: 19

Part (B1):
Page: 20

Part (B2):
Page: 21

C. G-4C-LOGIC/MIXED_MODE13-1P8M-FSG/TOP_METAL8K/L130E-INTERCAP V1.3_P1
Part (C1):
Page: 22

Part (C2):
Page: 23

D. G-4D-MIXED_MODE/RFCMOS13-1P8M-FSG/TOP_METAL20K/L130E-INTERCAP V1.3_P1
Part (D1):
Page: 24

Part (D2):
Page: 25

E. G-4E-LOGIC/MIXED_MODE13-1P7M-FSG/TOP_METAL8K/L130E-INTERCAP V1.4_P1
Page: 26

MMC cross section:
MMC Portion
700A = 7
350A = 7
700A = 7
MMCTP 600A
MMCBP 900A
350 = 4.1
1000A = 7
500A =4.1
Page: 27

5. Capacitance Look-Up Table.

All dimensions in look-up table are based on drawing size and the simulation has been
considered the process variation.
Please refer to files:
G-4A-LOGIC_MM13-1P8M-FSG-INTERCAP_Wd[X]X_V131.typ : typical case
G-4A-LOGIC_MM13-1P8M-FSG-INTERCAP_Wd[X]X_V131.min : minimum case
G-4A-LOGIC_MM13-1P8M-FSG-INTERCAP_Wd[X]X_V131.max : maximum case
G-4A-LOGIC_MM13-1P8M-FSG-INTERCAP_Wd[X]X_V131.cmp : comparison between typical, minimum
and maximum cases.
Note: [X] means 1, 2, 3 or 4.
G-4B-MM_RF13-1P8M-FSG-INTERCAP_Wd[X]X_V131.typ : typical case
G-4B-MM_RF13-1P8M-FSG-INTERCAP_Wd[X]X_V131.min : minimum case
G-4B-MM_RF13-1P8M-FSG-INTERCAP_Wd[X]X_V131.max : maximum case
G-4B-MM_RF13-1P8M-FSG-INTERCAP_Wd[X]X_V131.cmp : comparison between typical, min and max
cases.
C.G-4C-LOGIC/MIXED_MODE13-1P8M-FSG/TOP_METAL8K/L130E-INTERCAP V1.3_P1
G-4C-LOGIC_MM13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.typ : typical case
G-4C-LOGIC_MM13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.min : minimum case
G-4C-LOGIC_MM13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.max : maximum case
G-4C-LOGIC_MM13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.cmp : comparison between typical,
min and max cases.
D.G-4D-MIXED_MODE/RFCMOS13-1P8M-FSG/TOP_METAL20K/L130E-INTERCAP V1.3_P1
G-4D-MM_RF13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.typ : typical case
G-4D-MM_RF13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.min : minimum case
G-4D-MM_RF13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.max : maximum case
G-4D-MM_RF13-1P8M-FSG-woMMC-INTERCAP_Wd[X]X_V131.cmp : comparison between typical, min
and max cases.
E.G-4E-LOGIC/MIXED_MODE13-1P7M-FSG/TOP_METAL8K/L130E-INTERCAP V1.4_P1
G-4E-LOGIC_MM13-1P7M-FSG-woMMC-INTERCAP_Wd[X]X_V141.typ
G-4E-LOGIC_MM13-1P7M-FSG-woMMC-INTERCAP_Wd[X]X_V141.min
G-4E-LOGIC_MM13-1P7M-FSG-woMMC-INTERCAP_Wd[X]X_V141.max
G-4E-LOGIC_MM13-1P7M-FSG-woMMC-INTERCAP_Wd[X]X_V141.cmp
min and max cases.
Page: 28
: typical case
: minimum case
: maximum case
: comparison between typical,

MMC Structure
Type1
Page: 29

Type2
* END *
Page: 30

G 04 LOGIC - MIXED - MODE13 1P8M FSG INTERCAP Ver.1.4 - P1 PDF

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

G 04 LOGIC - MIXED - MODE13 1P8M FSG INTERCAP Ver.1.4 - P1 PDF

Загружено:

Авторское право:

Доступные форматы

* BEGIN *

0.13um Logic and Mixed-Mode 1P8M FSG Process

30 (INCLUDING THIS COVER PAGE)

Approve Date : 2009/12/08

TECHNICAL INFORMATION CENTER

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

3. Interconnect Capacitance Model

5. Capacitance Look-Up Table

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

04/15/2002 1.best,worst cases definition

06/27/2002 1.clarify chapter3 Ctotal

1.clarfy chapter3 Ctotal

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Ver. Phase Approved

03/06/2003 (i) 4.2 Dielectric thickness

(i) 4.2 Dielectric thickness

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Ver. Phase Approved

07/07/2003 5. Capacitance look-up table.

5. Capacitance look-up table.

Please refer to file

Please refer to file

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Ver. Phase Approved

11/01/2004 1. There are not

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Ver. Phase Approved

1.Add a new subset:

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

3. Interconnect Capacitance Model

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

3.3 "Array Between Ground Planes" Model

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

3.4 Corner Model Methodology

1. Metal Width : typical metal width

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

(Tj process variation)

Dielectric thickness variation of M3 between M2/M4 = total

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

3.5 Model Verification Plots

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

(2) Metal3 between Metal2 and Metal4:

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

(3) Metal7 between Metal6 and Metal8:

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Note: The value of W is based on WEE table of each conductor.

UMC CONFIDENTIAL NO DISCLOSURE

DSM NO: G-04-LOGIC/MIXED_MODE13-1P8M-FSG-INTERCAP

Note: The value of W is based on WEE table of each conductor.

Note: The value of W is based on WEE table of each conductor.