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Joseph E Stubbs, PE
EtherCAT Technology Group
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Agenda
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DCs definition
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Functional Principles
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Slave Device
Slave Device
EtherCAT Slave
Controller
EtherCAT Slave
Controller
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Master
Cable
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IRQ
Sync1 / Latch1
Sync0 / Latch0
FMMU n
Sync / Latch Unit
SyncMan
DC
Control
Port 1
Port 2
Port 3
Offset
System Time
Delay
Distributed Clocks
Mag
PHY
RJ45
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PHY
Mag
RJ45
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EtherCAT Frame
Processing Direction
EtherCAT Frame
Forwarding Direction
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Registers:
Receive Time Port 0
Receive Time Port 1
Receive Time Port 2
Receive Time Port 3
System Time Delay
(ADO: 0x0900:0x0903)
(ADO: 0x0904:0x0907)
(ADO: 0x0908:0x090B)
(ADO: 0x090C:0x090F)
(ADO: 0x0928:0x092B)
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This value is
distributed by
the master
stored in the
slave for drift
compensation
calculations
later.
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IPC
S
S
(15)
Registers:
System Time Offset
(ADO: 0x0920:0x927, small systems 0x0920:0x0923)
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Ref
S
IPC
S
S
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Offset Compensation
Registers:
System Time Offset
(ADO: 0x0920:0x927, small systems 0x0920:0x0923)
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This value is
distributed by
the master
and written to
each slave in
order to bring
all local times
to the same
exact time.
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IPC
S
S
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DC Control
Write access to System Time compares
received Time with local time
t = (tLocal time + tOffset - tPropagationDelay) tReceived System Time
If (t > 0) then decelerate local clock (each tick counts as
less time)
else if (t < 0) accelerate local clock (each tick counts as
more time)
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Drift Compensation
Master commands the Reference clock to distribute its local
time to all nodes occasionally.
Ref
S
The frequency of
issuing the RMW
command
determines the
amount of drift
allowed in the
system clocks
IPC
S
S
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Simultaneousness:
~15 ns
Jitter: ~ +/-20ns
Interrupt
Node 300
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PDI IRQ
Sync0
Sync1
Sync Unit
Latch Unit
DC
Control
Offset
System Time
Delay
Distributed Clocks
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Latch0
Latch1
Sync Unit
Latch Unit
DC
Control
Offset
System Time
Delay
Distributed Clocks
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1 + Tx 1 +Ty
1 + Tz
1 + T1 1 +T2
1 + T3
IN
Latch
Timestamp
Constant
OUT
Timestamp
?
OUT
Classical
Controls
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Constant
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PDI IRQ
Sync0
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An ESC can not only be used as a standalone unit, it also has interfaces for
communicating with other electronic units
such as a microcontroller or other driver
circuitry.
Communication via these interfaces can
also be controlled via distributed clocks in
order to ensure synchronous, highprecision sampling of input parameters, or
cyclic interrupts based on a multiple of the
base scan rate.
Examples for this use include interfacing
to a microprocessor controlling a power
drive, electronic shaft encoder analyzer,
or data acquisition slaves for condition
monitoring.
Sync Unit
Latch Unit
DC
Control
Offset
System Time
Delay
Distributed Clocks
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10.12.2013
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Summary
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Please visit
www.ethercat.org
for more information
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