AMBA AXI

The AXI protocol is burst-based. The communication between master and slave
takes place on read and write channels. This protocol defines 5 channel, namely,
write address, write data, write response, read address and read data channels.
AXI signals
Write address channel
signals
AWID[3:0]
AWVALID
AWREADY
AWLEN[3:0]
AWSIZE[2:0]
AWBURST[1:0]
AWADDR[31:0]
AWPROT
AWCACHE
AWLOCK

Write data channel

signals
WID[3:0]
WVALID
WREADY
WSTRB[7:0]
WDATA[63:0]
WLAST

Read address channel signals

ARID[3:0]
ARVALID
ARREADY
ARLEN[3:0]
ARSIZE[2:0]
ARBURST[1:0]
ARADDR[31:0]
ARPROT
ARCACHE
ARLOCK

Write response
channel signals
BID[3:0]
BVALID
BREADY
BRESP

Read data channel signals

RID[3:0]
RVALID
RREADY
RDATA[63:0]
RLAST
RRESP[1:0]

The VALID READY relation

The data transfer happens by the handshake between VALID and READY signals.
The master asserts the VALID signal only when it drives the address and control
signals information. This signal remain asserted until the slave responds with READY
signal.
|--------------------------------|
AWVALID -------|

|-----------------------|-----------------|

AWREADY-----------------------|

|--------------------------

The default value of READY can be high or low. The recommended default value is
high, in that case, only one cycle would be sufficient for the master to drive the
VALID signal.

|-------------------|
AWVALID ---------------------------------------|

|------------------------

|---------------------------------------------------------------------AWREADY---------|
A default READY value of low is also possible although it is not recommended. This
will make the transfer to take atleast two cycle, one to assert VALID and another to
assert READY.
To prevent deadlock situation between the handshake signals(ie, valid is asserted
when ready is high or ready will be asserted when valid is high), the following
dependency between valid and ready must be followed.
1. The VALID signals should not depend on READY signal. When initiating
transfer, the VALID signal is asserted with address and control signals placed
on the bus and remains asserted until the READY is asserted if the READY is
0. If READY is high before VALID is asserted, the VALID can go low one cycle
after valid address and control signals driven.
2. The READY signal can wait for VALID signal. The READY signal can be 0 by
default and it can go high after the VALID is high. But in this case, atleast two
cycles are needed.

The AXI protocol is burst based. The master initiates a burst of transactions with
start address of transfer. It is responsibility of slave to calculate the addresses of
remaining transfers. The address must not cross 4K boundary.
In case of AHB, the master calculates the address of each transfer in the burst. The
address must not cross 1KB boundary.
Burst length:
AWLEN and ARLEN specify the number of data transfers that occur in each burst.
Each burst can have 1 to 16 transfers.
For wrapping bursts, the burst length has to be 2, 4, 8 or 16.
In AHB, the arbiter can terminate a burst early than it is completed. In case of AXI,
no component should terminate the burst to reduce the number of data transfers.
For write data transfers, the Master can invalidate the transfer by making the
WSTRB to 0, but it should not terminate the burst early. It has to do the number of
data transfers as indicated by the burst length.

Burst size:
The burst size can be from 1 byte to 128 bytes (2^0 2^7).
For data transfers with burst size > data bus width is not allowed.
For fixed address burst, the address and strobe signals remain fixed for the burst.
For eg, for fixed burst of 4 transfers with transfer size=4 bytes, data bus width is 64
bits, if the address of transfer is 0x14 then the write strobe is 0xf0 and if the
address of transfer is 0x18 then the write strobe is 0x0f.
For incrementing or wrapping bursts with transfer sizes narrower than the data bus,
the data transfers are on different byte lanes for each beat of the burst.
For eg, for incrementing burst of 8 beats with transfer size = 2 bytes, data bus
width is 64 bits, start address of burst is 0x26 the write strobe will be 0xc0, 0x03,
0x0c, 0x30, 0xc0, 0x03, 0x0c, 0x30.
Burst type:
Three types of burst are supported. Fixed(00), Increment(01), Wrapping(10).
Fixed The address for each transfer in the burst remains the same. It is suitable for
applications where writing or emptying data to or from a same address location
such as FIFO write/read.
Incrementing burst The address of each transfer in the burst is an increment of
previous transfer and increment value depends on the size of transfer.
Wrapping burst It is similar to incrementing burst, but the address will wrap
around when the address boundary is reached. Two restrictions apply in this burst
type,
1. The start address of burst should be aligned to the size of transfer(unaligned
address is not supported with wrapping burst).
2. The burst length has to be 2, 4, 8 or 16.

Atomic accesses:
To enable the implementation of atomic access, the AWLOCK or ARLOCK signals
provide exclusive access and locked access.
AWLOCK/ARLOCK indicates normal access(00), exclusive access(01), locked
access(10).
Exclusive access:
The exclusive access mechanism enables the implementation of semaphore type
operations without requiring the bus to remain locked for a particular master for the
duration of operation. The RRESP and BRESP indicate the success or failure of
exclusive access (EXOKAY).
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The basic process for an exclusive access is,

-

The master performs an exclusive read from an address location

At some time later, the master attempts to complete the exclusive operation
by performing an exclusive write to the same address location.
The exclusive write access of the master is signaled as,
o Successful if no other master has written to that address location
between read and write accesses
o Failed if that address location is written by another master between
read and write access. In this case, the address location is not updated.

Locked access:
When a master sets the ARLOCK and AWLOCK to locked access, the interconnect
must ensure that only that master is allowed to access the slave region until an
unlocked transfer from that master completes.
When a master performs a sequence of locked transfers, it must ensure that it has
no outstanding transfers waiting to complete. Since the locked transfer forces the
arbiter to lock the following transaction, the locked sequence must complete with a
transfer that removes the lock.

AXI responses:
For every AXI transfer, there is a response that indicates the status of transfer. The
response can be OKAY, EXOKAY, SLVERR or DECERR.
OKAY indicates the normal access is successful. Can also be used to indicate the
exclusive access failure.
EXOKAY indicates either read or write operation of exclusive access is successful.
SLVERR indicates that the access reached the slave successfully, but the slave
wishes to return an error condition to the originating master.
DECERR This response is related to the interconnect component to indicate that a
slave does not exist at the address location
For the write operation, there is only one response for the entire transfer of the
burst.
For read operation, the slave can give different response for different transfers
within the burst. For eg, for a read of 16 transfers, the slave can return OKAY
response for 15 transfers and a SLVERR response for one transfer.
The protocol requires that the required number of transfers must be completed
even if error response is reported.

Ordering model
4

AXI protocol enables out of order transaction completion and support for multiple
outstanding addresses.
The ability to issue multiple outstanding transactions means that the master can
issue multiple transaction addresses without waiting for earlier transaction
completion. This enables parallel processing of transactions and increases the
system throughput.
The ability to complete transaction out of order means that the transactions to
faster memory regions can complete without waiting for earlier transactions to
slower memory regions.
Ordering restrictions:
-

Transactions from different masters have no ordering restrictions. They can

complete in any order.
Transactions from the same master, but with different ID values, have no
ordering restrictions. They can complete in any order.
The data for a sequence of write transactions with the same AWID value
must complete in the same order that the master issued the addresses in.
The data for a sequence of read transactions with the same ARID value must
be returned in order that:
o when reads with the same ARID are from the same slave then the
slave must ensure that the read data returns in the same order that
the addresses are received.
o when reads with the same ARID are from different slaves, the
interconnect must ensure that the read data returns in the same order
that the master issued the addresses in.
There are no ordering restrictions between read and write transactions with
the same AWID and ARID. If a master requires an ordering restriction then it
must ensure that the first transaction is fully completed before the second
transaction is issued.

Unaligned transfers:
Usually when performing a burst of transactions, the start address of burst will be
aligned with the size of the transfer. There are cases, where the start address does
not align to the size of transfer.
For eg, when doing a write transfer burst with a size of 4 bytes, the start address
can be 0x32 which is not aligned to 4 byte boundary.
In case of unaligned start address, the slave is not needed to take any care. It is the
master that drives the correct WSTRB signal during this unaligned transfer.
For a transfer size of 4 bytes, 8 beat burst on an 8-byte width data bus, the starting
address is 0x32. For incrementing burst, the address and strobe signals will be as,
0x32 0x0C,
0x34 0xF0,
0x38 0x0F
0x3C 0xF0
0x40 0x0F
0x44 0xF0
0x48 0x0F
5

0x4C 0xF0