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AD8196
FEATURES
AD8196
I2C_SDA
I2C_SCL
I2C_ADDR
CONFIG
INTERFACE
CONTROL
LOGIC
VTTI
VTTO
IP_B[3:0]
IN_B[3:0]
SWITCH
CORE
PE
EQ
OP[3:0]
ON[3:0]
HIGH SPEED
VTTI
AUX_A[3:0]
4
4
AUX_B[3:0]
BUFFERED
SWITCH
CORE
LOW SPEED
AUX_COM[3:0]
UNBUFFERED
06470-001
IP_A[3:0]
IN_A[3:0]
BIDIRECTIONAL
Figure 1.
TYPICAL APPLICATION
HDTV SET
HDMI
RECEIVER
SET-TOP BOX
DVD PLAYER
AD8196
01:18
06470-002
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1.
2.
3.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD8196
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Reset ............................................................................................. 14
Write Procedure.......................................................................... 14
Typical Application........................................................................... 1
Read Procedure........................................................................... 15
Switching/Update Delay............................................................ 15
Configuration Registers................................................................. 16
Specifications..................................................................................... 3
ESD Caution.................................................................................. 5
Pinout........................................................................................... 18
Introduction ................................................................................ 12
Input Channels............................................................................ 12
REVISION HISTORY
1/07Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8196
SPECIFICATIONS
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =
1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Bit Error Rate (BER)
Added Deterministic Jitter
Added Random Jitter
Differential Intrapair Skew
Differential Interpair Skew 1
EQUALIZATION PERFORMANCE
Receiver (Highest Setting) 2
Transmitter (Highest Setting) 3
INPUT CHARACTERISTICS
Input Voltage Swing
Input Common-Mode Voltage (VICM)
OUTPUT CHARACTERISTICS
High Voltage Level
Low Voltage Level
Rise/Fall Time (20% to 80%)
INPUT TERMINATION
Resistance
AUXILIARY CHANNELS
On Resistance, RAUX
On Capacitance, CAUX
Input/Output Voltage Range
POWER SUPPLY
AVCC
QUIESCENT CURRENT
AVCC
VTTI
VTTO
Conditions/Comments
Min
NRZ
PRBS 223 1
DR 2.25 Gbps, PRBS 27 1, EQ = 12 dB
2.25
Max
Unit
Gbps
109
At output
At output
25
1
1
40
ps (p-p)
ps (rms)
ps
ps
12
6
dB
dB
Differential
150
AVCC 800
1200
AVCC
mV
mV
AVCC 10
AVCC 600
75
AVCC + 10
AVCC 400
200
mV
mV
ps
135
Single-ended
50
100
8
AMUXVCC
pF
V
DVEE
Operating range
3.3
3.6
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
Input termination on 4
Output termination on, no pre-emphasis
Output termination on, maximum
pre-emphasis
30
53
98
5
36
73
40
60
108
40
40
80
45
66
120
54
44
88
mA
mA
mA
mA
mA
mA
7
0.01
10
0.1
mA
mA
115
411
754
271
574
936
364
664
1057
mW
mW
mW
200
1.5
ms
s
ns
DVCC
AMUXVCC
POWER DISSIPATION
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
TIMING CHARACTERISTICS
Switching/Update Delay
Typ
Rev. 0 | Page 3 of 24
AD8196
Parameter
SERIAL CONTROL INTERFACE 5
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Conditions/Comments
Min
Typ
Max
2
0.8
2.4
0.4
Unit
V
V
V
V
Differential interpair skew is measured between the TMDS pairs of a single link.
AD8196 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
4
Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI link is deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
5
The AD8196 is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
2
3
Rev. 0 | Page 4 of 24
AD8196
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
AVCC to AVEE
DVCC to DVEE
DVEE to AVEE
VTTI
VTTO
AMUXVCC
Internal Power Dissipation
High Speed Input Voltage
High Speed Differential
Input Voltage
Low Speed Input Voltage
I2C Logic Input Voltage
Storage Temperature
Range
Operating Temperature
Range
Junction Temperature
Rating
3.7 V
3.7 V
0.3 V
AVCC + 0.6 V
AVCC + 0.6 V
5.5 V
4.62 W
AVCC 1.4 V < VIN < AVCC + 0.6 V
2.0 V
JA
27
JC
2.1
Unit
C/W
40C to +85C
150C
ESD CAUTION
Rev. 0 | Page 5 of 24
AD8196
56
55
54
53
52
51
50
49
48
47
46
45
44
43
AUX_A0
AUX_A1
AUX_A2
AUX_A3
DVEE
AUX_COM0
AUX_COM1
AUX_COM2
AUX_COM3
AMUXVCC
AUX_B0
AUX_B1
AUX_B2
AUX_B3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN 1
INDICATOR
AD8196
TOP VIEW
(Not to Scale)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVCC
IP_B3
IN_B3
AVEE
IP_B2
IN_B2
VTTI
IP_B1
IN_B1
AVCC
IP_B0
IN_B0
AVEE
I2C_SDA
NOTES
1. THE AD8196 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO
MEET THERMAL SPECIFICATIONS.
06470-003
DVCC
ON0
OP0
VTTO
ON1
OP1
DVCC
ON2
OP2
VTTO
ON3
OP3
RESET
I2C_SCL
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AVCC
IN_A0
IP_A0
AVEE
IN_A1
IP_A1
VTTI
IN_A2
IP_A2
AVCC
IN_A3
IP_A3
AVEE
I2C_ADDR
Mnemonic
AVCC
IN_A0
IP_A0
AVEE
IN_A1
IP_A1
VTTI
IN_A2
IP_A2
IN_A3
IP_A3
I2C_ADDR
DVCC
ON0
OP0
VTTO
ON1
OP1
ON2
OP2
ON3
OP3
RESET
I2C_SCL
I2C_SDA
IN_B0
IP_B0
EE
AA
EA
Type 1
Power
HS I
HS I
Power
HS I
HS I
Power
HS I
HS I
HS I
HS I
Control
Power
HS O
HS O
Power
HS O
HS O
HS O
HS O
HS O
HS O
Control
Control
Control
HS I
HS I
Description
Positive Analog Supply. 3.3 V nominal.
High Speed Input Complement.
High Speed Input.
Negative Analog Supply. 0 V nominal.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
I2C Address LSB.
Positive Digital Power Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Configuration Registers Reset. This pin is normally pulled up to DVCC.
I2C Clock.
I2C Data.
High Speed Input Complement.
High Speed Input.
Rev. 0 | Page 6 of 24
AD8196
Pin No.
34
35
37
38
40
41
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
Mnemonic
IN_B1
IP_B1
IN_B2
IP_B2
IN_B3
IP_B3
AUX_B3
AUX_B2
AUX_B1
AUX_B0
AMUXVCC
AUX_COM3
AUX_COM2
AUX_COM1
AUX_COM0
DVEE
AUX_A3
AUX_A2
AUX_A1
AUX_A0
Type 1
HS I
HS I
HS I
HS I
HS I
HS I
LS I/O
LS I/O
LS I/O
LS I/O
Power
LS I/O
LS I/O
LS I/O
LS I/O
Power
LS I/O
LS I/O
LS I/O
LS I/O
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Positive Auxiliary Switch Supply. 5 V typical.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Negative Digital and Auxiliary Switch Power Supply. 0 V nominal.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Rev. 0 | Page 7 of 24
AD8196
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =
1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, pattern = PRBS 27 1, data rate = 2.25 Gbps, unless otherwise noted.
HDMI CABLE
AD8196
DIGITAL
PATTERN
GENERATOR
SERIAL DATA
ANALYZER
EVALUATION
BOARD
TP1
TP2
TP3
06470-004
06470-007
250mV/DIV
06470-005
250mV/DIV
06470-008
06470-006
250mV/DIV
0.125UI/DIV AT 2.25Gbps
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Rev. 0 | Page 8 of 24
AD8196
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =
1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, pattern = PRBS 27 1, data rate = 2.25 Gbps, unless otherwise noted.
HDMI CABLE
AD8196
DIGITAL
PATTERN
GENERATOR
SERIAL DATA
ANALYZER
EVALUATION
BOARD
TP1
TP2
TP3
06470-009
06470-012
250mV/DIV
06470-010
250mV/DIV
06470-013
06470-011
250mV/DIV
0.125UI/DIV AT 2.25Gbps
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Rev. 0 | Page 9 of 24
AD8196
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =
1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, pattern = PRBS 27 1, data rate = 2.25 Gbps, unless otherwise noted.
0.6
0.6
2m CABLE = 30AWG
5m TO 20m CABLES = 24AWG
2m CABLE = 30AWG
5m TO 20m CABLES = 24AWG
0.5
0.4
2.25Gbps
EQ = 12dB
0.3
1.65Gbps
EQ = 6dB
2.25Gbps
EQ = 6dB
0.2
1.65Gbps
EQ = 12dB
0.1
1.65Gbps, PE OFF
0.3
2.25Gbps, PE OFF
2.25Gbps, PE MAX
0.2
0.1
1.65Gbps, PE MAX
06470-014
0.4
10
15
25
20
10
06470-017
0.5
20
15
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
50
1200
45
1000
1080p
8-BIT
30
1080p
12-BIT
1.65Gbps
25
480p
20
1080i/720p
DJ (p-p)
480i
15
10
600
400
RJ (rms)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
06470-015
200
5
0
800
2.4
06470-018
JITTER (ps)
35
40
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
3.5
3.6
50
800
45
700
40
600
30
25
DJ (p-p)
20
15
500
400
300
200
10
0
3.0
RJ (rms)
3.1
3.2
3.3
3.4
3.5
3.6
100
0
2.5
06470-019
06470-016
JITTER (ps)
35
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
Rev. 0 | Page 10 of 24
3.4
AD8196
50
50
40
40
30
30
JITTER (ps)
DJ (p-p)
20
10
06470-020
10
RJ (rms)
0
DJ (p-p)
20
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
RJ (rms)
0
2.5
2.0
2.7
3.5
3.7
115
DIFFERENTIAL INPUT
TERMINATION RESISTANCE ()
40
35
30
25
DJ (p-p)
20
15
10
RJ (rms)
20
20
40
60
80
140
FALL TIME
120
RISE TIME
100
80
60
40
06470-022
20
40
90
20
20
40
60
80
100
160
20
95
TEMPERATURE (C)
100
80
40
100
TEMPERATURE (C)
20
105
85
06470-021
110
06470-024
JITTER (ps)
3.3
120
45
3.1
50
0
40
2.9
0
40
06470-023
JITTER (ps)
TA = 27C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =
1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, pattern = PRBS 27 1, data rate = 2.25 Gbps, unless otherwise noted.
60
80
100
TEMPERATURE (C)
Rev. 0 | Page 11 of 24
AD8196
THEORY OF OPERATION
VTTI
INTRODUCTION
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is provided
for the high speed channels where the user can (manually) select
among a number of fixed settings.
50
IP_xx
IN_xx
06470-025
CABLE
EQ
AVEE
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two single-ended 50
on-chip resistors (see Figure 26). This output termination is
user-selectable; all the output terminations can be turned on
or off by programming the TX_PTO bit of the transmitter
settings register.
VTTO
The AD8196 has I2C serial programming with two user programmable I2C slave addresses. The I2C slave address of the
AD8196 is 0b100100X. The least significant bit, represented by
X in the address, is set by tying the I2C_ADDR pin to either
3.3 V (for the value, X = 1) or to 0 V (for X = 0).
50
50
OPx
ONx
DISABLE
INPUT CHANNELS
IOUT
AVEE
50
06470-026
Rev. 0 | Page 12 of 24
AD8196
upon reset). If only external terminations are provided (if the
internal terminations are disabled), set the output current level
to 10 mA by programming the TX_OCL bit of the transmitter
settings register. The high speed outputs must be disabled if
there are no output termination resistors present in the system.
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register. No specific cable length is suggested
for a particular pre-emphasis setting because cable performance
varies widely between manufacturers.
SWITCHING MODE
The AD8196 behaves like a 2:1 HDMI/DVI link multiplexer by
routing groups of four TMDS input channels to the four channel
output. In this mode, the user selects the group of high speed
source signals (A or B) that is routed to the output by programming the HS_CH bit of the high speeds modes register as
shown in Table 7. The group of low speed auxiliary source
signals (AUX_A or AUX_B) that is routed to the common
output is separately set by programming the AUX_CH bit of
the auxiliary device register as shown in Table 9.
10k
I < 50mA
10M
+5V INTERNAL
(IF ANY)
AD8196
PERIPHERAL
CIRCUITRY
PERIPHERAL
CIRCUITRY
AUX_COM0
CAUX
I < 50mA
SOURCE B +5V
10k
Rev. 0 | Page 13 of 24
06470-028
CAUX
RAUX
SOURCE A +5V
AMUXVCC
06470-027
AUX_A0
AD8196
SERIAL CONTROL INTERFACE
RESET
6.
7.
8.
9.
b.
c.
d.
WRITE PROCEDURE
To write data to the AD8196 register set, an I2C master (such as
a microcontroller) needs to send the appropriate control signals
to the AD8196 slave device. The signals are controlled by the
I2C master, unless otherwise specified. For a diagram of the
procedure, see Figure 29. The steps for a write procedure are as
follows:
1.
2.
Send the AD8196 part address (seven bits). The upper six
bits of the AD8196 part address are the static value [100100]
and the LSB is set by Input Pin I2C_ADDR. This transfer
should be MSB first.
3.
4.
5.
*
I2C_SCL
R/W
GENERAL CASE
I2C_SDA
START
REGISTER ADDR
ADDR
ACK
DATA
STOP
ACK
ACK
EXAMPLE
I2C_SDA
2
Rev. 0 | Page 14 of 24
9
06470-029
AD8196
I2C_SCL
R/W
GENERAL CASE
I2C_SDA
START
R/W
SR
REGISTER ADDR
ADDR ACK
ACK
DATA
ADDR ACK
STOP
ACK
9 10 11
12
13
06470-030
EXAMPLE
I2C_SDA
READ PROCEDURE
a.
b.
c.
Send the AD8196 part address (seven bits). The upper six
bits of the AD8196 part address are the static value [100100]
and the LSB is set by Input Pin I2C_ADDR. This transfer
should be MSB first.
d.
3.
4.
5.
6.
7.
8.
9.
SWITCHING/UPDATE DELAY
There is a delay between when a user writes to the configuration registers of the AD8196 and when that state change takes
physical effect. This update delay begins at the falling edge of
I2C_SCL for the last data bit transferred, as shown in Figure 29.
This update delay is register specific and the times are specified
in Table 1.
During a delay window, new values can be written to the
configuration registers but the AD8196 does not physically
update until the end of that registers delay window. Writing
new values during the delay window does not reset the window;
new values supersede the previously written values. At the end
of the delay window, the AD8196 physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the delay
window ends, the AD8196 immediately updates and a new
delay window begins.
Rev. 0 | Page 15 of 24
AD8196
CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I2C serial interface, Pin I2C_SDA, and Pin I2C_SCL.
The LSB of the AD8196 I2C part address is set by tying Pin I2C_ADDR to 3.3 V (I2C_ADDR = 1) or 0 V (I2C_ADDR = 0).
Table 5. Register Map
Name
High Speed
Device
Modes
Bit 7
Bit 0
High speed
source select
HS_CH
Auxiliary
switch
source select
AUX_EN
AUX_CH
High speed
input
termination
select
RX_TO
Input termination pulse-on-source-switch select (disconnect termination for a short period of time)
Auxiliary
Device
Modes
Receiver
Settings
Input
Termination
Pulse
Receive
Equalizer
Bit 6
High speed
switch enable
HS_EN
Auxiliary
switch enable
Bit 5
Bit 4
RX_PT[7]
RX_PT[6]
RX_PT[5]
RX_EQ[7]
RX_EQ[6]
RX_EQ[5]
Bit 3
RX_PT[4]
Bit 2
RX_PT[3]
Bit 1
RX_PT[2]
RX_PT[1]
RX_PT[0]
RX_EQ[1]
High speed
output
termination
select
TX_PTO
RX_EQ[0]
High speed
output
current level
select
TX_OCL
Transmitter
Settings
RX_EQ[3] RX_EQ[2]
High speed output
pre-emphasis level
select
TX_PE[1]
TX_PE[0]
Addr.
0x00
Default
0x40
0x01
0x40
0x10
0x01
0x11
0x00
0x13
0x00
0x20
0x03
HS_EN
0
1
AUX_EN
0
Description
High speed channels off, low power/standby mode
High speed channels on
Description
Auxiliary switch off, no low speed input/output to
low speed common input/output connection
Auxiliary switch on
O[3:0]
A[3:0]
B[3:0]
Description
High speed Source A switched to output
High speed Source B switched to output
AUX_COM[3:0]
AUX_A[3:0]
AUX_B[3:0]
Rev. 0 | Page 16 of 24
Description
Auxiliary Source A switched to
output
Auxiliary Source B switched to
output
AD8196
RECEIVER SETTINGS REGISTER
RX_TO
0
1
RX_EQ[X]
0
1
Description
Input termination off
Input termination on (can be pulsed on and off
when source is switched, according to settings in
the input termination pulse register)
Description
Input termination for TMDS Channel X always
connected when source is switched
Input termination for TMDS Channel X
disconnected for approximately 100 ms when
source is switched
Description
Low equalization (6 dB)
High equalization (12 dB)
Description
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
Description
Output termination off
Output termination on
Rev. 0 | Page 17 of 24
Description
Output current set to 10 mA
Output current set to 20 mA
AD8196
06470-031
APPLICATION NOTES
PINOUT
The AD8196 is designed to have an HDMI/DVI receiver pinout
at its input and a transmitter pinout at its output. This makes the
AD8196 ideal for use in AVR-type applications where a designer
routes both the inputs and the outputs directly to HDMI/DVI
connectors as shown in Figure 31. When the AD8196 is used in
receiver-type applications, it is necessary to change the order of
the output pins on the PCB to align with the on-board receiver.
One advantage of the AD8196 in an AVR-type application is
that all of the high speed signals can be routed on one side (the
topside) of the board, as shown in Figure 31. In addition to
12 dB of input equalization, the AD8196 provides up to 6 dB of
output pre-emphasis that boosts the output TMDS signals and
Rev. 0 | Page 18 of 24
AD8196
CABLE LENGTHS AND EQUALIZATION
The AD8196 offers two levels of programmable equalization
for the high speed inputs: 6 dB and 12 dB. The equalizer of
the AD8196 supports video data rates of up to 2.25 Gbps, and
as shown in Figure 14, it can equalize more than 20 meters of
24 AWG HDMI cable at 2.25 Gbps, which corresponds to the video
format, 1080p with deep color.
The length of cable that can be used in a typical HDMI/DVI
application depends on a large number of factors including
Data rate: the data rate being sent over the cable. The signal
degradation of HDMI cables increases with data rate.
Edge rates: the edge rates of the source input. Slower input
edges result in more significant data eye closure at the end
of a cable.
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data
interleaves with the video data; the DVI standard does not incorporate audio information. The fourth high speed differential pair
is used for the AV data-word clock, and runs at one-tenth the
speed of the TMDS data channels.
The four high speed channels of the AD8196 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over
which channel. Additionally, the TMDS channels are symmetrical;
therefore, the p and n of a given differential pair are interchangeable, provided the inversion is consistent across all inputs
and outputs of the AD8196. However, the routing between inputs
and outputs through the AD8196 is fixed. For example, Output
Channel 0 always switches between Input A0 and Input B0, and
so forth.
The AD8196 buffers the TMDS signals and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces are more sensitive to the PCB layout. Regardless of the
data being carried on a specific TMDS channel, or whether the
TMDS line is at the input or the output of the AD8196, all four
high speed signals should be routed on a PCB in accordance
with the same RF layout guidelines.
Rev. 0 | Page 19 of 24
AD8196
Layout for the TMDS Signals
The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 . The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together to establish the required 100 differential impedance. Enough space should be left between the
differential pairs of a given group so that the n of one pair does
not couple to the p of another pair. For example, one technique is
to make the interpair distance 4 to 10 times wider than the
intrapair spacing.
Any one group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths to minimize
interpair skew. Severe interpair skew can cause the data on the
four different channels of a group to arrive out of alignment
with one another. A good practice is to match the trace lengths
for a given group of four channels to within 0.05 inches on FR4
material.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
Though the AD8196 features input equalization and output preemphasis, the length of the TMDS traces should be minimized
to reduce overall system signal degradation. Commonly used
PC board material such as FR4 is lossy at high frequencies, so
long traces on the circuit board increase signal attenuation,
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR
(REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
Rev. 0 | Page 20 of 24
06470-032
AD8196
3W
TMDS Terminations
The AD8196 provides internal 50 single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
3W
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
06470-033
SILKSCREEN
Power Supplies
The AD8196 has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are
AVCC/AVEE
VTTI/AVEE
VTTO/AVEE
DVCC/DVEE
AMUXVCC/DVEE
Rev. 0 | Page 21 of 24
AD8196
maximum allowed voltage on the auxiliary lines. For example,
if the DDC bus is using 5 V I2C, then AMUXVCC should be
connected to +5 V relative to DVEE.
DECOUPLING
CAPACITORS
AD8196
RECOMMENDED
AUXILIARY LINES
TMDS TRACES
06470-035
NOT RECOMMENDED
06470-034
Rev. 0 | Page 22 of 24
AD8196
OUTLINE DIMENSIONS
8.00
BSC SQ
0.30
0.23
0.18
0.60 MAX
0.60 MAX
56
43
42
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
0.40
0.30
1.00
0.85
0.80
12 MAX
SEATING
PLANE
14
29
28
15
0.30 MIN
6.50
REF
0.80 MAX
0.65 TYP
0.50 BSC
4.95
4.80 SQ
4.65
*EXPOSED
PAD
(BOTTOM VIEW)
7.75
BSC SQ
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
011907-A
TOP
VIEW
ORDERING GUIDE
Model
AD8196ACPZ 1
AD8196ACPZ-R71
AD8196ACPZ-RL1
AD8196-EVAL
1
Temperature
Range
40C to +85C
40C to +85C
40C to +85C
Package Description
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 23 of 24
Package
Option
CP-56-3
CP-56-3
CP-56-3
Ordering
Quantity
750
2500
AD8196
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev. 0 | Page 24 of 24