A Verification Methodology for Reusable Test Cases

and Coverage Based on System Verilog

Lingling Chai

Zheng Xie, Xinan Wang*

Key Lab of Integrated Microsystems

Peking University Shenzhen Graduate School
Shenzhen, 518055, China
levana_choi@sz.pku.edu.cn

Key Lab of Integrated Microsystems

Peking University Shenzhen Graduate School
Shenzhen, 518055, China
anxinwang@pku.edu.cn

AbstractAs the size and complexity of SoC design grow, it is

common to establish a scalable and reusable verification test
bench for verification engineers. To improve the efficiency of
verification and reduce the development time and effort in chip
design projects, the extensive and reusable test case model and
function coverage model for the special circuit and the standard
protocols should be focused on by verification engineers. In this
paper, a verification methodology for reusable test cases and
coverage is described. As an example, a reusable test bench of
chain table DUT is utilized to verify the feasibility of the
verification methodology.
KeywordsVerification
Case;Functional Coverage

Methodology;

Reusability;

Test

RM(reference model) and scoreboard may reuse in different

projects or different test phases in the same project. If the
interface signals of DUT are the standard protocols, the
monitor and master can be reused, for instance the VIP got
from EDA vendors. This paper mainly discusses test cases and
coverage model reused in the standard protocols and typical
functional circuits.
generate

Generator
model
generate

Testbench
architecture

Test case
sample

channel

generator

I.

INTRODUCTION

With the development of chip-manufacturing process

which has reached 16nm, in the integration of more than
million transistors on a single chip has been achieved. This has
made verification the most critical bottleneck in the chip
design flow. Roughly 70 to 80 percent of the design cycle is
spent on functional verification. The SoC design faces a gap
between the production capabilities and time to market
pressures. The longer a bug of a design does undetected the
more expensive it is. So both innovative verification
methodologies and an effective verification environment are
urgently needed. Reuse is the valuable technology for
constructing an effective verification environment. Currently,
there are many verification methodologies as VMM/UMV and
lots of VIPs for reuse to quickly set up a verification
environment. For some typical functional circuits and standard
protocols whose functionality or interface is stable, the paper
abstracts this functionality to build a set of reusable utilities
including test point, test case and function coverage model.
This can immensely improve the verification efficiency and
reduce the chip design time.
II.

TEST CASE REUSABLE TEST TENCH

ARCHITECTURE

At present, the generic test bench is designed to a

hierarchical architecture, it contains three main levels, namely
Driver BFM, generator and the test case component. As is
shown in the green frame of Fig.1. The Fig.1 shows that

channel

RM

Function
coverage

scoreboard

channel

channel

Driver BFM

channel

monitor

interface

monitor

DUT

Driver Bfm

interface

Fig.1. The complete and reusable test bench architecture

In the Fig.1 the generator model that is the core of the

reusable test bench was presented in the blue dotted frame. In
the paper, the test cases generator model is abstracted from the
DUT functionality. This model written by script language can
automatically generate the test case and function coverage
model. Owning to the DUT functionality is the standards or
the typical circuits, the model may be reuse in different
designs.
III.

THE INTRODUCTION OF CHAIN TABLE DUT

This section explains how to set up a complete and

reusable VIP architecture. Firstly, the chain table DUT
functionality and structure are described in Figure 2.

M1
M2

Chain Table
DUT

M3
M4

Fig.2. The architecture of the chain table DUT

The architecture of chain table DUT used here consists of

five main functions:

Four modules all can launch the fetch and add chain
operation.

The use of parameterized classes will make the classes more

convenient and flexible

At any one time, there can be more one chain table

request operation launched by multiple modules, but
the DUT only responses one requirement at the same
time, because there is only one arbiter.

Fig.4 shows how to use the parameterization design to

establish the transaction class.

The operation of the interface may be diverse, so the

monitor and the driver cant be fully reused.
Add the node at header of chain or at tail of chain.
Fetch the node which is the header of chain.
According to the chain table functionality is generic and
typical. We can abstract a function and construct a chain table
test case generator model. This model can be reusable and
automatically generate the test case and function coverage
model of chain table.
IV.

Fig.4. The establishment of the transaction class

D. Function coverage model

According to the generator model script, a function
coverage model has been automatically generated. It is
showed in Fig.5.

THE CHAIN TABLE TEST BENCH

The contracture of the chain table test bench used here

which contains master model, monitor model, reference
model(RM) , test case generator model and node content
transaction is shown in Fig.1. Due to the DUT interface may
be non-uniform standard in different projects, the driver and
monitor may not be reusable. But the generator model and RM
can be reusable.
A. Reference model(RM)
The RM model contains two associative array in which
stores the nodes content of chain table. It includes two tasks
that achieve the add chain function and fetch chain function.
The RM operate two associative arrays to form a chain table
whose structure and content are the same with the structure
and content of the DUT.

Fig.5. Auto-generation of the function coverage model

There are two covergroups, one stats the chain requirement

content, the other stats the requirement num at some point.
The generator model is used to abstract the chain table
functionality. In this way, we can reuse the test case in
different scenes in which we can only replace the monitor to
quickly set up a chain table verification environment during to
the different interfaces, the RM, test case and function
coverage can be reused.
V.

B. Test case generator model

The functionality of the DUT is affected by the number of
requirement source, the number of operation type and the
number of requirement. The generator model consists of two
functions, one function automatically generate many test cases
which contains requirement sequences; the other function
generate the function coverage model.
In this paper Perl script language is used to described the
generator model. It is showed in Fig.3.

CONCLUSIONS

The verification methodology described in this paper can be

reused easily for different designs. Such as AMBA BUS
protocols, I2C/UART/SPI interface, FIFO typical circuits. To
fully verify the feasibility of the methodology, the paper
discussed a chain table test bench using reusable generator
model to automatically generate test cases and coverage
model. Use of the verification methodology presented in this
paper will reduce development time and expense, and result in
more robust hardware devices.
REFERENCES
[1]
[2]

[3]
Fig.3. The generator model in the proposed test bench
[4]

C. Node content transaction

It is often useful to define a generic class whose objects
can be instantiated to have different array sizes or data types.

[5]

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Janick Bergeron, Eduard Cerny, et al. Verification Methodologr Manual
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