Академический Документы
Профессиональный Документы
Культура Документы
HC11M68HC
1M68HC11M
M68HC11E/D
REV 3
M68HC11E Family
Technical Data
HCMOS
Microcontroller Unit
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customers technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
List of Sections
Technical Data
List of Sections
List of Sections
EB188 Enabling the Security Feature
on M68HC811E2 Devices with PCbug11
on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . 323
EB296 Programming MC68HC711E9 Devices
with PCbug11 and the M68HC11EVBU . . . . . . . . 327
Technical Data
4
MOTOROLA
Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3
2.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5
2.6
2.7
2.8
2.9
2.10
2.11
STRA/AS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.12
STRB/R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Technical Data
Table of Contents
Table of Contents
Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1
Accumulators A, B, and D . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2
Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3
Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.3.6
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 49
3.3.6.1
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.6.2
Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.6.3
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3.6.4
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.5
Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.6
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6.7
X Interrupt Mask (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6.8
STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5
3.6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6.1
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6.2
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.3
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.4
Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.5
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.6
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.1
Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.2
Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Technical Data
6
MOTOROLA
Table of Contents
4.3.3
4.3.4
4.4
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.1
RAM and Input/Output Mapping. . . . . . . . . . . . . . . . . . . . . . 78
4.4.2
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4.3
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.4.3.1
System Configuration Register . . . . . . . . . . . . . . . . . . . . 84
4.4.3.2
RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . .87
4.4.3.3
System Configuration Options Register . . . . . . . . . . . . . . 89
4.5
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.5.1
Programming an Individual EPROM Address . . . . . . . . . . . 91
4.5.2
Programming the EPROM with Downloaded Data. . . . . . . . 92
4.5.3
EPROM and EEPROM Programming Control Register . . . . 92
4.6
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6.1
EEPROM and CONFIG Programming and Erasure. . . . . . . 96
4.6.1.1
Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6.1.2
EPROM and EEPROM Programming
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.6.1.3
EEPROM Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.1.4
EEPROM Row Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.1.5
EEPROM Byte Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.6.1.6
CONFIG Register Programming . . . . . . . . . . . . . . . . . .102
4.6.2
EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.2
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . 108
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.5
System Configuration Options Register . . . . . . . . . . . . . . . 110
5.3.6
Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . 111
5.4
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.1
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . 113
M68HC11E Family Rev. 3.0
MOTOROLA
Technical Data
Table of Contents
Table of Contents
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
5.4.10
5.5
Reset and Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5.1
Highest Priority Interrupt and Miscellaneous Register . . . . 117
5.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.6.1
Interrupt Recognition and Register Stacking . . . . . . . . . . . 120
5.6.2
Non-Maskable Interrupt Request (XIRQ) . . . . . . . . . . . . . .121
5.6.3
Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.6.4
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.6.5
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.6.6
Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . 122
5.7
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.8
6.9
Technical Data
8
MOTOROLA
Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.3
7.4
7.5
7.6
Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.6.1
Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.6.2
Address-Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.7
7.8
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
7.8.1
Serial Communications Data Register . . . . . . . . . . . . . . . . 150
7.8.2
Serial Communications Control Register 1 . . . . . . . . . . . . 151
7.8.3
Serial Communications Control Register 2 . . . . . . . . . . . . 152
7.8.4
Serial Communication Status Register. . . . . . . . . . . . . . . . 153
7.8.5
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.9
7.10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
8.3
8.4
8.5
8.6
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.6.1
Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.6.2
Master Out/Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.6.3
Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.6.4
Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.7
8.8
Technical Data
Table of Contents
Table of Contents
8.8.1
8.8.2
8.8.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.3
9.4
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
9.4.1
Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.4.2
Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . 182
9.4.3
Timer Input Capture 4/Output Compare 5 Register . . . . . . 184
9.5
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
9.5.1
Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . 185
9.5.2
Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 188
9.5.3
Output Compare Mask Register. . . . . . . . . . . . . . . . . . . . . 189
9.5.4
Output Compare Data Register . . . . . . . . . . . . . . . . . . . . . 190
9.5.5
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
9.5.6
Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 192
9.5.7
Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . 193
9.5.8
Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 194
9.5.9
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 194
9.5.10 Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . . 196
9.6
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.6.1
Timer Interrupt Mask Register 2. . . . . . . . . . . . . . . . . . . . . 198
9.6.2
Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . . 199
9.6.3
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 200
9.7
9.8
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.8.1
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 203
9.8.2
Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . .204
9.8.3
Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . 205
Technical Data
10
MOTOROLA
Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
10.5
10.6
10.7
10.8
10.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.3
11.4
11.5
11.6
11.7
11.8
11.9
Technical Data
Table of Contents
11
Table of Contents
11.11 MC68L11E9 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 228
11.12 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
11.13 MC68L11E9 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . 234
11.14 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . 238
11.15 MC68L11E9 Analog-to-Digital Converter Characteristics. . . . 239
11.16 Expansion Bus Timing Characteristics . . . . . . . . . . . . . . . . . . 240
11.17 MC68L11E9 Expansion Bus Timing Characteristics . . . . . . . 242
11.18 Serial Peripheral Interface Timing Characteristics . . . . . . . . .244
11.19 MC68L11E9 Serial Peirpheral Interface Characteristics . . . .245
11.20 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
11.21 MC68L11E9 EEPROM Characteristics . . . . . . . . . . . . . . . . . 248
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.3
12.4
12.5
12.6
12.7
12.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.3
13.4
13.5
Technical Data
12
MOTOROLA
Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
A.3
A.4
A.5
A.6
AN1060
AN1060 M68HC11 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . 273
EB184
EB184 Enabling the Security Feature on the MC68HC711E9
Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . 319
EB188
EB188 Enabling the Security Feature on M68HC811E2
Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . 323
EB296
EB296 Programming MC68HC711E9 Devices with PCbug11
and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Technical Data
Table of Contents
13
Table of Contents
Technical Data
14
MOTOROLA
List of Figures
Figure
Title
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Stacking Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
Address/Data Demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . 66
Memory Map for MC68HC11E0 . . . . . . . . . . . . . . . . . . . . . . . 68
Memory Map for MC68HC11E1 . . . . . . . . . . . . . . . . . . . . . . . 68
Memory Map for MC68HC(7)11E9. . . . . . . . . . . . . . . . . . . . . 69
Memory Map for MC68HC(7)11E20. . . . . . . . . . . . . . . . . . . .69
Memory Map for MC68HC811E2 . . . . . . . . . . . . . . . . . . . . . . 70
Register and Control Bit Assignments . . . . . . . . . . . . . . . . . . 70
RAM Standby MODB/VSTBY Connections . . . . . . . . . . . . . . . 79
Highest Priority I-Bit Interrupt and Miscellaneous
Register (HPRIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
System Configuration Register (CONFIG) . . . . . . . . . . . . . . .85
MC68HC811E2 System Configuration Register (CONFIG) . . 85
RAM and I/O Mapping Register (INIT) . . . . . . . . . . . . . . . . . . 87
System Configuration Options Register (OPTION) . . . . . . . . 89
4-10
4-11
4-12
4-13
Page
Technical Data
List of Figures
15
List of Figures
Figure
4-14
4-15
4-16
4-17
5-1
5-2
5-3
5-4
Title
5-5
5-6
5-7
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Technical Data
16
Page
MOTOROLA
List of Figures
Figure
7-9
Title
7-10
8-1
8-2
8-3
8-4
8-5
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
M68HC11E Family Rev. 3.0
MOTOROLA
Page
Technical Data
List of Figures
17
List of Figures
Figure
Title
9-26
9-27
9-28
10-1
10-2
10-3
10-4
10-5
10-6
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
Technical Data
18
Page
MOTOROLA
List of Tables
Table
Title
2-1
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
5-3
5-4
5-5
6-1
6-2
7-1
8-1
9-1
9-2
Page
Technical Data
List of Tables
19
List of Tables
Table
Title
9-3
9-4
9-5
9-6
9-7
10-1
10-2
Technical Data
20
Page
MOTOROLA
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Introduction
This document contains a detailed description of the M68HC11 E series
of 8-bit microcontroller units (MCUs). These MCUs all combine the
M68HC11 central processor unit (CPU) with high-performance, on-chip
peripherals.
The E series is comprised of many devices with various
configurations of:
Technical Data
General Description
21
General Description
1.3 Features
Features of the E-series devices include:
M68HC11 CPU
Technical Data
22
MOTOROLA
General Description
Structure
1.4 Structure
See Figure 1-1 for a functional diagram of the E-series MCUs.
Differences among devices are noted in the table accompanying
Figure 1-1.
Technical Data
General Description
23
General Description
XTAL EXTAL
IRQ
OSC
INTERRUPT
LOGIC
MODE CONTROL
ROM OR EPROM
(SEE TABLE)
EEPROM
(SEE TABLE)
M68HC11 CPU
RAM
(SEE TABLE)
SERIAL
COMMUNICATION
INTERFACE
SCI
SERIAL
PERIPHERAL
INTERFACE
SPI
VDD
VSS
VRH
VRL
TxD
RxD
ADDRESS/DATA
SS
SCK
MOSI
MISO
BUS EXPANSION
ADDRESS
R/W
AS
PULSE ACCUMULATOR
COP
PAI
OC2
OC3
OC4
OC5/IC4/OC1
IC1
IC2
PERIODIC INTERRUPT
IC3
CLOCK LOGIC
TIMER
SYSTEM
XIRQ/VPPE* RESET
STRB
STRA
MODA/ MODB/
LIR
VSTBY
A/D CONVERTER
DEVICE
MC68HC11E0
MC68HC11E1
MC68HC11E9
MC68HC711E9
MC68HC11E20
MC68HC711E20
MC68HC811E2
RAM
512
512
512
512
768
768
256
ROM
12 K
20 K
PE7/AN7
PE6/AN6
PE5/AN5
PE4/AN4
PE3/AN3
PE2/AN2
PE1/AN1
PE0/AN0
PORT E
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TxD
PD0/RxD
STRA/AS
PORT C
STRB/R/W
PORT B
PC7/ADDR7/DATA7
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
PC0/ADDR0/DATA0
PORT D
PORT A
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
CONTROL
PA7/PAI
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
PA2/IC1
PA1/IC2
PA0/IC3
CONTROL
EPROM
12 K
20 K
EEPROM
512
512
512
512
512
2048
Technical Data
24
MOTOROLA
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3
2.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5
2.6
2.7
2.8
2.9
2.10
2.11
STRA/AS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.12
STRB/R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Technical Data
Pin Descriptions
25
Pin Descriptions
2.2 Introduction
M68HC11 E-series MCUs are available packaged in:
47 PE2/AN2
48 PE6/AN6
49 PE3/AN3
50 PE7/AN7
51 VRL
VSS
52 VRH
2 MODB/VSTBY
3 MODA/LIR
4 STRA/AS
5 E
6 STRB/R/W
7 EXTAL
PE5/AN5
45
PE1/AN1
10
44
PE4/AN4
PC2/ADDR2/DATA2
11
43
PE0/AN0
PC3/ADDR3/DATA3
12
42
PB0/ADDR8
PC4/ADDR4/DATA4
13
41
PB1/ADDR9
PC5/ADDR5/DATA5
14
40
PB2/ADDR10
PC6/ADDR6/DATA6
15
39
PB3/ADDR11
PC7/ADDR7/DATA7
16
38
PB4/ADDR12
PC0/ADDR0/DATA0
PC1/ADDR1/DATA1
46
XTAL
M68HC11 E SERIES
31
32
33
PA3/OC5/IC4/OC1
PA2/IC1
PA1/IC2
29
30
28
PA5/OC3/OC1
PA4/OC4/OC1
27
PA7/PAI/OC1
PA6/OC2/OC1
PA0/IC3
26
34
25
20
PD5/SS
VDD
PD0/RxD
24
PB7/ADDR15
23
35
PD4/SCK
IRQ
PD3/MOSI
PB6/ADDR14
19
22
PB5/ADDR13
36
21
37
18
PD1/TxD
17
PD2/MISO
RESET
* XIRQ/VPPE
MOTOROLA
PA0/IC3
NC
NC
NC
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PE0/AN0
PE4/AN4
PE1/AN1
PE5/AN5
9
10
11
12
13
14
15
16
56
55
54
53
52
51
50
49
64
63
62
61
60
59
58
57
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
NC
NC
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
VDD
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TxD
VSS
Pin Descriptions
Introduction
2
3
M68HC11 E SERIES
NC
PD0/RxD
IRQ
XIRQ/VPPE*
NC
RESET
PC7/ADDR7/DATA7
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
NC
PC0/ADDR0/DATA0
XTAL
PE2/AN2
PE6/AN6
PE3/AN3
PE7/AN7
VRL
VRH
VSS
VSS
MODB/VSTBY
NC
MODA/LIR
STRA/AS
E
STRB/R/W
EXTAL
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Technical Data
Pin Descriptions
27
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
PD0/RxD
IRQ
XIRQ/VPPE*
RESET
PC7/ADDR7/DATA7
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
PC0/ADDR0/DATA0
XTAL
PE2/AN2
PE6/AN6
PE3/AN3
PE7/AN7
VRL
VRH
VSS
MODB/VSTBY
MODA/LIR
STRA/AS
E
STRB/R/W
EXTAL
19
20
21
22
23
24
25
26
M68HC11 E SERIES
14
15
16
17
18
PA0/IC3
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PE0/AN0
PE4/AN4
PE1/AN1
PE5/AN5
45
44
43
42
41
40
52
51
50
49
48
47
46
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
VDD
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TxD
Pin Descriptions
Technical Data
28
MOTOROLA
Pin Descriptions
Introduction
VSS
56
EVSS
MODB/VSTBY
55
VRH
MODA/LIR
54
VRL
STRA/AS
53
PE7/AN7
52
PE3/AN3
STRB/R/W
51
PE6/AN6
EXTAL
50
PE2/AN2
XTAL
49
PE5/AN5
PC0/ADDR0/DATA0
48
PE1/AN1
PC1/ADDR1/DATA1
10
47
PE4/AN4
PC2/ADDR2/DATA2
11
46
PE0/AN0
PC3/ADDR3/DATA3
12
45
PB0/ADDR8
PC4/ADDR4/DATA4
13
44
PB1/ADDR9
PC5/ADDR5/DATA5
14
43
PB2/ADDR10
PC6/ADDR6/DATA6
15
M68HC11 E SERIES 42
PB3/ADDR11
PC7/ADDR7/DATA7
16
41
PB4/ADDR12
RESET
17
40
PB5/ADDR13
* XIRQ/VPPE
18
39
PB6/ADDR14
IRQ
19
38
PB7/ADDR15
PD0/RxD
20
37
PA0/IC3
EVSS
21
36
PA1/IC2
PD1/TxD
22
35
PA2/IC1
PD2/MISO
23
34
PA3/OC5/IC4/OC1
PD3/MOSI
24
33
PA4/OC4/OC1
PD4/SCK
25
32
PA5/OC3/OC1
PD5/SS
26
31
PA6/OC2/OC1
VDD
27
30
PA7/PAI/OC1
VSS
28
29
EVDD
Technical Data
Pin Descriptions
29
Pin Descriptions
PA7/PAI/OC1
48
VDD
PA6/OC2/OC1
47
PD5/SS
PA5/OC3/OC1
46
PD4/SCK
PA4/OC4/OC1
45
PD3/MOSI
PA3/OC5/IC4/OC1
44
PD2/MISO
PA2/IC1
43
PD1/TxD
PA1/IC2
42
PD0/RxD
PA0/IC3
41
IRQ
PB7/ADDR15
40
XIRQ
PB6/ADDR14
10
39
RESET
PB5/ADDR13
11
PB4/ADDR12
12
PB3/ADDR11
38
PC7/ADDR7/DATA7
37
PC6/ADDR6/DATA6
13
36
PC5/ADDR5/DATA5
PB2/ADDR10
14
35
PC4/ADDR4/DATA4
PB1/ADDR9
15
34
PC3/ADDR3/DATA3
PB0/ADDR8
16
33
PC2/ADDR2/DATA2
PE0/AN0
MC68HC811E2
17
32
PC1/ADDR1/DATA1
PE1/AN1
18
31
PC0/ADDR0/DATA0
PE2/AN2
19
30
XTAL
PE3/AN3
20
29
EXTAL
VRL
21
28
STRB/R/W
VRH
22
27
VSS
23
26
STRA/AS
MODB/VSTBY
24
25
MODA/LIR
Technical Data
30
MOTOROLA
Pin Descriptions
VDD and VSS
VDD
4.7 k
IN
RESET
MC34(0/1)64
TO RESET
OF M68HC11
GND
3
VDD
VDD
IN
RESET
MC34064
GND
VDD
4.7 k
TO RESET
OF M68HC11
4.7 k
MANUAL
RESET SWITCH
4.7 k
1.0 F
IN
RESET
MC34164
GND
Technical Data
Pin Descriptions
31
Pin Descriptions
2.4 RESET
A bidirectional control signal, RESET, acts as an input to initialize the
MCU to a known startup state. It also acts as an open-drain output to
indicate that an internal failure has been detected in either the clock
monitor or computer operating properly (COP) watchdog circuit. The
CPU distinguishes between internal and external reset conditions by
sensing whether the reset pin rises to a logic 1 in less than two E-clock
cycles after a reset has occurred. See Figure 2-6 and Figure 2-7.
CAUTION:
Technical Data
32
MOTOROLA
Pin Descriptions
Crystal Driver and External Clock Input (XTAL and EXTAL)
2.5 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a CMOScompatible clock to control the internal clock generator circuitry. The
frequency applied to these pins is four times higher than the desired
E-clock rate.
The XTAL pin must be left unterminated when an external CMOScompatible clock input is connected to the EXTAL pin. The XTAL output
is normally intended to drive only a crystal.
CAUTION:
In all cases, use caution around the oscillator pins. Load capacitances
shown in the oscillator circuit are specified by the crystal manufacturer
and should include all stray layout capacitances.
Refer to Figure 2-8 and Figure 2-9.
CL
EXTAL
10 M
MCU
4xE
CRYSTAL
CL
XTAL
4xE
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
EXTAL
MCU
XTAL
NC
Technical Data
Pin Descriptions
33
Pin Descriptions
2.6 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal
from E is used as a timing reference. The frequency of the E-clock output
is one fourth that of the input frequency at the XTAL and EXTAL pins.
When E-clock output is low, an internal process is taking place. When it
is high, data is being accessed.
All clocks, including the E clock, are halted when the MCU is in stop
mode. To reduce RFI emissions, the E-clock output of most E-series
devices can be disabled while operating in single-chip modes.
The E-clock signal is always enabled on the MC68HC811E2.
NOTE:
Technical Data
34
MOTOROLA
Pin Descriptions
MODA and MODB (MODA/LIR and MODB/VSTBY)
There should be a single pullup resistor near the MCU interrupt input pin
(typically 4.7 k). There must also be an interlock mechanism at each
interrupt source so that the source holds the interrupt line low until the
MCU recognizes and acknowledges the interrupt request. If one or more
interrupt sources are still pending after the MCU services a request, the
interrupt line will still be held low and the MCU will be interrupted again
as soon as the interrupt mask bit in the MCU is cleared (normally upon
return from an interrupt). Refer to Section 5. Resets and Interrupts.
VPPE is the input for the 12-volt nominal programming voltage required
for EPROM/OTPROM programming. On devices without
EPROM/OTPROM, this pin is only an XIRQ input.
Single-chip mode
Expanded mode
Test mode
Bootstrap mode
Technical Data
Pin Descriptions
35
Pin Descriptions
2.10 VRL and VRH
These two inputs provide the reference voltages for the analog-to-digital
(A/D) converter circuitry:
2.11 STRA/AS
The strobe A (STRA) and address strobe (AS) pin performs either of two
separate functions, depending on the operating mode:
2.12 STRB/R/W
The strobe B (STRB) and read/write (R/W) pin act as either an output
strobe or as a data bus direction indicator, depending on the operating
mode.
In single-chip operating mode, STRB acts as a programmable strobe for
handshake with other parallel devices. Refer to Section 6. Parallel
Input/Output (I/O) Ports for further information.
In expanded multiplexed operating mode, R/W is used to indicate the
direction of transfers on the external data bus. A low on the R/W pin
indicates data is being written to the external data bus. A high on this pin
Technical Data
36
MOTOROLA
Pin Descriptions
Port Signals
2.13.1 Port A
In all operating modes, port A can be configured for three timer input
capture (IC) functions and four timer output compare (OC) functions. An
additional pin can be configured as either the fourth IC or the fifth OC.
Any port A pin that is not currently being used for a timer function can be
used as either a general-purpose input or output line. Only port A pins
PA7 and PA3 have an associated data direction control bit that allows
the pin to be selectively configured as input or output. Bits DDRA7 and
DDRA3 located in PACTL register control data direction for PA7 and
PA3, respectively. All other port A pins are fixed as either input or output.
Technical Data
Pin Descriptions
37
Pin Descriptions
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Single-Chip and
Bootstrap Modes
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR0/DATA0
ADDR1/DATA1
ADDR2/DATA2
ADDR3/DATA3
ADDR4/DATA4
ADDR5/DATA5
ADDR6/DATA6
ADDR7/DATA7
PD0/RxD
PD1/TxD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
STRA
STRB
AS
R/W
PE0/AN0
PE1/AN1
PE3/AN2
PE3/AN3
PE4/AN4
PE5/AN5
PE6/AN6
PE7/AN7
Technical Data
38
Expanded and
Test Modes
MOTOROLA
Pin Descriptions
Port Signals
2.13.2 Port B
During single-chip operating modes, all port B pins are general-purpose
output pins. During MCU reads of this port, the level sensed at the input
side of the port B output drivers is read. Port B can also be used in simple
strobed output mode. In this mode, an output pulse appears at the STRB
signal each time data is written to port B.
In expanded multiplexed operating modes, all of the port B pins act as
high order address output signals. During each MCU cycle, bits 158 of
the address bus are output on the PB7PB0 pins. The PORTB register
is treated as an external address in expanded modes.
Technical Data
Pin Descriptions
39
Pin Descriptions
2.13.3 Port C
While in single-chip operating modes, all port C pins are
general-purpose I/O pins. Port C inputs can be latched into an alternate
PORTCL register by providing an input transition to the STRA signal.
Port C can also be used in full handshake modes of parallel I/O where
the STRA input and STRB output act as handshake control lines.
When in expanded multiplexed modes, all port C pins are configured as
multiplexed address/data signals. During the address portion of each
MCU cycle, bits 70 of the address are output on the PC7PC0 pins.
During the data portion of each MCU cycle (E high), PC7PC0 are
bidirectional data signals, DATA7DATA0. The direction of data at the
port C pins is indicated by the R/W signal.
The CWOM control bit in the PIOC register disables the port C P-channel
output driver. CWOM simultaneously affects all eight bits of port C.
Because the N-channel driver is not affected by CWOM, setting CWOM
causes port C to become an open-drain type output port suitable for
wired-OR operation.
In wired-OR mode:
Technical Data
40
MOTOROLA
Pin Descriptions
Port Signals
2.13.4 Port D
Pins PD5PD0 can be used for general-purpose I/O signals. These pins
alternately serve as the serial communication interface (SCI) and serial
peripheral interface (SPI) signals when those subsystems are enabled.
PD0 is the receive data input (RxD) signal for the SCI.
PD1 is the transmit data output (TxD) signal for the SCI.
2.13.5 Port E
Use port E for general-purpose or analog-to-digital (A/D) inputs.
CAUTION:
Technical Data
Pin Descriptions
41
Pin Descriptions
Technical Data
42
MOTOROLA
3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1
Accumulators A, B, and D . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2
Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3
Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.3.6
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 49
3.3.6.1
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.6.2
Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.6.3
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3.6.4
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.5
Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.6
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6.7
X Interrupt Mask (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6.8
STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5
3.6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6.1
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6.2
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.3
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.4
Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.5
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.6
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.7
Technical Data
Central Processor Unit (CPU)
43
Data types
Addressing modes
Instruction set
Technical Data
44
MOTOROLA
7
15
0
0
IX
INDEX REGISTER X
IY
INDEX REGISTER Y
SP
STACK POINTER
PROGRAM COUNTER
PC
7
S
0
X
CONDITION CODES
Technical Data
Central Processor Unit (CPU)
45
Technical Data
46
MOTOROLA
MAIN PROGRAM
INTERRUPT ROUTINE
PC
PC
DIRECT
$9D = JSR
dd
RTN NEXT MAIN INSTR.
$3B = RTI
SP+2
SP+3
SP+4
PC
$AD = JSR
ff
RTN NEXT MAIN INSTR.
SP+5
7
SP+6
SP2
SP+7
SP
PC
$18 = PRE
$AD = JSR
RTN
ff
NEXT MAIN INSTR.
SP+8
RTNH
RTNL
SP1
MAIN PROGRAM
INDEXED, Y
STACK
SP+9
MAIN PROGRAM
PC
$3F = SWI
SP6
$8D = BSR
STACK
SP3
$3E = WAI
SP2
SP
STACK
SP
SP+1
SP+2
CCR
ACCB
ACCA
IXH
IXL
IYH
IYL
RTNH
RTNL
LEGEND:
RTNH
RTNL
SP
SP2
$39 = RTS
SP4
SP1
SP1
PC
SP5
MAIN PROGRAM
BSR, BRANCH TO SUBROUTINE
STACK
SP9
SP7
$BD = PRE
hh
RTN
ll
NEXT MAIN INSTR.
PC
PC
7
SP8
MAIN PROGRAM
MAIN PROGRAM
PC
INDEXED, Y
STACK
CCR
ACCB
ACCA
IXH
IXL
IYH
IYL
RTNH
RTNL
SP+1
MAIN PROGRAM
INDEXED, X
7
SP
RTNH
RTNL
Technical Data
Central Processor Unit (CPU)
47
Clock Monitor
COP Watchdog
Normal
$FFFE, F
$FFFC, D
$FFFA, B
Test or Boot
$BFFE, F
$BFFC, D
$BFFA, B
Technical Data
48
MOTOROLA
Technical Data
Central Processor Unit (CPU)
49
MOTOROLA
Technical Data
Central Processor Unit (CPU)
51
Immediate
Direct
Extended
Indexed
Inherent
Relative
These modes are detailed in the following paragraphs. All modes except
inherent mode use an effective address. The effective address is the
memory address from which the argument is fetched or stored or the
address from which execution is to proceed. The effective address can
be specified within an instruction, or it can be calculated.
3.6.1 Immediate
In the immediate addressing mode, an argument is contained in the
byte(s) immediately following the opcode. The number of bytes following
the opcode matches the size of the register or memory location being
operated on. There are 2-, 3-, and 4- (if prebyte is required) byte
immediate instructions. The effective address is the address of the byte
following the instruction.
Technical Data
52
MOTOROLA
3.6.2 Direct
In the direct addressing mode, the low-order byte of the operand
address is contained in a single byte following the opcode, and the
high-order byte of the address is assumed to be $00. Addresses
$00$FF are thus accessed directly, using 2-byte instructions.
Execution time is reduced by eliminating the additional memory access
required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11
MCUs, the memory map can be configured for combinations of internal
registers, RAM, or external memory to occupy these addresses.
3.6.3 Extended
In the extended addressing mode, the effective address of the argument
is contained in two bytes following the opcode byte. These are 3-byte
instructions (or 4-byte instructions if a prebyte is required). One or two
bytes are needed for the opcode and two for the effective address.
3.6.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in
the instruction is added to the value contained in an index register (IX or
IY). The sum is the effective address. This addressing mode allows
referencing any memory location in the 64-Kbyte address space. These
are 2- to 5-byte instructions, depending on whether or not a prebyte is
required.
3.6.5 Inherent
In the inherent addressing mode, all the information necessary to
execute the instruction is contained in the opcode. Operations that use
only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are
1- or 2-byte instructions.
Technical Data
Central Processor Unit (CPU)
53
Technical Data
54
MOTOROLA
Operation
Description
ABA
Add
Accumulators
Add B to X
Add B to Y
Add with Carry
to A
A+BA
ABX
ABY
ADCA (opr)
Addressing
Mode
INH
IX + (00 : B) IX
IY + (00 : B) IY
A+M+CA
ADCB (opr)
B+M+CB
ADDA (opr)
Add Memory to
A
A+MA
ADDB (opr)
Add Memory to
B
B+MB
ADDD (opr)
Add 16-Bit to D
D + (M : M + 1) D
ANDA (opr)
AND A with
Memory
AMA
ANDB (opr)
AND B with
Memory
BMB
ASL (opr)
Arithmetic Shift
Left
C
ASLA
b0
b7
b0
b7
18
18
18
18
18
18
18
18
18
Instruction
Operand
3A
3A
89
99
B9
A9
A9
C9
D9
F9
E9
E9
8B
9B
BB
AB
AB
CB
DB
FB
EB
EB
C3
D3
F3
E3
E3
84
94
B4
A4
A4
C4
D4
F4
E4
E4
78
68
68
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
Cycles
2
Condition Codes
H
I
N
Z
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
6
6
7
INH
48
INH
58
INH
05
77
67
67
47
hh ll
ff
ff
6
6
7
2
EXT
IND,X
IND,Y
INH
INH
57
REL
24
rr
DIR
IND,X
IND,Y
15
1D
1D
dd mm
ff mm
ff mm
6
7
8
Arithmetic Shift
Left B
C
ASLD
A
A
A
A
A
B
B
B
B
B
Arithmetic Shift
Left A
C
ASLB
b7
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
Opcode
1B
b0
Arithmetic Shift
Left D
0
C b7 A b0 b7 B b0
ASR
Arithmetic Shift
Right
ASRA
Arithmetic Shift
Right A
ASRB
Arithmetic Shift
Right B
BCC (rel)
Branch if Carry
Clear
Clear Bit(s)
b7
b0
b7
b0
b7
BCLR (opr)
(msk)
b0
18
?C=0
M (mm) M
18
Technical Data
Central Processor Unit (CPU)
55
Operation
Description
BCS (rel)
Branch if Carry
Set
Branch if = Zero
Branch if Zero
Branch if > Zero
Branch if
Higher
Branch if
Higher or Same
Bit(s) Test A
with Memory
?C=1
BEQ (rel)
BGE (rel)
BGT (rel)
BHI (rel)
BHS (rel)
BITA (opr)
?C=0
REL
24
rr
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
REL
REL
REL
85
95
B5
A5
A5
C5
D5
F5
E5
E5
2F
25
23
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
rr
rr
2
3
4
4
5
2
3
4
4
5
3
3
3
REL
REL
REL
2D
2B
26
rr
rr
rr
3
3
3
REL
REL
DIR
IND,X
IND,Y
REL
DIR
IND,X
IND,Y
DIR
IND,X
IND,Y
REL
2A
20
13
1F
1F
21
12
1E
1E
14
1C
1C
8D
rr
rr
dd mm rr
ff mm rr
ff mm rr
rr
dd mm rr
ff mm rr
ff mm rr
dd mm
ff mm
ff mm
rr
3
3
6
7
8
3
6
7
8
6
7
8
6
AM
Set Bit(s)
M + mm M
Branch to
Subroutine
Branch if
Overflow Clear
Branch if
Overflow Set
Compare A to B
Clear Carry Bit
Clear Interrupt
Mask
Clear Memory
Byte
See Figure 32
Clear
Accumulator A
Clear
Accumulator B
Clear Overflow
Flag
Compare A to
Memory
0A
0B
CLRB
CLV
CMPA (opr)
A
A
A
A
A
B
B
B
B
B
?NV=1
?N=1
?Z=0
?N=0
?1=1
? M mm = 0
18
18
18
18
18
?V=0
REL
28
rr
?V=1
REL
29
rr
AB
0C
0I
INH
INH
INH
11
0C
0E
2
2
2
0M
7F
6F
6F
4F
hh ll
ff
ff
6
6
7
2
EXT
IND,X
IND,Y
INH
INH
5F
INH
0A
IMM
DIR
EXT
IND,X
IND,Y
81
91
B1
A1
A1
2
3
4
4
5
0V
AM
A
A
A
A
A
18
18
ii
dd
hh ll
ff
ff
Technical Data
56
?1=0
? (M) mm = 0
CLRA
Branch Never
Branch if Bit(s)
Set
CLR (opr)
Condition Codes
H
I
N
Z
? Z + (N V) = 1
?C=1
?C+Z=1
CBA
CLC
CLI
3
3
3
3
Branch if Zero
Branch if Lower
Branch if Lower
or Same
Branch if < Zero
Branch if Minus
Branch if not =
Zero
Branch if Plus
Branch Always
Branch if
Bit(s) Clear
BVS (rel)
rr
rr
rr
rr
BLE (rel)
BLO (rel)
BLS (rel)
BVC (rel)
Cycles
3
27
2C
2E
22
BM
BSR (rel)
Instruction
Operand
rr
REL
REL
REL
REL
Bit(s) Test B
with Memory
BPL (rel)
BRA (rel)
BRCLR(opr)
(msk)
(rel)
BRN (rel)
BRSET(opr)
(msk)
(rel)
BSET (opr)
(msk)
Opcode
25
?Z=1
?NV=0
? Z + (N V) = 0
?C+Z=0
BITB (opr)
BLT (rel)
BMI (rel)
BNE (rel)
Addressing
Mode
REL
MOTOROLA
Operation
Description
CMPB (opr)
Compare B to
Memory
BM
COM (opr)
Ones
Complement
Memory Byte
Ones
Complement
A
Ones
Complement
B
Compare D to
Memory 16-Bit
$FF M M
COMA
COMB
CPD (opr)
B
B
B
B
B
$FF A A
$FF B B
DM:M +1
Addressing
Mode
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
Cycles
2
3
4
4
5
6
6
7
2
Condition Codes
H
I
N
Z
83
93
B3
A3
A3
8C
9C
BC
AC
AC
8C
9C
BC
AC
AC
19
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
5
6
7
7
7
4
5
6
6
7
5
6
7
7
7
2
7A
6A
6A
4A
hh ll
ff
ff
Opcode
C1
D1
F1
E1
18
E1
73
63
18
63
43
Instruction
Operand
ii
dd
hh ll
ff
ff
hh ll
ff
ff
53
1A
1A
1A
1A
CD
6
6
7
2
CPX (opr)
Compare X to
Memory 16-Bit
IX M : M + 1
CPY (opr)
Compare Y to
Memory 16-Bit
IY M : M + 1
DAA
Decimal Adjust
A
Decrement
Memory Byte
Decrement
Accumulator
A
Decrement
Accumulator
B
Decrement
Stack Pointer
Decrement
Index Register
X
Decrement
Index Register
Y
Exclusive OR A
with Memory
A1A
EXT
IND,X
IND,Y
INH
B1B
INH
5A
SP 1 SP
INH
34
IX 1 IX
INH
09
IY 1 IY
INH
09
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
2
3
4
4
5
2
3
4
4
5
41
DEC (opr)
DECA
DECB
DES
DEX
DEY
M1M
AMA
18
18
EORB (opr)
Exclusive OR B
with Memory
BMB
FDIV
Fractional
Divide 16 by 16
Integer Divide
16 by 16
Increment
Memory Byte
D / IX IX; r D
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
D / IX IX; r D
INH
02
41
EXT
IND,X
IND,Y
INH
7C
6C
6C
4C
hh ll
ff
ff
6
6
7
2
EORA (opr)
IDIV
INC (opr)
INCA
Increment
Accumulator
A
A
A
A
A
A
B
B
B
B
B
CD
18
18
18
1A
18
M+1M
A+1A
18
18
18
88
98
B8
A8
A8
C8
D8
F8
E8
E8
03
Technical Data
Central Processor Unit (CPU)
57
Operation
Description
INCB
Increment
Accumulator
B
Increment
Stack Pointer
Increment
Index Register
X
Increment
Index Register
Y
Jump
B+1B
INS
INX
INY
JMP (opr)
Addressing
Mode
B
INH
IX + 1 IX
INH
08
IY + 1 IY
INH
08
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
3
3
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
2
LDAB (opr)
Load
Accumulator
B
MB
LDD (opr)
Load Double
Accumulator
D
M A,M + 1 B
LDS (opr)
Load Stack
Pointer
M : M + 1 SP
LDX (opr)
Load Index
Register
X
M : M + 1 IX
LDY (opr)
Load Index
Register
Y
M : M + 1 IY
LSL (opr)
Logical Shift
Left
C
b7
b0
b7
b0
Logical Shift
Left B
C
b7
b0
INH
58
INH
05
EXT
IND,X
IND,Y
INH
74
64
64
44
hh ll
ff
ff
6
6
7
2
b0
b7
b0
18
18
18
18
18
CD
18
18
18
1A
18
18
A
0
18
7E
6E
6E
9D
BD
AD
AD
86
96
B6
A6
A6
C6
D6
F6
E6
E6
CC
DC
FC
EC
EC
8E
9E
BE
AE
AE
CE
DE
FE
EE
EE
CE
DE
FE
EE
EE
78
68
68
48
b7 A b0 b7 B b0
b7
Logical Shift
Left Double
Logical Shift
Right A
18
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
A
A
A
A
A
B
B
B
B
B
Logical Shift
Left A
C
LSRA
18
Technical Data
58
MA
See Figure 32
Condition Codes
H
I
N
Z
Load
Accumulator
A
Logical Shift
Right
LDAA (opr)
LSR (opr)
31
See Figure 32
LSLD
Cycles
2
INH
Jump to
Subroutine
LSLB
Instruction
Operand
SP + 1 SP
JSR (opr)
LSLA
Opcode
5C
MOTOROLA
Operation
LSRB
Logical Shift
Right B
LSRD
Logical Shift
Right Double
MUL
NEG (opr)
Multiply 8 by 8
Twos
Complement
Memory Byte
Twos
Complement
A
Twos
Complement
B
No operation
OR
Accumulator
A (Inclusive)
NEGA
NEGB
NOP
ORAA (opr)
ORAB (opr)
OR
Accumulator
B (Inclusive)
PSHA
ROL (opr)
Push A onto
Stack
Push B onto
Stack
Push X onto
Stack (Lo
First)
Push Y onto
Stack (Lo
First)
Pull A from
Stack
Pull B from
Stack
Pull X From
Stack (Hi
First)
Pull Y from
Stack (Hi
First)
Rotate Left
ROLA
Rotate Left A
ROLB
Rotate Left B
ROR (opr)
Rotate Right
RORA
Rotate Right A
RORB
Rotate Right B
RTI
Return from
Interrupt
PSHB
PSHX
PSHY
PULA
PULB
PULX
PULY
Addressing
Mode
B
INH
Description
b7
b0
Opcode
54
Instruction
Operand
Condition Codes
H
I
N
Z
INH
04
3D
70
60
60
40
hh ll
ff
ff
10
6
6
7
2
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
2
2
3
4
4
5
2
3
4
4
5
3
b7 A b0 b7 B b0 C
ABD
0MM
0AA
INH
EXT
IND,X
IND,Y
INH
0BB
INH
50
A
A
A
A
A
B+MB
B
B
B
B
B
A Stk,SP = SP 1 A
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
01
8A
9A
BA
AA
AA
CA
DA
FA
EA
EA
36
B Stk,SP = SP 1 B
INH
37
IX Stk,SP = SP 2
INH
3C
IY Stk,SP = SP 2
INH
3C
SP = SP + 1, A Stk A
INH
32
SP = SP + 1, B Stk B
INH
33
SP = SP + 2, IX Stk
INH
38
SP = SP + 2, IY Stk
INH
18
38
hh ll
ff
ff
6
6
7
2
18
79
69
69
49
No Operation
A+MA
b7
b7
b7
b7
b7
b7
18
18
18
18
EXT
IND,X
IND,Y
INH
INH
59
76
66
66
46
hh ll
ff
ff
6
6
7
2
EXT
IND,X
IND,Y
INH
INH
56
INH
3B
12
b0
b0
b0
b0 C
18
b0 C
b0 C
See Figure 32
Cycles
2
Technical Data
Central Processor Unit (CPU)
59
Operation
Description
RTS
Return from
Subroutine
Subtract B from
A
Subtract with
Carry from A
See Figure 32
SBCB (opr)
Subtract with
Carry from B
BMCB
SEC
SEI
Set Carry
Set Interrupt
Mask
Set Overflow
Flag
Store
Accumulator
A
SBA
SBCA (opr)
SEV
STAA (opr)
ABA
Cycles
5
Condition Codes
H
I
N
Z
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
2
3
4
4
5
2
3
4
4
5
2
2
1C
1I
82
92
B2
A2
A2
C2
D2
F2
E2
E2
0D
0F
1V
INH
0B
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
INH
97
B7
A7
A7
D7
F7
E7
E7
DD
FD
ED
ED
CF
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
3
4
4
5
3
4
4
5
4
5
5
6
2
9F
BF
AF
AF
DF
FF
EF
EF
DF
FF
EF
EF
80
90
B0
A0
A0
C0
D0
F0
E0
E0
83
93
B3
A3
A3
3F
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
14
AM
STD (opr)
Store
Accumulator
D
A M, B M + 1
STOP
Stop Internal
Clocks
Store Stack
Pointer
A
A
A
A
A
B
B
B
B
B
A
A
A
A
B
B
B
B
SP M : M + 1
STX (opr)
Store Index
Register X
IX M : M + 1
STY (opr)
Store Index
Register Y
IY M : M + 1
SUBA (opr)
Subtract
Memory from
A
AMA
SUBB (opr)
Subtract
Memory from
B
BMB
SUBD (opr)
Subtract
Memory from
D
DM:M+1D
SWI
Software
Interrupt
Transfer A to B
Transfer A to
CC Register
Transfer B to A
See Figure 32
A
A
A
A
A
A
A
A
A
A
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
18
18
18
18
18
18
CD
18
18
1A
18
18
18
18
AB
A CCR
INH
INH
16
06
2
2
BA
INH
17
Technical Data
60
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
AMCA
BM
TBA
Instruction
Operand
10
Store
Accumulator
B
TAB
TAP
Opcode
39
INH
STAB (opr)
STS (opr)
Addressing
Mode
INH
MOTOROLA
Operation
Description
TEST
TEST (Only in
Test Modes)
Transfer CC
Register to A
Test for Zero or
Minus
A0
B0
TPA
TST (opr)
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
Cycle
*
**
Addressing
Mode
INH
CCR A
Opcode
00
Instruction
Operand
Cycles
*
Condition Codes
H
I
N
Z
INH
07
7D
6D
6D
4D
hh ll
ff
ff
6
6
7
2
EXT
IND,X
IND,Y
INH
INH
5D
SP + 1 IX
INH
30
SP + 1 IY
INH
30
IX 1 SP
INH
35
IY 1 SP
INH
35
INH
3E
**
IX D, D IX
INH
8F
IY D, D IY
INH
8F
M0
18
18
18
18
Operands
dd
= 8-bit direct address ($0000$00FF) (high byte assumed to be $00)
ff
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh
= High-order byte of 16-bit extended address
ii
= One byte of immediate data
jj
= High-order byte of 16-bit immediate data
kk
= Low-order byte of 16-bit immediate data
ll
= Low-order byte of 16-bit extended address
mm
= 8-bit mask (set bits to be affected)
rr
= Signed relative offset $80 (128) to $7F (+127)
(offset relative to address following machine code offset byte))
Operators
()
Contents of register shown inside parentheses
Is transferred to
Boolean AND
+
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
Exclusive-OR
Multiply
:
Concatenation
Condition Codes
Technical Data
Central Processor Unit (CPU)
61
Technical Data
62
MOTOROLA
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.1
Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.2
Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.3.3
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.3.4
Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.4
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.1
RAM and Input/Output Mapping. . . . . . . . . . . . . . . . . . . . . . 78
4.4.2
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4.3
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.4.3.1
System Configuration Register . . . . . . . . . . . . . . . . . . . . 84
4.4.3.2
RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . .87
4.4.3.3
System Configuration Options Register . . . . . . . . . . . . . . 89
4.5
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.5.1
Programming an Individual EPROM Address . . . . . . . . . . . 91
4.5.2
Programming the EPROM with Downloaded Data. . . . . . . . 92
4.5.3
EPROM and EEPROM Programming Control Register . . . . 92
4.6
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6.1
EEPROM and CONFIG Programming and Erasure. . . . . . . 96
4.6.1.1
Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6.1.2
EPROM and EEPROM Programming
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.6.1.3
EEPROM Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.1.4
EEPROM Row Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.1.5
EEPROM Byte Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.6.1.6
CONFIG Register Programming . . . . . . . . . . . . . . . . . .102
4.6.2
EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Technical Data
Operating Modes and On-Chip Memory
63
NOTE:
For the MC68HC811E2, the vector locations are the same; however,
they are contained in the 2048-byte EEPROM array.
Technical Data
64
MOTOROLA
NOTE:
The write enable signal for an external memory is the NAND of the
E clock and the inverted R/W signal.
Technical Data
Operating Modes and On-Chip Memory
65
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
HC373
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
AS
D1
D2
D3
D4
D5
D6
D7
D8
LE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
OE
R/W
E
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
WE
OE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MCU
MOTOROLA
passes to the loaded program at $0000. Refer to Figure 4-2, Figure 4-3,
Figure 4-4, Figure 4-5, and Figure 4-6.
Use of an external pullup resistor is required when using the SCI
transmitter pin because port D pins are configured for wired-OR
operation by the bootloader. In bootstrap mode, the interrupt vectors are
directed to RAM. This allows the use of interrupts through a jump table.
Refer to the application note AN1060 entitled M68HC11 Bootstrap
Mode, that is included in this data book.
Technical Data
Operating Modes and On-Chip Memory
67
$0000
0000
512 BYTES RAM
EXT
EXT
$1000
01FF
1000
103F
$B600
EXT
EXT
BF00
BOOT
ROM
BFC0
BFFF
BFFF
SPECIAL MODES
INTERRUPT
VECTORS
$D000
FFC0
FFFF
$FFFF
EXPANDED
BOOTSTRAP
NORMAL
MODES
INTERRUPT
VECTORS
SPECIAL
TEST
0000
$0000
EXT
$1000
01FF
1000
EXT
EXT
103F
B600
$B600
B7FF
EXT
BF00
BOOT
ROM
BFC0
EXT
BFFF
BFFF
SPECIAL MODES
INTERRUPT
VECTORS
$D000
FFC0
FFFF
$FFFF
EXPANDED
BOOTSTRAP
NORMAL
MODES
INTERRUPT
VECTORS
SPECIAL
TEST
Technical Data
68
MOTOROLA
0000
$0000
EXT
$1000
01FF
1000
EXT
EXT
B600
$B600
103F
B7FF
EXT
EXT
BF00
BOOT
ROM
BFFF
BFFF
$D000
D000
BFC0
12 KBYTES ROM/EPROM
FFC0
FFFF
FFFF
$FFFF
SINGLE
CHIP
EXPANDED
BOOTSTRAP
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL
MODES
INTERRUPT
VECTORS
SPECIAL
TEST
$0000
EXT
$1000
02FF
1000
EXT
EXT
9000
$9000
103F
8 KBYTES ROM/EPROM *
AFFF
EXT
EXT
$B600
B600
B7FF
EXT
EXT
BF00
BOOT
ROM
BFFF
$D000
$FFFF
FFFF
NORMAL
MODES
INTERRUPT
VECTORS
EXPANDED
SINGLE
BOOTSTRAP
SPECIAL
CHIP
TEST
* 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each.
Technical Data
Operating Modes and On-Chip Memory
69
$0000
0000
256 BYTES RAM
EXT
EXT
00FF
$1000
1000
103F
EXT
EXT
BF00
BOOT
ROM
BFFF
F800
FFC0
FFFF
FFFF
$FFFF
SINGLE
CHIP
EXPANDED
BOOTSTRAP
NORMAL
MODES
INTERRUPT
VECTORS
SPECIAL
TEST
Addr.
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 132.
Reset:
$1000
$1001
$1002
Reserved
Bit 7
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
STAI
CWOM
HNDS
OIN
PLS
EGA
INVB
= Reserved
Read:
Parallel I/O Control Register
STAF
(PIOC) Write:
See page 139.
Reset:
0
= Unimplemented
U = Unaffected
Technical Data
70
MOTOROLA
Addr.
$1003
$1004
$1005
$1006
Register Name
Read:
Port C Data Register
(PORTC) Write:
See page 134.
Reset:
Read:
Port B Data Register
(PORTB) Write:
See page 134.
Reset:
Bit 7
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
Read:
Port C Latched Register
PCL7
(PORTCL) Write:
See page 135.
Reset:
Reserved
Read:
Port C Data Direction Register
DDRC7 DDRC6
$1007
(DDRC) Write:
See page 135.
Reset:
0
0
$1008
Read:
Port D Data Register
(PORTD) Write:
See page 136.
Reset:
Read:
Port D Data Direction Register
$1009
(DDRD) Write:
See page 136.
Reset:
$100A
$100B
Read:
Port E Data Register
(PORTE) Write:
See page 137.
Reset:
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
PD5
PD4
PD3
PD2
PD1
PD0
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Read:
Timer Compare Force
FOC1
Register (CFORC) Write:
See page 188.
Reset:
0
FOC2
FOC3
FOC4
FOC5
= Reserved
= Unimplemented
U = Unaffected
Technical Data
Operating Modes and On-Chip Memory
71
Addr.
$100C
$100D
$100E
$100F
Register Name
Bit 7
Bit 0
OC1M5
OC1M4
OC1M3
OC1D6
OC1D5
OC1D4
OC1D3
Read: Bit 15
Timer Counter Register High
(TCNTH) Write:
See page 191.
Reset:
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Timer Counter Register Low
(TCNTL) Write:
See page 191.
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Read:
Output Compare 1 Mask
OC1M7 OC1M6
Register (OC1M) Write:
See page 189.
Reset:
0
0
Read:
Output Compare 1 Data
OC1D7
Register (OC1D) Write:
See page 190.
Reset:
0
Read:
Timer Input Capture 1 Register
Bit 15
$1010
High (TIC1H) Write:
See page 182.
Reset:
Read:
Timer Input Capture 1 Register
$1011
Low (TIC1L) Write:
See page 182.
Reset:
Bit 7
$1013
Bit 6
Bit 5
Bit 4
Bit 3
Read:
Timer Input Capture 2 Register
Bit 15
$1012
High (TIC2H) Write:
See page 183.
Reset:
Read:
TImer Input Capture 2
Register Low (TIC2L) Write:
See page 183.
Reset:
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 5
Bit 4
Bit 3
Read:
Timer Input Capture 3 Register
Bit 15
$1014
High (TIC3H) Write:
See page 183.
Reset:
Bit 14
Bit 13
Bit 12
Bit 11
= Reserved
U = Unaffected
Technical Data
72
MOTOROLA
Addr.
Register Name
Read:
Timer Input Capture 3 Register
$1015
Low (TIC3L) Write:
See page 183.
Reset:
$1016
$1017
$1018
$1019
$101A
$101B
$101C
$101D
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Timer Output Compare 1
Bit 15
Register High (TOC1H) Write:
See page 186.
Reset:
1
Read:
Timer Output Compare 1
Register Low (TOC1L) Write:
See page 186.
Reset:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
= Reserved
Read:
Timer Output Compare 2
Bit 15
Register High (TOC2H) Write:
See page 186.
Reset:
1
Read:
Timer Output Compare 2
Register Low (TOC2L) Write:
See page 186.
Reset:
Read:
Timer Output Compare 3
Bit 15
Register High (TOC3H) Write:
See page 187.
Reset:
1
Read:
Timer Output Compare 3
Register Low (TOC3L) Write:
See page 187.
Reset:
Read:
Timer Output Compare 4
Bit 15
Register High (TOC4H) Write:
See page 187.
Reset:
1
Read:
Timer Output Compare 4
Register Low (TOC4L) Write:
See page 187.
Reset:
= Unimplemented
U = Unaffected
Technical Data
Operating Modes and On-Chip Memory
73
Addr.
$101E
$101F
$1020
$1021
$1022
Register Name
Read:
Timer Input Capture 4/Output
Compare 5 Register Low Write:
(TI4/O5) See page 184.
Reset:
Read:
Timer Control Register 1
(TCTL1) Write:
See page 192.
Reset:
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
TOI
RTII
PAOVI
PAII
PR1
PR0
TOF
RTIF
PAOVF
PAIF
PAEN
0
Read:
Timer Control Register 2
EDG4B
(TCTL2) Write:
See page 181.
Reset:
0
Read:
Timer Interrupt Mask 1
Register (TMSK1) Write:
See page 193.
Reset:
Read:
Timer Interrupt Flag 1
OC1F
(TFLG1) Write:
See page 194.
Reset:
0
Read:
Timer Interrupt Mask 2
Register (TMSK2) Write:
See page 194.
Reset:
Read:
Timer Interrupt Flag 2
(TFLG2) Write:
See page 199.
Reset:
$1025
$1026
Read:
Timer Input Capture 4/Output
Bit 15
Compare 5 Register High Write:
(TI4/O5) See page 184.
Reset:
1
$1023
$1024
Bit 7
Read:
Pulse Accumulator Control
DDRA7
Register (PACTL) Write:
See page 200.
Reset:
0
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
= Reserved
= Unimplemented
U = Unaffected
Technical Data
74
MOTOROLA
Addr.
Register Name
$1027
Read:
Pulse Accumulator Count
Register (PACNT) Write:
See page 204.
Reset:
$1028
Read:
Serial Peripheral Control
Register (SPCR) Write:
See page 171.
Reset:
Read:
Serial Peripheral Status
Register (SPSR) Write:
See page 173.
Reset:
$1029
$102A
Read:
Serial Peripheral Data I/O
Register (SPDR) Write:
See page 174.
Reset:
$102D
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
SPIF
WCOL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Serial Communications
Control Register 1 (SCCR1) Write:
See page 151.
Reset:
Read:
Serial Communications
Control Register 2 (SCCR2) Write:
See page 152.
Reset:
MODF
Read:
Baud Rate Register
TCLR
(BAUD) Write:
See page 155.
Reset:
0
$102B
$102C
Bit 7
SCP2(1)
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
WAKE
R8
T8
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TC
RDRF
IDLE
OR
NF
FE
= Reserved
Read:
Serial Communications Status
TDRE
$102E
Register (SCSR) Write:
See page 153.
Reset:
1
U = Unaffected
Technical Data
Operating Modes and On-Chip Memory
75
Addr.
$102F
$1030
$1031
$1032
$1033
$1034
$1035
Register Name
Bit 7
Read:
Serial Communications Data
R7/T7
Register (SCDR) Write:
See page 150.
Reset:
Bit 0
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
CC
CB
CA
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Read:
Analog-to-Digital Control
Status Register (ADCTL) Write:
See page 216.
Reset:
CCF
Read:
Analog-to-Digital Results
Register 1 (ADR1) Write:
See page 218.
Reset:
Bit 7
Bit 6
Read:
Analog-to-Digital Results
Register 2 (ADR2) Write:
See page 218.
Reset:
Bit 7
Read:
Analog-to-Digital Results
Register 3 (ADR3) Write:
See page 218.
Reset:
Bit 7
Read:
Analog-to-Digital Results
Register 4 (ADR4) Write:
See page 218.
Reset:
Bit 7
Read:
Block Protect Register
(BPROT) Write:
See page 97.
Reset:
Read:
EPROM Programming Control
(1)
$1036
Register (EPROG)
Write:
See page 99.
Reset:
$1037
Reserved
SCAN
MULT
CD
Bit 4
Bit 3
Bit 5
Bit 4
Bit 3
Bit 5
Bit 4
Bit 3
Bit 5
Bit 4
Bit 3
MBE
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
ELAT
EXCOL
EXROW
T1
T0
PGM
= Unimplemented
= Reserved
1. MC68HC711E20 only
U = Unaffected
Technical Data
76
MOTOROLA
Addr.
Register Name
$1038
Reserved
$1039
$103A
Bit 0
CSEL
IRQE(1)
DLY(1)
CME
CR1(1)
CR0 (1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ODD
EVEN
ELAT(2)
BYTE
ROW
ERASE
EELAT
EPGM
SMOD
MDA
IRV(NE)
PSEL3
PSEL2
PSEL1
PSEL0
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
Read:
System Configuration Options
ADPU
Register (OPTION) Write:
See page 89.
Reset:
0
Read:
Arm/Reset COP Timer
Circuitry Register (COPRST) Write:
See page 109.
Reset:
Read:
EPROM and EEPROM
$103B Programming Control Register Write:
(PPROG) See page 93.
Reset:
$103C
Bit 7
Read:
Highest Priority I Bit Interrupt
RBOOT
and Miscellaneous Register Write:
(HPRIO) See page 81.
Reset:
0
$103D
Read:
RAM and I/O Mapping
RAM3
Register (INIT) Write:
See page 87.
Reset:
0
$103E
Reserved
Read:
System Configuration Register
$103F
(CONFIG) Write:
See page 85.
Reset:
Read:
System Configuration Register
$103F
(CONFIG)(3) Write:
See page 85.
Reset:
NOSEC
NOCOP ROMON
EE3
EE2
EE1
EE0
NOSEC
NOCOP
EEON
U
EEON
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.
2. MC68HC711E9 only
3. MC68HC811E2 only
= Unimplemented
= Reserved
U = Unaffected
Technical Data
Operating Modes and On-Chip Memory
77
Technical Data
78
MOTOROLA
VDD
MAX
690
VDD
4.7 k
VOUT
4.8-V
NiCd
TO MODB/VSTBY
OF M68HC11
VBATT
+
Technical Data
Operating Modes and On-Chip Memory
79
MODA
Mode
RBOOT
SMOD
MDA
Single chip
Expanded
Bootstrap
Special test
Technical Data
80
MOTOROLA
Address:
$103C
Bit 7
Read:
Bit 0
MDA(1)
IRV(NE)(1)
PSEL3
PSEL2
PSEL1
PSEL0
Write:
Resets:
Single chip:
Expanded:
Bootstrap:
Test:
1. The reset values depend on the mode selected at the RESET pin rising edge.
Mode
MODB
MODA
SMOD
MDA
Single chip
Expanded
Bootstrap
Special test
Latched at Reset
Technical Data
Operating Modes and On-Chip Memory
81
IRVNE Out
of Reset
E Clock Out
of Reset
IRV Out
of Reset
IRVNE
Affects Only
IRVNE Can
Be Written
Single chip
On
Off
Once
Expanded
On
Off
IRV
Once
Bootstrap
On
Off
Once
Special test
On
On
IRV
Once
Technical Data
82
MOTOROLA
SMOD = 1
Register
Address
Register Name
Must be Written
in First 64 Cycles
$x024
Bits [7:2]
$x035
$x039
System configuration
options (OPTION)
$x03C
See HPRIO
description
See HPRIO
description
$x03D
$x024
$x035
$x039
$x03C
See HPRIO
description
$x03D
Write
Anytime
See HPRIO
description
All, set or clear
Technical Data
Operating Modes and On-Chip Memory
83
Bulk erase
Byte programming
Communication server
NOTE:
Technical Data
84
MOTOROLA
Address:
$103F
Bit 7
Bit 0
NOSEC
NOCOP
ROMON
EEON
Read:
Write:
Resets:
Single chip:
Bootstrap:
U(L)
Expanded:
Test:
U(L)
= Unimplemented
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch
prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Address:
$103F
Bit 7
EE3
EE2
EE1
EE0
NOSEC
NOCOP
Single chip:
Bootstrap:
U(L)
Expanded:
Test:
U(L)
Read:
Bit 0
EEON
Write:
Resets:
= Unimplemented
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch
prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Technical Data
Operating Modes and On-Chip Memory
85
EEPROM Location
0000
$0800$0FFF
0001
$1800$1FFF
0010
$2800$2FFF
0011
$3800$3FFF
0100
$4800$4FFF
0101
$5800$5FFF
0110
$6800$6FFF
0111
$7800$7FFF
1000
$8800$8FFF
1001
$9800$9FFF
1010
$A800$AFFF
1011
$B800$BFFF
1100
$C800$CFFF
1101
$D800$DFFF
1110
$E800$EFFF
1111
$F800$FFFF
Technical Data
86
MOTOROLA
$103D
Bit 7
Bit 0
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
Read:
Write:
Reset:
Technical Data
Operating Modes and On-Chip Memory
87
RAM[3:0]
Address
REG[3:0]
Address
0000
$0000$0xFF
0000
$0000$003F
0001
$1000$1xFF
0001
$1000$103F
0010
$2000$2xFF
0010
$2000$203F
0011
$3000$3xFF
0011
$3000$303F
0100
$4000$4xFF
0100
$4000$403F
0101
$5000$5xFF
0101
$5000$503F
0110
$6000$6xFF
0110
$6000$603F
0111
$7000$7xFF
0111
$7000$703F
1000
$8000$8xFF
1000
$8000$803F
1001
$9000$9xFF
1001
$9000$903F
1010
$A000$AxFF
1010
$A000$A03F
1011
$B000$BxFF
1011
$B000$B03F
1100
$C000$CxFF
1100
$C000$C03F
1101
$D000$DxFF
1101
$D000$D03F
1110
$E000$ExFF
1110
$E000$E03F
1111
$F000$FxFF
1111
$F000$F03F
Technical Data
88
MOTOROLA
Read:
$1039
Bit 7
ADPU
CSEL
IRQE(1)
DLY(1)
CME
Bit 0
CR1 (1)
CR0 (1)
Write:
Reset:
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during
special modes.
= Unimplemented
Technical Data
Operating Modes and On-Chip Memory
89
4.5 EPROM/OTPROM
Certain devices in the M68HC11 E series include on-chip
EPROM/OTPROM. For instance:
MOTOROLA
NOTE:
LDAB
STAB
#$20
$103B
STAA
LDAB
STAB
$0,X
#$21
$103B
JSR
CLR
DLYEP
$103B
LDAB
STAB
#$20
$1036
STAA
LDAB
STAB
$0,X
#$21
$1036
JSR
CLR
DLYEP
$1036
Technical Data
Operating Modes and On-Chip Memory
91
Technical Data
92
MOTOROLA
Address:
$103B
Bit 7
Bit 0
ODD
EVEN
ELAT(1)
BYTE
ROW
ERASE
EELAT
EPGM
Read:
Write:
Reset:
1. MC68HC711E9 only
Technical Data
Operating Modes and On-Chip Memory
93
Address:
$1036
Bit 7
Bit 0
ELAT
EXCOL
EXROW
T1
T0
PGM
Read:
MBE
Write:
Reset:
= Unimplemented
MOTOROLA
T0
Function Selected
Normal mode
Reserved
Gate stress
Drain stress
Technical Data
Operating Modes and On-Chip Memory
95
4.6 EEPROM
Some E-series devices contain 512 bytes of on-chip EEPROM. The
MC68HC811E2 contains 2048 bytes of EEPROM with selectable base
address. All E-series devices contain the EEPROM-based CONFIG
register.
Technical Data
96
MOTOROLA
$1035
Bit 7
Bit 0
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
Read:
Write:
Reset:
= Unimplemented
Technical Data
Operating Modes and On-Chip Memory
97
Block Protected
Block Size
BPRT0
$B600$B61F
32 bytes
BPRT1
$B620$B65F
64 bytes
BPRT2
$B660$B6DF
128 bytes
BPRT3
$B6E0$B7FF
288 bytes
Block Protected
Block Size
BPRT0
$x800$x9FF(1)
512 bytes
BPRT1
$xA00$xBFF(1)
512 bytes
BPRT2
$xC00$xDFF(1)
512 bytes
BPRT3
$xE00$xFFF(1)
512 bytes
Technical Data
98
MOTOROLA
$103B
Bit 7
Bit 0
ODD
EVEN
ELAT(1)
BYTE
ROW
ERASE
EELAT
EPGM
Read:
Write:
Reset:
1. MC68HC711E9 only
Technical Data
Operating Modes and On-Chip Memory
99
ROW
Action
Byte erase
Byte erase
LDAB
STAB
STAA
#$02
$103B
$XXXX
LDAB
STAB
JSR
CLR
#$03
$103B
DLY10
$103B
EELAT = 1
Set EELAT bit
Store data to EEPROM address
(for valid EEPROM address see memory
map for each device)
EELAT = 1, EPGM = 1
Turn on programming voltage
Delay 10 ms
Turn off high voltage and set
to READ mode
Technical Data
100
MOTOROLA
LDAB
#$06
EELAT = 1, ERASE = 1
STAB
$103B
STAA
$XXXX
LDAB
#$07
STAB
$103B
JSR
DLY10
Delay 10 ms
CLR
$103B
LDAB
#$0E
STAB
$103B
STAB
0,X
LDAB
#$0F
STAB
$103B
JSR
DLY10
Delay 10 ms
CLR
$103B
Technical Data
Operating Modes and On-Chip Memory
101
LDAB
#$16
STAB
$103B
STAB
0,X
LDAB
#$17
STAB
$103B
JSR
DLY10
Delay 10 ms
CLR
$103B
NOTE:
Technical Data
102
MOTOROLA
Technical Data
Operating Modes and On-Chip Memory
103
Technical Data
104
MOTOROLA
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.2
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . 108
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.5
System Configuration Options Register . . . . . . . . . . . . . . . 110
5.3.6
Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . 111
5.4
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.1
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . 113
5.4.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.4.3
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.4.4
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.4.5
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.4.6
Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . 114
5.4.7
Serial Communications Interface (SCI) . . . . . . . . . . . . . . . 114
5.4.8
Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . 115
5.4.9
Analog-to-Digital (A/D) Converter. . . . . . . . . . . . . . . . . . . . 115
5.4.10 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5
Reset and Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5.1
Highest Priority Interrupt and Miscellaneous Register . . . . 117
5.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.6.1
Interrupt Recognition and Register Stacking . . . . . . . . . . . 120
5.6.2
Non-Maskable Interrupt Request (XIRQ) . . . . . . . . . . . . . .121
5.6.3
Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.6.4
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.6.5
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.6.6
Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . 122
M68HC11E Family Rev. 3.0
MOTOROLA
Technical Data
Resets and Interrupts
105
5.2 Introduction
Resets and interrupt operations load the program counter with a vector
that points to a new location from which instructions are to be fetched. A
reset immediately stops execution of the current instruction and forces
the program counter to a known starting address. Internal registers and
control bits are initialized so the MCU can resume executing instructions.
An interrupt temporarily suspends normal program execution while an
interrupt service routine is being executed. After an interrupt has been
serviced, the main program resumes as if there had been no
interruption.
5.3 Resets
The four possible sources of reset are:
POR and RESET share the normal reset vector. COP reset and the
clock monitor reset each has its own vector.
Technical Data
106
MOTOROLA
NOTE:
CAUTION:
Technical Data
Resets and Interrupts
107
Divide
E/215 By
00
32.768 ms
16.384 ms
10.923 ms
8.19 ms
01
131.072 ms
65.536 ms
43.691 ms
32.8 ms
10
16
524.28 ms
262.14 ms
174.76 ms
131 ms
11
64
2.098 s
1.049 s
699.05 ms
524 ms
E=
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
Technical Data
108
MOTOROLA
Address:
$103A
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Technical Data
Resets and Interrupts
109
$1039
Bit 7
ADPU
CSEL
IRQE(1)
DLY(1)
CME
Read:
Bit 0
CR1(1)
CR0(1)
Write:
Reset:
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
= Unimplemented
Technical Data
110
MOTOROLA
$103F
Bit 7
Bit 0
EE3
EE2
EE1
EE0
NOSEC
NOCOP
ROMON
EEON
Read:
Write:
Reset:
Technical Data
Resets and Interrupts
111
Normal Mode
Vector
Special Test
or Bootstrap
$FFFE, FFFF
$BFFE, $BFFF
$FFFC, FFFD
$BFFC, $BFFD
$FFFA, FFFB
$BFFA, $BFFB
These initial states then control on-chip peripheral systems to force them
to known startup states, as described in the following subsections.
Technical Data
112
MOTOROLA
5.4.3 Timer
During reset, the timer system is initialized to a count of $0000. The
prescaler bits are cleared, and all output compare registers are initialized
to $FFFF. All input capture registers are indeterminate after reset. The
output compare 1 mask (OC1M) register is cleared so that successful
OC1 compares do not affect any I/O pins. The other four output
compares are configured so that they do not affect any I/O pins on
successful compares. All input capture edge-detector circuits are
configured for capture disabled operation. The timer overflow interrupt
flag and all eight timer function interrupt flags are cleared. All nine timer
interrupts are disabled because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5
function as OC5; however, the OM5:OL5 control bits in the TCTL1
register are clear so OC5 does not control the PA3 pin.
Technical Data
Resets and Interrupts
113
Technical Data
114
MOTOROLA
5.4.10 System
The EEPROM programming controls are disabled, so the memory
system is configured for normal read operation. PSEL[3:0] are initialized
with the value %0110, causing the external IRQ pin to have the highest
I-bit interrupt priority. The IRQ pin is configured for level-sensitive
operation (for wired-OR systems). The RBOOT, SMOD, and MDA bits in
the HPRIO register reflect the status of the MODB and MODA inputs at
the rising edge of reset. MODA and MODB inputs select one of the four
operating modes. After reset, writing SMOD and MDA in special modes
causes the MCU to change operating modes. Refer to the description of
HPRIO register in Section 4. Operating Modes and On-Chip Memory
for a detailed description of SMOD and MDA. The DLY control bit is set
to specify that an oscillator startup delay is imposed upon recovery from
stop mode. The clock monitor system is disabled because CME is
cleared.
Technical Data
Resets and Interrupts
115
Technical Data
116
MOTOROLA
masking by the I bit in the CCR, or by any associated local bits. Interrupt
vectors are not affected by priority assignment. To avoid race conditions,
HPRIO can be written only while I-bit interrupts are inhibited.
$103C
Bit 7
Read:
RBOOT(1) SMOD(1)
Bit 0
MDA(1)
IRVNE
PSEL2
PSEL2
PSEL1
PSEL0
Write:
Reset:
Single chip:
Expanded:
Bootstrap:
Special test:
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
RESET pin rising edge. Refer to Table 4-1. Hardware Mode Select Summary.
Technical Data
Resets and Interrupts
117
0000
Timer overflow
0001
0010
0011
0100
0101
0110
0111
Real-time interrupt
1000
1001
1010
1011
1100
1101
1110
1111
Technical Data
118
MOTOROLA
5.6 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The
15 maskable interrupts are generated by on-chip peripheral systems.
These interrupts are recognized when the global interrupt mask bit (I) in
the condition code register (CCR) is clear. The three non-maskable
interrupt sources are illegal opcode trap, software interrupt, and XIRQ
pin. Refer to Table 5-4, which shows the interrupt sources and vector
assignments for each source.
Table 5-4. Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
FFD6, D7
Local
Mask
FFD8, D9
SPIE
FFDA, DB
PAII
FFDC, DD
PAOVI
FFDE, DF
Timer overflow
TOI
FFE0, E1
I4/O5I
FFE2, E3
OC4I
FFE4, E5
OC3I
FFE6, E7
OC2I
FFE8, E9
OC1I
FFEA, EB
IC3I
FFEC, ED
IC2I
FFEE, EF
IC1I
FFF0, F1
Real-time interrupt
RTII
FFF2, F3
None
FFF4, F5
XIRQ pin
None
FFF6, F7
Software interrupt
None
None
FFF8, F9
None
None
FFFA, FB
COP failure
None
NOCOP
FFFC, FD
None
CME
FFFE, FF
RESET
None
None
CCR
Mask Bit
RIE
RIE
TIE
TCIE
ILIE
Technical Data
Resets and Interrupts
119
CPU Registers
SP
PCL
SP1
PCH
SP2
IYL
SP3
IYH
SP4
IXL
SP5
IXH
SP6
ACCA
SP7
ACCB
SP8
CCR
Technical Data
120
MOTOROLA
Technical Data
Resets and Interrupts
121
Technical Data
122
MOTOROLA
HIGHEST
PRIORITY
POWER-ON RESET
(POR)
LOWEST
PRIORITY
COP WATCHDOG
TIMEOUT
(WITH NOCOP = 0)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFE, $FFFF
(VECTOR FETCH)
1A
BEGIN INSTRUCTION
SEQUENCE
BIT X IN
CCR = 1?
N
XIRQ
PIN LOW?
2A
STACK CPU
REGISTERS
SET BITS I AND X
FETCH VECTOR
$FFF4, $FFF5
Technical Data
Resets and Interrupts
123
2A
BIT I IN
CCR = 1?
N
ANY I-BIT
INTERRUPT
PENDING?
STACK CPU
REGISTERS
N
FETCH OPCODE
STACK CPU
REGISTERS
ILLEGAL
OPCODE?
FETCH VECTOR
$FFF8, $FFF9
WAI
Y
INSTRUCTION?
STACK CPU
REGISTERS
N
Y
STACK CPU
REGISTERS
SWI
INSTRUCTION?
N
RESTORE CPU
REGISTERS
FROM STACK
RTI
INSTRUCTION?
N
EXECUTE THIS
INSTRUCTION
ANY
INTERRUPT
PENDING?
Y
SET BIT I IN CCR
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
SEE FIGURE 52
1A
Technical Data
124
MOTOROLA
BEGIN
X BIT
IN CCR
SET ?
YES
NO
XIRQ PIN
LOW ?
YES
SET X BIT IN CCR
FETCH VECTOR
$FFF4, FFF5
NO
HIGHEST
PRIORITY
INTERRUPT
?
NO
IRQ ?
YES
FETCH VECTOR
YES
FETCH VECTOR
$FFF2, FFF3
NO
RTII = 1 ?
YES
NO
REAL-TIME
INTERRUPT
?
YES
FETCH VECTOR
$FFF0, FFF1
YES
FETCH VECTOR
$FFEE, FFEF
YES
FETCH VECTOR
$FFEC, FFED
YES
FETCH VECTOR
$FFEA, FFEB
YES
FETCH VECTOR
$FFE8, FFE9
NO
YES
IC1I = 1 ?
NO
TIMER
IC1F ?
NO
YES
IC2I = 1 ?
NO
TIMER
IC2F ?
NO
YES
IC3I = 1 ?
NO
TIMER
IC3F ?
NO
YES
OC1I = 1 ?
NO
TIMER
OC1F ?
NO
2B
2A
Technical Data
Resets and Interrupts
125
2A
2B
Y
OC2I = 1?
FLAG
OC2F = 1?
FETCH VECTOR
$FFE6, $FFE7
FETCH VECTOR
$FFE4, $FFE5
FETCH VECTOR
$FFE2, $FFE3
FETCH VECTOR
$FFE0, $FFE1
FETCH VECTOR
$FFDE, $FFDF
FETCH VECTOR
$FFDC, $FFDD
FETCH VECTOR
$FFDA, $FFDB
FETCH VECTOR
$FFD8, $FFD9
OC3I = 1?
FLAG
OC3F = 1
N
OC4I = 1?
FLAG
OC4F = 1?
N
I4/O5I = 1?
FLAG
I4/O5IF = 1?
N
N
Y
TOI = 1?
FLAG
TOF = 1?
N
PAOVI = 1?
FLAG
PAOVF = 1
N
PAII = 1?
FLAG
PAIF = 1?
N
SPIE = 1?
FLAGS
SPIF = 1? OR
MODF = 1?
N
N
SCI
INTERRUPT?
SEE FIGURE
53
FETCH VECTOR
$FFD6, $FFD7
FETCH VECTOR
$FFF2, $FFF3
END
MOTOROLA
BEGIN
FLAG
RDRF = 1?
N
Y
OR = 1?
RIE = 1?
TDRE = 1?
TIE = 1?
TE = 1?
TC = 1?
RE = 1?
TCIE = 1?
IDLE = 1?
Y
ILIE = 1?
N
N
NO
VALID SCI REQUEST
RE = 1?
Technical Data
Resets and Interrupts
127
Technical Data
128
MOTOROLA
Because all clocks are stopped in this mode, all internal peripheral
functions also stop. The data in the internal RAM is retained as long as
VDD power is maintained. The CPU state and I/O pin levels are static and
are unchanged by stop. Therefore, when an interrupt comes to restart
the system, the MCU resumes processing as if there were no
interruption. If reset is used to restart the system, a normal reset
sequence results in which all I/O pins and functions are also restored to
their initial states.
To use the IRQ pin as a means of recovering from stop, the I bit in the
CCR must be clear (IRQ not masked). The XIRQ pin can be used to
wake up the MCU from stop regardless of the state of the X bit in the
CCR, although the recovery sequence depends on the state of the X bit.
If X is set to 0 (XIRQ not masked), the MCU starts up, beginning with the
stacking sequence leading to normal service of the XIRQ request. If X is
set to 1 (XIRQ masked or inhibited), then processing continues with the
instruction that immediately follows the STOP instruction, and no XIRQ
interrupt service is requested or pending.
Because the oscillator is stopped in stop mode, a restart delay may be
imposed to allow oscillator stabilization upon leaving stop. If the internal
oscillator is being used, this delay is required; however, if a stable
external oscillator is being used, the DLY control bit can be used to
bypass this startup delay. The DLY control bit is set by reset and can be
optionally cleared during initialization. If the DLY equal to 0 option is
used to avoid startup delay on recovery from stop, then reset should not
be used as the means of recovering from stop, as this causes DLY to be
set again by reset, imposing the restart delay. This same delay also
applies to power-on reset, regardless of the state of the DLY control bit,
but does not apply to a reset while the clocks are running.
Technical Data
Resets and Interrupts
129
Technical Data
130
MOTOROLA
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.8
6.9
6.2 Introduction
All M68HC11 E-series MCUs have five input/output (I/O) ports and up to
38 I/O lines, depending on the operating mode. Refer to Table 6-1 for a
summary of the ports and their shared functions.
Table 6-1. Input/Output Ports
Port
Input
Pins
Output
Pins
Bidirectional
Pins
Port A
Timer
Port B
High-order address
Port C
Port D
Port E
Shared Functions
Technical Data
Parallel Input/Output (I/O) Ports
131
6.3 Port A
Port A shares functions with the timer system and has:
Address:
$1000
Bit 7
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Alternate function:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
Read:
Write:
Reset:
Technical Data
132
MOTOROLA
Address:
$1026
Bit 7
Bit 0
DDRA7
PAEWN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Read:
Write:
Reset:
NOTE:
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
PAEN Pulse Accumulator System Enable Bit
Refer to Section 9. Timing System.
PAMOD Pulse Accumulator Mode Bit
Refer to Section 9. Timing System.
PEDGE Pulse Accumulator Edge Control Bit
Refer to Section 9. Timing System.
DDRA3 Data Direction for Port A Bit 3
This bit is overridden if an output compare function is configured to
control the PA3 pin.
0 = Input
1 = Output
I4/O5 Input Capture 4/Output Compare 5 Bit
Refer to Section 9. Timing System.
RTR[1:0] RTI Interrupt Rate Select Bits
Refer to Section 9. Timing System.
Technical Data
Parallel Input/Output (I/O) Ports
133
$1004
Bit 7
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
Write:
Reset:
6.5 Port C
In single-chip and bootstrap modes, port C pins reset to high-impedance
inputs. (DDRC bits are set to 0.) In expanded and special test modes,
port C pins are multiplexed address/data bus and the port C register
address is treated as an external memory location.
Address:
$1003
Bit 7
Bit 0
PC5
PC4
PC3
PC2
PC1
PC0
ADDR2
DATA2
ADDR1
DATA1
ADDR0
DATA0
PC7
PC6
Write:
Reset:
ADDR7
DATA7
ADDR6
DATA6
ADDR5
DATA5
ADDR4
DATA4
ADDR3
DATA3
Technical Data
134
MOTOROLA
Address:
$1005
Bit 7
Bit 0
PCL7
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
Read:
Write:
Reset:
$1007
Bit 7
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Read:
Write:
Reset:
Technical Data
Parallel Input/Output (I/O) Ports
135
$1008
Bit 7
Bit 0
PD5
PD4
PD3
PD2
PD1
PD0
Reset:
Alternate Function:
PD5
SS
PD4
SCK
PD3
MOSI
PD2
MISO
PD1
Tx
PD0
RxD
Read:
Write:
Address:
$1009
Bit 7
Bit 0
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
Read:
Write:
Reset:
= Unimplemented
Technical Data
136
MOTOROLA
6.7 Port E
Port E is used for general-purpose static inputs or pins that share
functions with the analog-to-digital (A/D) converter system. When some
port E pins are being used for general-purpose input and others are
being used as A/D inputs, PORTE should not be read during the sample
portion of an A/D conversion.
Address:
$100A
Bit 7
Bit 0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
AN2
AN1
AN0
Read:
Write:
Reset:
Alternate Function:
AN6
AN5
AN4
AN3
Technical Data
Parallel Input/Output (I/O) Ports
137
Technical Data
138
MOTOROLA
$1002
Bit 7
Bit 0
STAF
STAI
CWOM
HNDS
OIN
PLS
EGA
INVB
Read:
Write:
Reset:
U = Unaffected
Technical Data
Parallel Input/Output (I/O) Ports
139
Technical Data
140
MOTOROLA
Read
PIOC with
STAF = 1
then read
PORTCL
Full-input
handshake
mode
Read
PIOC with
STAF = 1
then read
PORTCL
Fulloutput
handshake
mode
Read
PIOC with
STAF = 1
then write
PORTCL
HNDS OIN
PLS
EGA
0 = STRB
active level
1 = STRB
active pulse
Inputs latched
into PORTCL on
any active edge
on STRA
1
0
0
1
Port C
Driven
STRA
Follow Active Edge Follow
DDRC
DDRC
Port C
Inputs latched
STRB pulses
into PORTCL on
on writes
any active edge
to PORTB
on STRA
0
1
0 = STRB
active level
1 = STRB
active pulse
Port B
Normal output
port,
unaffected in
handshake
modes
Driven as outputs
Normal output
if STRA at active
port,
level; follows
unaffected in
DDRC
handshake
if STRA not at
modes
active level
Technical Data
Parallel Input/Output (I/O) Ports
141
Technical Data
142
MOTOROLA
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.3
7.4
7.5
7.6
Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.6.1
Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.6.2
Address-Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.7
7.8
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
7.8.1
Serial Communications Data Register . . . . . . . . . . . . . . . . 150
7.8.2
Serial Communications Control Register 1 . . . . . . . . . . . . 151
7.8.3
Serial Communications Control Register 2 . . . . . . . . . . . . 152
7.8.4
Serial Communication Status Register. . . . . . . . . . . . . . . . 153
7.8.5
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.9
7.10
7.2 Introduction
The serial communications interface (SCI) is a universal asynchronous
receiver transmitter (UART), one of two independent serial input/output
(I/O) subsystems in the M68HC11 E series of microcontrollers. It has a
standard non-return-to-zero (NRZ) format (one start bit , eight or nine
data bits, and one stop bit). Several baud rates are available. The SCI
Technical Data
Serial Communications Interface (SCI)
143
Technical Data
144
MOTOROLA
WRITE ONLY
TRANSMITTER
BAUD RATE
CLOCK
SCDR Tx BUFFER
DDD1
10 (11) - BIT Tx SHIFT REGISTER
2
BREAKJAM 0s
PREAMBLEJAM 1s
JAM ENABLE
SHIFT ENABLE
TRANSFER Tx BUFFER
SIZE 8/9
H (8) 7
SEE NOTE
PIN BUFFER
AND CONTROL
PD1
TxD
FORCE PIN
DIRECTION (OUT)
TRANSMITTER
CONTROL LOGIC
FE
NF
OR
IDLE
RDRF
TC
TDRE
WAKE
T8
R8
8
TDRE
TIE
TC
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
TCIE
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Note: Refer to Figure B-1. EVBU Schematic Diagram for an example of connecting TxD to a PC.
Technical Data
Serial Communications Interface (SCI)
145
Idle-line wakeup
Address-mark wakeup
Technical Data
146
MOTOROLA
RECEIVER
BAUD RATE
CLOCK
SEE NOTE
DATA
RECOVERY
PIN BUFFER
AND CONTROL
PD0
RxD
10 (11) - BIT
Rx SHIFT REGISTER
STOP
16
START
DDD0
(8) 7
MSB
DISABLE
DRIVER
ALL 1s
RE
WAKEUP
LOGIC
RWU
FE
NF
OR
IDLE
RDRF
TC
TDRE
WAKE
T8
R8
SCDR Rx BUFFER
READ ONLY
8
RDRF
RIE
IDLE
ILIE
OR
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
RIE
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Note: Refer to Figure B-1. EVBU Schematic Diagram for an example of connecting RxD to a PC.
Technical Data
Serial Communications Interface (SCI)
147
Technical Data
148
MOTOROLA
there is a loss of efficiency because of the extra bit time for each
character (address bit) required for all characters.
Technical Data
Serial Communications Interface (SCI)
149
The SCI registers are the same for all M68HC11 E-series devices with
one exception. The SCI system for MC68HC(7)11E20 contains an extra
bit in the BAUD register that provides a greater selection of baud
prescaler rates. Refer to 7.8.5 Baud Rate Register, Figure 7-8, and
Figure 7-9.
Reads access the receive data buffer and writes access the transmit
data buffer. Receive and transmit are double buffered.
Address:
$102F
Bit 7
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Read:
Write:
Reset:
Technical Data
150
MOTOROLA
$102C
Bit 7
R8
T8
WAKE
Bit 0
Read:
Write:
Reset:
Technical Data
Serial Communications Interface (SCI)
151
$102D
Bit 7
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read:
Write:
Reset:
Technical Data
152
MOTOROLA
$102E
Bit 7
TDRE
TC
RDRF
IDLE
OR
NF
FE
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
Serial Communications Interface (SCI)
153
Technical Data
154
MOTOROLA
$102B
Bit 7
Bit 0
TCLR
SCP2
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
Read:
Write:
Reset:
U = Unaffected
NOTE:
Technical Data
Serial Communications Interface (SCI)
155
16.00
4.00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
2
4
8
16
32
64
128
62500
31250
15625
7813
3906
1953
977
488
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
3
3
3
3
3
3
3
1
2
4
8
16
32
64
128
20833
10417
5208
2604
1302
651
326
163
25600
12800
6400
3200
1600
800
400
200
41667
20833
10417
5208
2604
1302
651
326
52083
26042
13021
6510
3255
1628
814
407
62500
31250
15625
7813
3906
1953
977
488
83333
41667
20833
10417
5208
2604
1302
651
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
4
4
4
4
4
4
4
1
2
4
8
16
32
64
128
15625
7813
3906
1953
977
488
244
122
19200
9600
4800
2400
1200
600
300
150
31250
15625
7813
3906
1953
977
488
244
39063
19531
9766
4883
2441
1221
610
305
46875
23438
11719
5859
2930
1465
732
366
62500
31250
15625
7813
3906
1953
977
488
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
13
13
13
13
13
13
13
13
1
2
4
8
16
32
64
128
4808
2404
1202
601
300
150
75
38
5908
2954
1477
738
369
185
92
46
9615
4808
2404
1202
601
300
150
75
12019
6010
3005
1502
751
376
188
94
14423
7212
3606
1803
901
451
225
113
19231
9615
4808
2404
1202
601
300
150
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
39
39
39
39
39
39
39
39
1
2
4
8
16
32
64
128
1603
801
401
200
100
50
25
13
1969
985
492
246
123
62
31
15
3205
1603
801
401
200
100
50
25
4006
2003
1002
501
250
125
63
31
4808
2404
1202
601
300
150
75
38
6410
3205
1603
801
401
200
100
50
Technical Data
156
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
157
EXTAL
OSCILLATOR
AND
CLOCK GENERATOR
(4)
XTAL
13
SCP[1:0]
E
0:0
AS
0:1
1:0
1:1
SCR[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
16
1:0:1
1:1:0
1:1:1
SCI
TRANSMIT
BAUD RATE
(1X)
SCI
RECEIVE
BAUD RATE
(16X)
Technical Data
158
MOTOROLA
EXTAL
OSCILLATOR
AND
CLOCK GENERATOR
(4)
XTAL
13
39
SCP[2:0]*
E
0:0:0
AS
0:0:1
0:1:0
0:1:1
1:0:0
SCR[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
16
2
1:0:0
1:0:1
1:1:0
1:1:1
SCI
TRANSMIT
BAUD RATE
(1X)
SCI
RECEIVE
BAUD RATE
(16X)
Technical Data
Serial Communications Interface (SCI)
159
Technical Data
160
MOTOROLA
busy and becomes idle, which prevents repeated interrupts for the whole
time RxD remains idle.
BEGIN
FLAG
RDRF = 1?
OR = 1?
RIE = 1?
TDRE = 1?
TIE = 1?
TC = 1?
RE = 1?
TE = 1?
TCIE = 1?
IDLE = 1?
Y
ILIE = 1?
N
N
NO
VALID SCI REQUEST
RE = 1?
Technical Data
Serial Communications Interface (SCI)
161
Technical Data
162
MOTOROLA
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
8.3
8.4
8.5
8.6
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.6.1
Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.6.2
Master Out/Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.6.3
Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.6.4
Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.7
8.8
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
8.8.1
Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . 171
8.8.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . 173
8.8.3
Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . .174
Technical Data
Serial Peripheral Interface (SPI)
163
Frequency synthesizers
Other microprocessors
Technical Data
164
MOTOROLA
MSB
LSB
MISO
PD2
M
S
MOSI
PD3
INTERNAL
MCU CLOCK
2 4 16 32
CLOCK
SELECT
SPI INTERRUPT
REQUEST
SEC
DWOM
MSTD
SPRO
SPRI
CPHA
CPOL
INSTR
DWOM
SPIF
MODE
WCOL
MSTR
SPE
SPE
SPRO
SPRI
SCK
PD4
SS
PD5
SPI CONTROL
SPIF
S
M
CLOCK
LOGIC
INTERNAL
DATA BUS
Technical Data
Serial Peripheral Interface (SPI)
165
SCK CYCLE #
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
MSB
LSB
SAMPLE INPUT
MSB
LSB
SS (TO SLAVE)
SLAVE CPHA = 1 TRANSFER IN PROGRESS
3
MASTER TRANSFER IN PROGRESS
2
1
4
SLAVE CPHA = 0 TRANSFER IN PROGRESS
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
Technical Data
166
MOTOROLA
Any SPI output line must have its corresponding data direction bit in
DDRD register set. If the DDR bit is clear, that line is disconnected from
the SPI logic and becomes a general-purpose input. All SPI input lines
are forced to act as inputs regardless of the state of the corresponding
DDR bits in DDRD register.
Technical Data
Serial Peripheral Interface (SPI)
167
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
169
Technical Data
170
MOTOROLA
$1028
Bit 7
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
Read:
Write:
Reset:
U = Unaffected
Technical Data
Serial Peripheral Interface (SPI)
171
Divide
E Clock By
Frequency at
E = 1 MHz (Baud)
Frequency at
E = 2 MHz (Baud)
Frequency at
E = 3 MHz (Baud)
Frequency at
E = 4 MHz (Baud)
00
500 kHz
1.0 MHz
1.5 MHz
2 MHz
01
250 kHz
500 kHz
750 kHz
1 MHz
10
16
62.5 kHz
125 kHz
187.5 kHz
250 kHz
11
32
31.3 kHz
62.5 kHz
93.8 kHz
125 kHz
Technical Data
172
MOTOROLA
$1029
Bit 7
SPIF
WCOL
Bit 0
Read:
MODF
Write:
Reset:
= Unimplemented
Technical Data
Serial Peripheral Interface (SPI)
173
$102A
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Technical Data
174
MOTOROLA
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.3
9.4
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
9.4.1
Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.4.2
Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . 182
9.4.3
Timer Input Capture 4/Output Compare 5 Register . . . . . . 184
9.5
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
9.5.1
Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . 185
9.5.2
Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 188
9.5.3
Output Compare Mask Register. . . . . . . . . . . . . . . . . . . . . 189
9.5.4
Output Compare Data Register . . . . . . . . . . . . . . . . . . . . . 190
9.5.5
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
9.5.6
Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 192
9.5.7
Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . 193
9.5.8
Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 194
9.5.9
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 194
9.5.10 Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . . 196
9.6
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.6.1
Timer Interrupt Mask Register 2. . . . . . . . . . . . . . . . . . . . . 198
9.6.2
Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . . 199
9.6.3
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 200
9.7
9.8
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.8.1
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 203
9.8.2
Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . .204
9.8.3
Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . 205
Technical Data
Timing System
175
Timing System
9.2 Introduction
The M68HC11 timing system is composed of five clock divider chains.
The main clock divider chain includes a 16-bit free-running counter,
which is driven by a programmable prescaler. The main timers
programmable prescaler provides one of the four clocking rates to drive
the 16-bit counter. Two prescaler control bits select the prescale rate.
The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off
of this main clocking chain drive circuitry that generates the slower
clocks used by the pulse accumulator, the real-time interrupt (RTI), and
the computer operating properly (COP) watchdog subsystems, also
described in this section. Refer to Figure 9-1.
All main timer system activities are referenced to this free-running
counter. The counter begins incrementing from $0000 as the MCU
comes out of reset and continues to the maximum count, $FFFF. At the
maximum count, the counter rolls over to $0000, sets an overflow flag,
and continues to increment. As long as the MCU is running in a normal
operating mode, there is no way to reset, change, or interrupt the
counting. The capture/compare subsystem features three input capture
channels, four output compare channels, and one channel that can be
selected to perform either input capture or output compare. Each of the
three input capture functions has its own 16-bit input capture register
(time capture latch) and each of the output compare functions has its
own 16-bit compare register. All timer functions, including the timer
overflow and RTI, have their own interrupt controls and separate
interrupt vectors.
The pulse accumulator contains an 8-bit counter and edge select logic.
The pulse accumulator can operate in either event counting mode or
gated time accumulation mode. During event counting mode, the pulse
accumulators 8-bit counter increments when a specified edge is
detected on an input signal. During gated time accumulation mode, an
internal clock source increments the 8-bit counter while an input signal
has a predetermined logic level.
The real-time interrupt (RTI) is a programmable periodic interrupt circuit
that permits pacing the execution of software routines by selecting one
of four interrupt rates.
Technical Data
176
MOTOROLA
Timing System
Introduction
The COP watchdog clock input (E 215) is tapped off of the free-running
counter chain. The COP automatically times out unless it is serviced
within a specific time by a program reset sequence. If the COP is allowed
to time out, a reset is generated, which drives the RESET pin low to reset
the MCU and the external system. Refer to Table 9-1 for crystal-related
frequencies and periods.
OSCILLATOR AND
CLOCK GENERATOR
(DIVIDE BY FOUR)
AS
E CLOCK
INTERNAL BUS CLOCK (PH2)
PRESCALER
( 2, 4, 16, 32)
SPR[1:0]
PRESCALER
( 1, 3, 4, 13)
SCP[1:0]
SPI
PRESCALER
( 1, 2, 4,....128)
SCR[2:0]
39
SCP2*
16
E 26
PRESCALER
( 1, 2, 4, 8)
RTR[1:0]
E 213
PRESCALER
( 1, 4, 8, 16)
PR[1:0]
REAL-TIME INTERRUPT
E215
PRESCALER
(1, 4, 16, 64)
CR[1:0]
TOF
TCNT
FF1
FF2
FORCE
COP
RESET
IC/OC
* SCP2 present on MC68HC(7)11E20 only
CLEAR COP
TIMER
SYSTEM
RESET
Technical Data
Timing System
177
Timing System
Control Bits
PR1, PR0
4.0 MHz
8.0 MHz
12.0 MHz
Other Rates
1.0 MHz
2.0 MHz
3.0 MHz
(E)
1000 ns
500 ns
333 ns
(1/E)
1000 ns
65.536 ms
500 ns
32.768 ms
333 ns
21.845 ms
(E/1)
(E/216)
01
1 count
overflow
4.0 s
262.14 ms
2.0 s
131.07 ms
1.333 s
87.381 ms
(E/4)
(E/218)
10
1 count
overflow
8.0 s
524.29 ms
4.0 s
262.14 ms
2.667 s
174.76 ms
(E/8)
(E/219)
11
1 count
overflow
16.0 s
1.049 s
8.0 s
524.29 ms
5.333 s
349.52 ms
(E/16)
(E/220)
MOTOROLA
Timing System
Timer Structure
PRESCALER
DIVIDE BY
1, 4, 8, OR 16
MCU
E CLK
PR1
TCNT (HI)
TCNT (LO)
TOI
16-BIT FREE-RUNNING
COUNTER
PR0
TOF
TAPS FOR RTI,
COP WATCHDOG, AND
PULSE ACCUMULATOR
INTERRUPT REQUESTS
(FURTHER QUALIFIED BY
I BIT IN CCR)
TO PULSE
ACCUMULATOR
OC1I
16-BIT COMPARATOR =
TOC1 (HI)
OC1F
TOC1 (LO)
FOC1
OC2I
16-BIT COMPARATOR =
TOC2 (HI)
TOC2 (LO)
TOC3 (LO)
TOC4 (LO)
OC5
TI4/O5 (LO)
I4/O5F
CLK
TIC2 (HI)
CFORC
FORCE OUTPUT
COMPARE
CLK
IC1I
BIT 3
PA3/OC5/
IC4/OC1
BIT 2
PA2/IC1
BIT 1
PA1/IC2
BIT 0
PA0/IC3
IC1F
IC2I
IC2F
TIC2 (LO)
16-BIT LATCH
TIC3 (HI)
CLK
PA4/OC4/
OC1
FOC5
TIC1 (LO)
16-BIT LATCH
BIT 4
IC4
I4/O5
CLK
PA5/OC3/
OC1
FOC4
I4/O5I
16-BIT LATCH
BIT 5
OC4F
16-BIT COMPARATOR =
TIC1 (HI)
PA6/OC2/
OC1
FOC3
16-BIT COMPARATOR =
16-BIT LATCH
BIT 6
OC3F
OC4I
TI4/O5 (HI)
PA7/OC1/
PAI
FOC2
16-BIT COMPARATOR =
TOC4 (HI)
BIT 7
OC2F
OC3I
TOC3 (HI)
PIN
FUNCTIONS
IC3I
IC3F
TIC3 (LO)
TFLG 1
STATUS
FLAGS
TMSK 1
INTERRUPT
ENABLES
PORT A
PIN CONTROL
Technical Data
Timing System
179
Timing System
9.4 Input Capture
The input capture function records the time an external event occurs by
latching the value of the free-running counter when a selected edge is
detected at the associated timer input pin. Software can store latched
values and use them to compute the periodicity and duration of events.
For example, by storing the times of successive edges of an incoming
signal, software can determine the period and pulse width of a signal. To
measure period, two successive edges of the same polarity are
captured. To measure pulse width, two alternate polarity edges are
captured.
In most cases, input capture edges are asynchronous to the internal
timer counter, which is clocked relative to an internal clock (PH2). These
asynchronous capture requests are synchronized to PH2 so that the
latching occurs on the opposite half cycle of PH2 from when the timer
counter is being incremented. This synchronization process introduces
a delay from when the edge occurs to when the counter value is
detected. Because these delays offset each other when the time
between two edges is being measured, the delay can be ignored. When
an input capture is being used with an output compare, there is a similar
delay between the actual compare point and when the output pin
changes state.
The control and status bits that implement the input capture functions
are contained in:
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the
PACTL register. Note that this bit is cleared out of reset. To enable PA3
as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with
bit I4/O5 being cleared. If the DDRA3 bit is set (configuring PA3 as an
output), and IC4 is enabled, then writes to PA3 cause edges on the pin
Technical Data
180
MOTOROLA
Timing System
Input Capture
$1021
Bit 7
Bit 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
Read:
Write:
Reset:
EDGxA
Capture disabled
Configuration
Technical Data
Timing System
181
Timing System
9.4.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit
free-running counter value is transferred into the input capture register
pair as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2
clock so that the count value is stable whenever a capture occurs. The
timer input capture registers are not affected by reset. Input capture
values can be read from a pair of 8-bit read-only registers. A read of the
high-order byte of an input capture register pair inhibits a new capture
transfer for one bus cycle. If a double-byte read instruction, such as load
double accumulator D (LDD), is used to read the captured value,
coherency is assured. When a new input capture occurs immediately
after a high-order byte read, transfer is delayed for an additional cycle
but the value is not lost.
Address: $1010
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $1011
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Technical Data
182
MOTOROLA
Timing System
Input Capture
Address: $1012
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $1013
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Address: $1014
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $1015
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Technical Data
Timing System
183
Timing System
9.4.3 Timer Input Capture 4/Output Compare 5 Register
Use TI4/O5 as either an input capture register or an output compare
register, depending on the function chosen for the PA3 pin. To enable it
as an input capture pin, set the I4/O5 bit in the pulse accumulator control
register (PACTL) to logic level 1. To use it as an output compare register,
set the I4/O5 bit to a logic level 0. Refer to 9.8 Pulse Accumulator.
Address: $101E
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $101F
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
MOTOROLA
Timing System
Output Compare
Technical Data
Timing System
185
Timing System
high-order byte of an output compare register pair inhibits the output
compare function for one bus cycle. This inhibition prevents
inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output
compare registers TOC1TOC4 and TI4/O5. When TCNT value
matches the comparison value, specified pin actions occur.
Register name: Timer Output Compare 1 Register (High)
Address: $1016
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $1017
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Address: $1018
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $1019
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
MOTOROLA
Timing System
Output Compare
Address: $101A
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $101B
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Address: $101C
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Write:
Reset:
Address: $101D
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Technical Data
Timing System
187
Timing System
9.5.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5]
correspond to the five output compares. These bits are set for each
output compare that is to be forced. The action taken as a result of a
forced compare is the same as if there were a match between the OCx
register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their
programmed pin actions to occur at the next timer count transition after
the write to CFORC.
The CFORC bits should not be used on an output compare function that
is programmed to toggle its output on a successful compare because a
normal compare that occurs immediately before or after the force can
result in an undesirable operation.
Address:
$100B
Bit 7
FOC1
FOC2
FOC3
FOC4
FOC5
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
188
MOTOROLA
Timing System
Output Compare
$100C
Bit 7
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
Timing System
189
Timing System
9.5.4 Output Compare Data Register
Use this register with OC1 to specify the data that is to be stored on the
affected pin of port A after a successful OC1 compare. When a
successful OC1 compare occurs, a data bit in OC1D is stored in the
corresponding bit of port A for each bit that is set in OC1M.
Address:
$100D
Bit 7
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
190
MOTOROLA
Timing System
Output Compare
Read:
Address: $100E
Bit 7
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Read:
Address: $100F
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
= Unimplemented
Technical Data
Timing System
191
Timing System
9.5.6 Timer Control Register 1
The bits of this register specify the action taken as a result of a
successful OCx compare.
Address:
$1020
Bit 7
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
Read:
Write:
Reset:
OLx
Technical Data
192
MOTOROLA
Timing System
Output Compare
$1022
Bit 7
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
Read:
Write:
Reset:
NOTE:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in
TMSK1 enable the corresponding interrupt sources.
Technical Data
Timing System
193
Timing System
9.5.8 Timer Interrupt Flag 1 Register
Bits in this register indicate when timer system events have occurred.
Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer
subsystem to operate in either a polled or interrupt driven system. Each
bit of TFLG1 corresponds to a bit in TMSK1 in the same position.
Address:
$1023
Bit 7
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
Read:
Write:
Reset:
$1024
Bit 7
TOI
RTII
PAOVI
PAII
Bit 0
PR1
PR0
Read:
Write:
Reset:
= Unimplemented
MOTOROLA
Timing System
Output Compare
NOTE:
PR[1:0]
Prescaler
00
01
10
11
16
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in
TMSK2 enable the corresponding interrupt sources.
Technical Data
Timing System
195
Timing System
9.5.10 Timer Interrupt Flag Register 2
Bits in this register indicate when certain timer system events have
occurred. Coupled with the four high-order bits of TMSK2, the bits of
TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
Address:
$1025
Bit 7
TOF
RTIF
PAOVF
PAIF
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
196
MOTOROLA
Timing System
Real-Time Interrupt (RTI)
E = 3 MHz
E = 2 MHz
E = 1 MHz
E = X MHz
00
2.731 ms
4.096 ms
8.192 ms
(E/213)
01
5.461 ms
8.192 ms
16.384 ms
(E/214)
10
10.923 ms
16.384 ms
32.768 ms
(E/215)
11
21.845 ms
32.768 ms
65.536 ms
(E/216)
The clock source for the RTI function is a free-running clock that cannot
be stopped or interrupted except by reset. This clock causes the time
between successive RTI timeouts to be a constant that is independent
of the software latencies associated with flag clearing and service. For
this reason, an RTI period starts from the previous timeout, not from
when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set,
an interrupt request is generated. After reset, one entire RTI period
elapses before the RTIF is set for the first time. Refer to the 9.5.9 Timer
Interrupt Mask 2 Register, 9.6.2 Timer Interrupt Flag Register 2, and
9.6.3 Pulse Accumulator Control Register.
Technical Data
Timing System
197
Timing System
9.6.1 Timer Interrupt Mask Register 2
This register contains the real-time interrupt enable bits.
Address:
$1024
Bit 7
TOI
RTI
PAOVI
PAII
Bit 0
PR1
PR0
Read:
Write:
Reset:
= Unimplemented
NOTE:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in
TMSK2 enable the corresponding interrupt sources.
Technical Data
198
MOTOROLA
Timing System
Real-Time Interrupt (RTI)
$1025
Bit 7
TOF
RTIF
PAOVF
PAIF
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
Timing System
199
Timing System
9.6.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The
remaining bits control the pulse accumulator and IC4/OC5 functions.
Address:
$1026
Bit 7
Bit 0
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Read:
Write:
Reset:
Technical Data
200
MOTOROLA
Timing System
Computer Operating Properly (COP) Watchdog Function
Technical Data
Timing System
201
Timing System
PAOVI
PAOVF
1
INTERRUPT
REQUESTS
PAII
PAIF
PAII
PAOVI
PAOVF
PAIF
E 64 CLOCK
FROM MAIN TIMER
DISABLE
FLAG SETTING
PAEN
OVERFLOW
MCU PIN
2:1
MUX
INPUT BUFFER
AND
EDGE DETECTOR
PA7/
PAI/
OC1
FROM
DDRA7
DATA
BUS
OUTPUT
BUFFER
PEDGE
PAMOD
PAEN
PAEN
FROM
MAIN TIMER
OC1
CLOCK
PACTL CONTROL
INTERNAL
DATA BUS
E Clock
Cycle Time
E 64
PACNT
Overflow
4.0 MHz
1 MHz
1000 ns
64 s
16.384 ms
8.0 MHz
2 MHz
500 ns
32 s
8.192 ms
12.0 MHz
3 MHz
333 ns
21.33 s
5.461 ms
Pulse accumulator control bits are also located within two timer
registers, TMSK2 and TFLG2, as described in the following paragraphs.
Technical Data
202
MOTOROLA
Timing System
Pulse Accumulator
$1026
Bit 7
Bit 0
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Read:
Write:
Reset:
PEDGE
Action on Clock
Technical Data
Timing System
203
Timing System
DDRA3 Data Direction for Port A Bit 3
Refer to Section 6. Parallel Input/Output (I/O) Ports.
I4/O5 Input Capture 4/Output Compare 5 Bit
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
RTR[1:0] RTI Interrupt Rate Select Bits
Refer to 9.6 Real-Time Interrupt (RTI).
$1027
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Technical Data
204
MOTOROLA
Timing System
Pulse Accumulator
$1024
Bit 7
TOI
RTII
PAOVI
PAII
Bit 0
PR1
PR0
Read:
Write:
Reset:
= Unimplemented
Address:
$1025
Bit 7
TOF
RTIF
PAOVF
PAIF
Bit 0
Read:
Write:
Reset:
= Unimplemented
Technical Data
Timing System
205
Timing System
interrupt request is generated each time PAOVF is set. Before leaving
the interrupt service routine, software must clear PAOVF by writing to
the TFLG2 register.
PAII and PAIF Pulse Accumulator Input Edge Interrupt Enable Bit
and Flag
The PAIF status bit is automatically set each time a selected edge is
detected at the PA7/PAI/OC1 pin. To clear this status bit, write to the
TFLG2 register with a 1 in the corresponding data bit position (bit 4).
The PAII control bit allows configuring the pulse accumulator input
edge detect for polled or interrupt-driven operation but does not affect
setting or clearing the PAIF bit. When PAII is 0, pulse accumulator
input interrupts are inhibited, and the system operates in a polled
mode. In this mode, the PAIF bit must be polled by user software to
determine when an edge has occurred. When the PAII control bit is
set, a hardware interrupt request is generated each time PAIF is set.
Before leaving the interrupt service routine, software must clear PAIF
by writing to the TFLG2 register.
Technical Data
206
MOTOROLA
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
10.5
10.6
10.7
10.8
10.9
10.2 Introduction
The analog-to-digital (A/D) system, a successive approximation
converter, uses an all-capacitive charge redistribution technique to
convert analog signals to digital values.
Technical Data
Analog-to-Digital (A/D) Converter
207
10.3.1 Multiplexer
The multiplexer selects one of 16 inputs for conversion. Input selection
is controlled by the value of bits CD:CA in the ADCTL register. The eight
port E pins are fixed-direction analog inputs to the multiplexer, and
additional internal analog signal lines are routed to it.
Port E pins also can be used as digital inputs. Digital reads of port E pins
are not recommended during the sample portion of an A/D conversion
cycle, when the gate signal to the N-channel input gate is on. Because
no P-channel devices are directly connected to either input pins or
reference voltage pins, voltages above VDD do not cause a latchup
problem, although current should be limited according to maximum
ratings. Refer to Figure 10-2, which is a functional diagram of an input
pin.
Technical Data
208
MOTOROLA
PE0
AN0
VRH
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
PE1
AN1
VRL
PE2
AN2
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
PE3
AN3
RESULT
ANALOG
MUX
PE4
AN4
PE5
AN5
INTERNAL
DATA BUS
CA
CC
CB
SCAN
PE7
AN7
MULT
CD
CCF
PE6
AN6
ANALOG
INPUT
PIN
< 2 pF
INPUT
PROTECTION
DEVICE
+ ~20 V
~0.7 V
4 k
+ ~12V
~0.7V
DUMMY N-CHANNEL
OUTPUT DEVICE
400 nA
JUNCTION
LEAKAGE
*
~ 20 pF
DAC
CAPACITANCE
VRL
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
Technical Data
Analog-to-Digital (A/D) Converter
209
Technical Data
210
MOTOROLA
MSB
4
CYCLES
CONVERT FIRST
CHANNEL, UPDATE
ADR1
32
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
2
CYC
END
CONVERT SECOND
CHANNEL, UPDATE
ADR2
64
CONVERT THIRD
CHANNEL, UPDATE
ADR3
96
CONVERT FOURTH
CHANNEL, UPDATE
ADR4
SET CC FLAG
WRITE TO ADCTL
12 E CYCLES
E CLOCK
128 E CYCLES
Technical Data
Analog-to-Digital (A/D) Converter
211
$1039
Bit 7
ADPU
CSEL
IRQE(1)
DLY(1)
CME
Read:
Bit 0
CR1(1)
CR0(1)
Write:
Reset:
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes
= Unimplemented
Technical Data
212
MOTOROLA
Technical Data
Analog-to-Digital (A/D) Converter
213
Channel
Signal
Result in ADRx
if MULT = 1
AN0
ADR1
AN1
ADR2
AN2
ADR3
AN3
ADR4
AN4
ADR1
AN5
ADR2
AN6
ADR3
AN7
ADR4
9 12
Reserved
13
VRH(1)
ADR1
14
VRL(1)
ADR2
15
(VRH)/2(1)
ADR3
16
Reserved(1)
ADR4
MOTOROLA
Technical Data
Analog-to-Digital (A/D) Converter
215
$1030
Bit 7
Read:
Bit 0
SCAN
MULT
CD
CC
CB
CA
CCF
Write:
Reset:
= Unimplemented
Technical Data
216
MOTOROLA
NOTE:
Channel Signal
Result in ADRx
if MULT = 1
0000
AN0
ADR1
0001
AN1
ADR2
0010
AN2
ADR3
0011
AN3
ADR4
0100
AN4
ADR1
0101
AN5
ADR2
CD:CC:CB:CA
0110
AN6
ADR3
0111
AN7
ADR4
10XX
Reserved
1100
VRH(1)
ADR1
1101
VRL(1)
ADR2
1110
(VRH)/2(1)
ADR3
1111
Reserved(1)
ADR4
Technical Data
Analog-to-Digital (A/D) Converter
217
Read:
Address: $1031
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Read:
Address: $1032
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Read:
Address: $1033
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Read:
Address: $1034
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Technical Data
218
MOTOROLA
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.3
11.4
11.5
11.6
11.7
11.8
11.9
Technical Data
Electrical Characteristics
219
Electrical Characteristics
11.2 Introduction
This section contains electrical specifications for the M68HC11 E-series
devices.
NOTE:
Symbol
Value
Unit
Supply voltage
VDD
0.3 to +7.0
Input voltage
VIn
0.3 to +7.0
ID
25
mA
TSTG
55 to +150
Storage temperature
NOTE:
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the
range VSS (VIn or VOut) VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD).
Technical Data
220
MOTOROLA
Electrical Characteristics
Functional Operating Range
Symbol
Value
Unit
TA
TL to TH
0 to +70
40 to +85
40 to +105
40 to +125
0 to +70
40 to +85
40 to +105
40 to +125
20 to +70
VDD
5.0 10%
Symbol
Value
Unit
TJ
TA + (PD JA)
Ambient temperature
TA
User-determined
JA
PD
PINT + PI/O
K / TJ + 273C
PINT
IDD VDD
PI/O
User-determined
A constant(3)
50
50
50
85
85
C/W
PD (TA + 273C)
+ JA PD2
W/C
Technical Data
Electrical Characteristics
221
Electrical Characteristics
11.6 DC Electrical Characteristics
Characteristics(1)
Symbol
Min
Max
VDD 0.1
0.1
Unit
Output voltage(2)
ILoad = 10.0 A
All outputs except XTAL
All outputs except XTAL, RESET, and MODA
VOL, VOH
VOH
VDD 0.8
VOL
0.4
VIH
0.7 VDD
0.8 VDD
VDD + 0.3
VDD + 0.3
VIL
VSS 0.3
0.2 VDD
IOZ
10
IIn
1
10
VSB
4.0
VDD
ISB
10
Input capacitance
PA[2:0], PE[7:0], IRQ, XIRQ, EXTAL
PA7, PA3, PC[7:0], PD[5:0], AS/STRA, MODA/LIR, RESET
C In
8
12
pF
CL
90
100
pF
Technical Data
222
MOTOROLA
Electrical Characteristics
Supply Currents and Power Dissipation
Symbol
2 MHz
3 MHz
2 MHz
3 MHz
IDD
2 MHz
3 MHz
2 MHz
3 MHz
WIDD
40C to +85C
> +85C to +105C
> +105C to +125C
SIDD
2 MHz
3 MHz
2 MHz
3 MHz
PD
Min
Max
15
27
27
35
6
15
10
20
25
50
100
85
150
150
195
Unit
mA
mA
mW
Technical Data
Electrical Characteristics
223
Electrical Characteristics
11.8 MC68L11E9 DC Electrical Characteristics
Characteristics(1)
Symbol
Min
Max
Unit
Output voltage(2)
ILoad = 10.0 A
All outputs except XTAL
All outputs except XTAL, RESET, and MODA
V OL, VOH
VDD 0.1
0.1
VOH
VDD 0.8
VOL
0.4
VIH
0.7 VDD
0.8 VDD
VDD + 0.3
VDD + 0.3
VIL
VSS 0.3
0.2 VDD
IOZ
10
IIn
1
10
VSB
2.0
VDD
ISB
10
8
12
pF
CL
90
100
pF
Input capacitance
PA[2:0], PE[7:0], IRQ, XIRQ, EXTAL
PA7, PA3, PC[7:0], PD[5:0], AS/STRA, MODA/LIR, RESET
Output load capacitance
All outputs except PD[4:1]
PD[4:1]
1. V DD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. V OH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specification not
applicable to ports C and D in wired-OR mode.
3. Refer to 11.14 Analog-to-Digital Converter Characteristics and 11.15 MC68L11E9 Analog-to-Digital Converter
Characteristics for leakage current for port E.
Technical Data
224
MOTOROLA
Electrical Characteristics
MC68L11E9 Supply Currents and Power Dissipation
Symbol
VDD
VDD
VDD
VDD
= 5.5 V
= 3.0 V
= 5.5 V
= 5.5 V
VDD
VDD
VDD
VDD
= 5.5 V
= 3.0 V
= 5.5 V
= 3.0 V
VDD = 5.5 V
VDD = 3.0 V
2 MHz
3 MHz
2 MHz
3 MHz
IDD
WIDD
SIDD
PD
1 MHz
2 MHz
8
4
14
7
15
8
27
14
3
1.5
5
2.5
6
3
10
5
50
25
50
25
44
12
77
21
85
24
150
42
Unit
mA
mA
mW
1. V DD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. EXTAL is driven with a square wave, and
tcyc = 500 ns for 2 MHz rating
tcyc = 333 ns for 3 MHz rating
VIL 0.2 V
VIH VDD 0.2 V
no dc loads
Technical Data
Electrical Characteristics
225
Electrical Characteristics
CLOCKS,
STROBES
~ VDD
0.4 VOLTS
~ V SS
0.4 VOLTS
NOM
NOM
70% of V DD
INPUTS
20% of V DD
NOMINAL TIMING
~ VDD
OUTPUTS
0.4 Volts
~ VSS
DC TESTING
CLOCKS,
STROBES
~ VDD
70% of VDD
20% of VDD
~ VSS
20% of V DD
SPEC
SPEC
70% of VDD
INPUTS
20% of V DD
(NOTE 2)
VDD 0.8 VOLTS
0.4 VOLTS
SPEC TIMING
~ VDD
OUTPUTS
~ VSS
70% of V DD
20% of V DD
AC TESTING
Notes:
1. Full test loads are applied during all dc electrical tests and ac timing measurements.
2. During ac timing measurements, inputs are driven to 0.4 volts and VDD 0.8 volts while timing
measurements are taken at 20% and 70% of VDD points.
Technical Data
226
MOTOROLA
Electrical Characteristics
Control Timing
Characteristic(1) (2)
2.0 MHz
3.0 MHz
Symbol
Unit
Min Max Min Max Min Max
fo
dc
1.0
dc
2.0
dc
3.0
MHz
tcyc
1000
500
333
ns
fXTAL
4.0
8.0
12.0
MHz
4 fo
dc
4.0
dc
8.0
dc
12.0
MHz
tPCSU
300
175
133
ns
8
1
8
1
8
1
Frequency of operation
E-clock period
Crystal frequency
PWRSTL
tcyc
tMPS
tcyc
tMPH
10
10
10
ns
PWIRQ
1020
520
353
ns
tWRS
tcyc
PWTIM
1020
520
353
ns
1. V DD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Section 5.
Resets and Interrupts for further detail.
Technical Data
Electrical Characteristics
227
Electrical Characteristics
11.11 MC68L11E9 Control Timing
1.0 MHz
Characteristic(1) (2)
2.0 MHz
Symbol
Unit
Min
Max
Min
Max
fo
dc
1.0
dc
2.0
MHz
tcyc
1000
500
ns
fXTAL
4.0
8.0
MHz
4 fo
dc
4.0
dc
8.0
MHz
tPCSU
325
200
ns
PW RSTL
8
1
8
1
tcyc
tMPS
tcyc
tMPH
10
10
ns
PW IRQ
1020
520
ns
tWRS
tcyc
PWTIM
1020
520
ns
Frequency of operation
E-clock period
Crystal frequency
1. V DD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to T H, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Section 5.
Resets and Interrupts for further detail.
PA[2:0]
(1)
PA[2:0]
(2)
(1) (3)
PA7
PWTIM
PA7(2) (3)
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
MOTOROLA
MOTOROLA
VDD
EXTAL
Electrical Characteristics
4064 tCYC
E
tPCSU
PWRSTL
RESET
tMPS
tMPH
MODA, MODB
ADDRESS
FFFE
FFFE
FFFE
FFFE
FFFF
NEW
PC
FFFE
FFFE
FFFE
FFFE
FFFE
FFFF
NEW
PC
Technical Data
229
Electrical Characteristics
Technical Data
230
INTERNAL
CLOCKS
IRQ1
PWIRQ
Electrical Characteristics
IRQ
or XIRQ
tSTOPDELAY3
E
ADDRESS4
STOP
ADDR
STOP
ADDR + 1
STOP
ADDR + 1
OPCODE
Resume program with instruction which follows the STOP instruction.
ADDRESS5
STOP
ADDR
STOP
ADDR + 1
STOP
ADDR + 1
STOP
ADDR + 2
SPSP7
SP 8
Notes:
1. Edge Sensitive IRQ pin (IRQE bit = 1)
2. Level sensitive IRQ pin (IRQE bit = 0)
3. tSTOPDELAY = 4064 tCYC if DLY bit = 1 or 4 tCYC if DLY = 0.
MOTOROLA
SP 8
FFF2
(FFF4)
FFF3
(FFF5)
NEW
PC
MOTOROLA
E
tPCSU
Electrical Characteristics
IRQ, XIRQ,
OR INTERNAL
INTERRUPTS
tWRS
ADDRESS
WAIT
ADDR
WAIT
ADDR + 1
SP
PCL
SP 1
SP 2SP 8
SP 8
SP 8SP 8
SP 8
SP 8
SP 8
VECTOR
ADDR
VECTOR
ADDR + 1
NEW
PC
STACK REGISTERS
R/W
Technical Data
231
Electrical Characteristics
Technical Data
232
E
tPCSU
IRQ 1
PWIRQ
2 , XIRQ,
Electrical Characteristics
IRQ
OR INTERNAL
INTERRUPT
ADDRESS
DATA
NEXT
OPCODE
NEXT
OP + 1
OP
CODE
SP
PCL
SP 1
SP 2
SP 3
SP 4
SP 5
SP 6
SP 7
SP 8
SP 8
VECTOR
ADDR
VECTOR
ADDR + 1
PCH
IYL
IYH
IXL
IXH
CCR
VECT
MSB
VECT
LSB
R/W
Notes:
1. Edge sensitive IRQ pin (IRQE bit = 1)
2. Level sensitive IRQ pin (IRQE bit = 0)
MOTOROLA
NEW
PC
OP
CODE
Electrical Characteristics
Peripheral Port Timing
1.0 MHz
2.0 MHz
3.0 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
fo
dc
1.0
dc
2.0
dc
3.0
MHz
tcyc
1000
500
333
ns
tPDSU
100
100
100
ns
tPDH
50
50
50
ns
tPWD
200
350
200
225
200
183
Frequency of operation
E-clock frequency
E-clock period
ns
tIS
60
60
60
ns
tIH
100
100
100
ns
tDEB
350
225
183
ns
tAES
ns
tPCD
100
100
100
ns
tPCH
10
10
10
ns
tPCZ
150
150
150
ns
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, T A = TL to TH, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers,
respectively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more
cycle.
Technical Data
Electrical Characteristics
233
Electrical Characteristics
11.13 MC68L11E9 Peripheral Port Timing
1.0 MHz
Characteristic(1) (2)
2.0 MHz
Symbol
Unit
Min
Max
Min
Max
fo
dc
1.0
dc
2.0
MHz
tcyc
1000
500
ns
tPDSU
100
100
ns
tPDH
50
50
ns
tPWD
250
400
250
275
Frequency of operation
E-clock frequency
E-clock period
ns
tIS
60
60
ns
tIH
100
100
ns
tDEB
400
275
ns
tAES
ns
tPCD
100
100
ns
tPCH
10
10
ns
tPCZ
150
150
ns
1. V DD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to T H, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers,
respectively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.
Technical Data
234
MOTOROLA
Electrical Characteristics
MC68L11E9 Peripheral Port Timing
MCU
MCUREAD
READOF
OFPORT
PORT
E
E
tPDSU
PDSU
ttPDH
PDH
PORTS
PORTS
D
A,A,C*C*,, D
ttPDSU
PDSU
ttPDH
PDH
PORT E
E
PORT
* FOR
NON-LATCHED
OPERATION
PORTCC
* For
non-latched
operation OF
of port
E9 PORT RD TIM
MCU
MCU WRITE TO PORT
PORT
EE
ttPWD
PWD
PORTS
PORTS
C, D
D
B,B,C,
PREVIOUS PORT
PORT DATA
DATA
DATAVALID
VALID
NEW DATA
tPWD
PWD
PORT A
A
PORT
PREVIOUS
PREVIOUSPORT
PORTDATA
DATA
NEW DATA
DATAVALID
VALID
NEW
STRA (IN)
STRA (IN)
ttIS
IS
tIS
PORT
C (IN)
PORT
C (IN)
Technical Data
Electrical Characteristics
235
Electrical Characteristics
MCU WRITE
WRITETO
TOPORT
PORT BB
MCU
EE
ttPWD
PWD
PORT BB
PORT
NEWDATA
DATA VALID
VALID
NEW
PREVIOUS
DATA
PREVIOUS PORT DATA
ttDEB
DEB
STRB (OUT)
(OUT)
STRB
ttDEB
DEB
READY
"READY"
tDEB
DEB
STRB (OUT)
STRB (0UT)
tAES
AES
STRA
(IN)
STRA (IN)
ttIS
IS
tIH
IH
PORT
C(IN)
(IN)
PORT C
NOTES:
Notes:
1. After reading PIOC with STAF set
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
EE
ttPWD
PWD
PORTCC(OUT)
(OUT)
PORT
PREVIOUSPORT
PORT DATA
PREVIOUS
DATA
NEW DATA
NEW
DATA VALID
VALID
tDEB
DEB
READY
"READY"
STRB (IN)
ttDEB
DEB
STRB (OUT)
ttAES
AES
STRA
(IN)
STRA (IN)
NOTES:
Notes:
After reading
PIOC
with STAF
1.1.After
reading
PIOC
withsetSTAF set
Figure shows
risingrising
edge STRA
(EGA
= 1) and
high =
true
1). STRB (INVB = 1).
2.2.Figure
shows
edge
STRA
(EGA
1)STRB
and(INVB
high =true
PORT C OUTPUT HNDSHK TIM
Technical Data
236
MOTOROLA
Electrical Characteristics
MC68L11E9 Peripheral Port Timing
1(1)
READ
READPORTCL
PORTCL
E
E
ttPWD
PWD
PORTC
C (OUT)
(OUT)
PORT
(DDR
DDR ==1)1
tDEB
DEB
ttDEB
DEB
READY
"READY"
STRB
STRB(OUT)
(OUT)
ttAES
AES
STRA (IN)
(IN)
STRA
ttPCD
PCD
PORTC
C (OUT)
(OUT)
PORT
(DDR
DDR ==0)0
OLDDATA
DATA
OLD
ttPCH
PCH
NEW
DATA
VALID
NEW
DATA
VALID
ttPCZ
PCZ
a)STRA
STRAACTIVE
ACTIVEBEFORE
BEFORE
PORTCL
WRITE
a)
PORTCL
WRITE
STRA (IN)
(IN)
STRA
tPCH
PCH
ttPCD
PCD
PORTC
C (OUT)
(OUT)
PORT
(DDR
DDR ==0)0
NEW
NEWDATA
DATAVALID
VALID
b) STRA
STRA ACTIVE
WRITE
b)
ACTIVEAFTER
AFTERPORTCL
PORTCL
WRITE
ttPCZ
PCZ
NOTES:
Notes:
1. After reading PIOC with STAF set
1.
Aftershows
reading
with
STAF
sethigh true STRB (INVB = 1).
2. Figure
rising PIOC
edge STRA
(EGA
= 1) and
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
Technical Data
Electrical Characteristics
237
Electrical Characteristics
11.14 Analog-to-Digital Converter Characteristics
Characteristic(1)
Parameter(2)
Resolution
Bits
Min
Absolute
1/2
LSB
1/2
LSB
1/2
LSB
1/2
1/2
LSB
1/2
1/2
LSB
LSB
VRL
VRH
VRH
VRH
VRL
VRL
VSS 0.1
32
tcyc +32
tcyc +32
tcyc
s
V
V
VR
Conversion
time
Monotonicity
Guaranteed
00
Hex
FF
FF
Hex
Sample
acquisition
time
12
12
12
tcyc
s
Sample/hold
capacitance
20 typical
pF
400
1.0
400
1.0
nA
A
Zero input
reading
Full scale
reading
Input leakage
VRL(2)
1. V DD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, 750 kHz E 3.0 MHz, unless otherwise noted
2. Source impedances greater than 10 k affect accuracy adversely because of input leakage.
3. Performance verified down to 2.5 V VR, but accuracy is tested and guaranteed at VR = 5 V 10%.
Technical Data
238
MOTOROLA
Electrical Characteristics
MC68L11E9 Analog-to-Digital Converter Characteristics
Parameter(2)
Min
Absolute
Max
Unit
Resolution
Bits
Non-linearity
LSB
Zero error
LSB
LSB
Total unadjusted
error
1/2
LSB
1/2
LSB
LSB
Conversion range
VRL
VRH
VRH
VRL
VDD + 0.1
VRL
VSS 0.1
VRH
VR
3.0
Conversion time
32
tcyc + 32
tcyc
s
Monotonicity
Guaranteed
00
Hex
FF
Hex
Sample acquisition
time
12
12
tcyc
s
Sample/hold
capacitance
20 typical
pF
Input leakage
400
1.0
nA
A
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, 750 kHz E 2.0 MHz, unless otherwise noted
2. Source impedances greater than 10 k affect accuracy adversely because of input leakage.
Technical Data
Electrical Characteristics
239
Electrical Characteristics
11.16 Expansion Bus Timing Characteristics
1.0 MHz
Characteristic(1)
Num
2.0 MHz
3.0 MHz
Symbol
Frequency of operation
(E-clock frequency)
Unit
Min
Max
Min
Max
Min
Max
fo
dc
1.0
dc
2.0
dc
3.0
MHz
tcyc
1000
500
333
ns
Cycle time
PWEL
477
227
146
ns
PWEH
472
222
141
ns
4a
tr
20
20
20
ns
4b
tf
20
20
15
ns
tAH
95.5
33
26
ns
12
tAV
281.5
94
54
ns
17
tDSR
30
30
30
ns
18
tDHR
145.5
83
51
ns
19
tDDW
190.5
128
71
ns
21
tDHW
95.5
33
26
ns
22
tAVM
271.5
84
54
ns
tASL
151
26
13
ns
tAHL
95.5
33
31
ns
24
25
Continued
Technical Data
240
MOTOROLA
Electrical Characteristics
Expansion Bus Timing Characteristics
Characteristic(1)
Num
26
27
1.0 MHz
2.0 MHz
3.0 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
tASD
115.5
53
31
ns
PWASH
221
96
63
ns
28
tASED
115.5
53
31
ns
29
tACCA
744.5
307
196
ns
35
tACCE
442
192
111
ns
36
tMAD
145.5
83
ns
51
1. V DD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. Formula only for dc to 2 MHz
3. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tcyc in the above formulas, where applicable:
(a) (1dc) 1/4 tcyc
(b) dc 1/4 tcyc
Where:
dc is the decimal value of duty cycle percentage (high time)
Technical Data
Electrical Characteristics
241
Electrical Characteristics
11.17 MC68L11E9 Expansion Bus Timing Characteristics
Characteristic(1)
Num
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
fo
dc
1.0
dc
2.0
MHz
tcyc
1000
500
ns
Cycle time
PWEL
475
225
ns
PW EH
470
220
ns
4a
tr
25
25
ns
4b
tf
25
25
ns
tAH
95
33
ns
12
tAV
275
88
ns
17
tDSR
30
30
ns
18
tDHR
150
88
ns
19
tDDW
195
133
ns
21
tDHW
95
33
ns
22
tAVM
268
78
ns
24
tASL
150
25
ns
25
tAHL
95
33
ns
26
tASD
120
58
ns
27
PWASH
220
95
ns
28
tASED
120
58
ns
29
tACCA
735
298
ns
35
tACCE
440
190
ns
36
tMAD
150
88
ns
1. V DD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to T H, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tcyc in the above formulas, where applicable:
(a) (1dc) 1/4 tcyc
(b) dc 1/4 tcyc
Where:
dc is the decimal value of duty cycle percentage (high time).
Technical Data
242
MOTOROLA
Electrical Characteristics
MC68L11E9 Expansion Bus Timing Characteristics
11
2
33
4B
E
4A
12
12
99
R/W,
ADDRESS
R/W,ADDRESS
(NON-MUX)
NON-MULTIPLEXED
22
22
17
17
35
35
36
18
18
29
ADDRESS
ADDRESS
READ
READ
DATA
DATA
ADDRESS/DATA
ADDRESS/DATA
MULTIPLEXED
(MULTIPLEXED)
19
19
WRITE
WRITE
21
21
DATA
DATA
ADDRESS
25
4A
4A
24
24
4B
4B
AS
AS
26
26
27
27
28
28
NOTE:
Measurement points
shown
are 20%
70%
of V70% of V DD. DD.
Note:
Measurement
points
shown
areand
20%
and
Technical Data
Electrical Characteristics
243
Electrical Characteristics
11.18 Serial Peripheral Interface Timing Characteristics
Characteristic(1)
Num
Symbol
E9
E20
Unit
Min
Max
Min
Max
fo
dc
3.0
dc
3.0
MHz
tcyc
333
333
ns
Operating frequency
Master
Slave
fop(m)
fop(s)
fo/32
dc
fo/2
fo
fo/128
dc
fo/2
fo
MHz
Cycle time
Master
Slave
tcyc(m)
tcyc(s)
2
1
32
2
1
128
tcyc
tlead(s)
tcyc
tlag(s)
tcyc
tcyc 25
tw(SCKH)m
tw(SCKH)s 1/2 tcyc 25
16 tcyc
tcyc 25
1/2 tcyc 25
64 tcyc
ns
tw(SCKL)m
tw(SCKL)s
tcyc 25
1/2 tcyc 25
16 tcyc
tcyc 25
1/2 tcyc 25
64 tcyc
ns
tsu(m)
tsu(s)
30
30
30
30
ns
th(m)
th(s)
30
30
30
30
ns
ta
0
0
40
40
0
0
40
40
ns
tdis
50
50
ns
10
tv
50
50
ns
11
tho
ns
Frequency of operation
E clock
E-clock period
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% V DD and 70% VDD, unless
otherwise noted
2. Time to data active from high-impedance state
3. Assumes 200 pF load on SCK, MOSI, and MISO pins
Technical Data
244
MOTOROLA
Electrical Characteristics
MC68L11E9 Serial Peirpheral Interface Characteristics
Num
Symbol
E9
E20
Unit
Min
Max
Min
Max
fo
dc
2.0
dc
2.0
MHz
tcyc
500
500
ns
Operating frequency
Master
Slave
fop(m)
fop(s)
fo/32
dc
fo/2
fo
fo/128
dc
fo/2
fo
MHz
Cycle time
Master
Slave
tcyc(m)
tcyc(s)
2
1
32
2
1
128
tcyc
tlead(s)
tcyc
tlag(s)
tcyc
tcyc 30
tw(SCKH)m
tw(SCKH)s 1/2 tcyc 30
16 tcyc
tcyc 30
1/2 tcyc 30
64 tcyc
ns
tw(SCKL)m
tw(SCKL)s
tcyc 30
1/2 tcyc 30
16 tcyc
tcyc 30
1/2 tcyc 30
64 tcyc
ns
tsu(m)
tsu(s)
40
40
40
40
ns
th(m)
th(s)
40
40
40
40
ns
ta
0
0
50
50
0
0
50
50
ns
tdis
60
60
ns
10
tv
60
60
ns
11
tho
ns
Frequency of operation
E clock
E-clock period
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% VDD and 70% V DD, unless
otherwise noted
2. Time to data active from high-impedance state
3. Assumes 100 pF load on SCK, MOSI, and MISO pins
Technical Data
Electrical Characteristics
245
Electrical Characteristics
SS
INPUT
1
SCK
CPOL = 0
INPUT
SCK
CPOL = 1
OUTPUT
5
SEE NOTE
4
5
SEE NOTE
4
6
MISO
INPUT
7
BIT 6 . . . 1
MSB IN
LSB IN
11
MOSI
OUTPUT
11 (REF)
10
BIT 6 . . . 1
Note: This first clock edge is generated internally but is not seen at the SCK pin.
SS
INPUT
SCK
CPOL = 0
INPUT
SCK
CPOL = 1
OUTPUT
5
SEE NOTE
4
5
SEE NOTE
4
6
MISO
INPUT
BIT 6 . . . 1
MSB IN
11
10 (REF)
MOSI
OUTPUT
LSB IN
11 (REF)
10
BIT 6 . . . 1
Note: This first clock edge is generated internally but is not seen at the SCK pin.
Technical Data
246
MOTOROLA
Electrical Characteristics
MC68L11E9 Serial Peirpheral Interface Characteristics
SS
INPUT
1
SCK
CPOL = 0
INPUT
3
5
4
2
SCK
CPOL = 1
INPUT
8
MISO
OUTPUT
SLAVE
BIT 6 . . . 1
MSB OUT
10
6
MOSI
INPUT
11
7
BIT 6 . . . 1
MSB IN
SEE
NOTE
11
LSB IN
SS
INPUT
1
SCK
CPOL = 0
INPUT
5
4
2
SCK
CPOL = 1
INPUT
8
MISO
OUTPUT
10
SEE
NOTE
SLAVE
9
BIT 6 . . . 1
MSB OUT
10
6
MOSI
INPUT
7
MSB IN
BIT 6 . . . 1
LSB IN
Technical Data
Electrical Characteristics
247
Electrical Characteristics
11.20 EEPROM Characteristics
Temperature Range
Characteristic(1)
Unit
40 to 85C
40 to 105C
40 to 125C
Programming time(2)
< 1.0 MHz, RCO enabled
1.0 to 2.0 MHz, RCO disabled
2.0 MHz (or anytime RCO enabled)
10
20
10
Erase time(2)
Byte, row, and bulk
10
10
10
ms
10,000
10,000
10,000
Cycles
10
10
10
Years
Write/erase endurance
Data retention
15
20
Must use RCO Must use RCO
15
20
ms
Unit
Programming time(2)
3 V, E 2.0 MHz, RCO enabled
5 V, E 2.0 MHz, RCO enabled
25
10
ms
ms
25
10
ms
ms
10,000
Cycles
10
Years
Characteristic(1)
Write/erase endurance
Data retention
Technical Data
248
MOTOROLA
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.3
12.4
12.5
12.6
12.7
12.8
12.2 Introduction
The M68HC11E series microcontrollers are available in:
Technical Data
Mechanical Data
249
Mechanical Data
The diagrams included in this section show the latest package
specifications available at the time of this publication. To make sure that
you have the latest information, contact one of the following:
Follow the World Wide Web on-line instructions to retrieve the current
mechanical specifications.
Technical Data
250
MOTOROLA
Mechanical Data
52-Pin Plastic-Leaded Chip Carrier (Case 778)
0.007 (0.18)
B
Y BRK
T LM
0.007 (0.18)
T LM
D
Z
M
W
D
52
0.007 (0.18)
T LM
0.007 (0.18)
T LM
E
C
0.004 (0.100)
T SEATING
J
VIEW S
PLANE
G1
S
T LM
0.007 (0.18)
T LM
K1
0.007 (0.18)
T LM
VIEW S
T LM
VIEW DD
0.010 (0.25)
G1
0.010 (0.25)
NOTES:
1. DATUMS L, M, AND N DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.750
0.756
0.750
0.756
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2_
10 _
0.710
0.730
0.040
MILLIMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
19.05
19.20
19.05
19.20
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2_
10 _
18.04
18.54
1.02
Technical Data
Mechanical Data
251
Mechanical Data
12.4 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B)
-A0.51 (0.020)
0.51 (0.020)
F
T A
T A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION R AND N DO NOT INCLUDE
GLASS PROTRUSION. GLASS PROTRUSION
TO BE 0.25 (0.010) MAXIMUM.
4. ALL DIMENSIONS AND TOLERANCES
INCLUDE LEAD TRIM OFFSET AND LEAD
FINISH.
DIM
A
B
C
D
F
G
H
J
K
N
R
S
-B-
INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.200
0.017
0.021
0.026
0.032
0.050 BSC
0.090
0.130
0.006
0.010
0.035
0.045
0.735
0.756
0.735
0.756
0.690
0.730
MILLIMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
5.08
0.44
0.53
0.67
0.81
1.27 BSC
2.29
3.30
0.16
0.25
0.89
1.14
18.67
19.20
18.67
19.20
17.53
18.54
K
H
0.15 (0.006)
-T-
J
D
S
SEATING
PLANE
52 PL
0.18 (0.007)
T A
Technical Data
252
MOTOROLA
Mechanical Data
64-Pin Quad Flat Pack (Case 840C)
A, B, D
33
48
32
D
C AB
P
DETAIL A
0.20 (0.008)
0.05 (0.002) D
0.20 (0.008)
DETAIL A
H AB
49
17
64
0.20 (0.008)
D
H AB
0.05 (0.002) AB
S
0.20 (0.008)
C AB
C E
DATUM PLANE
0.10 (0.004)
C SEATING PLANE
G
DETAIL C
U
M
Q
SEATING PLANE
K
X
M
DETAIL C
C AB
SECTION BB
A
0.20 (0.008)
BASE
METAL
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS AB AND D TO BE DETERMINED AT
DATUM PLANE H.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE C.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE H.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED 0.53
(0.021). DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT.
8. DIMENSION K IS TO BE MEASURED FROM THE
THEORETICAL INTERSECTION OF LEAD FOOT
AND LEG CENTERLINES.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
X
MILLIMETERS
MIN
MAX
13.90
14.10
13.90
14.10
2.07
2.46
0.30
0.45
2.00
2.40
0.30
0.80 BSC
0.067
0.250
0.130
0.230
0.50
0.66
12.00 REF
5_
10_
0.130
0.170
0.40 BSC
2_
8_
0.13
0.30
16.20
16.60
0.20 REF
0_
16.20
16.60
1.10
1.30
INCHES
MIN
MAX
0.547
0.555
0.547
0.555
0.081
0.097
0.012
0.018
0.079
0.094
0.012
0.031 BSC
0.003
0.010
0.005
0.090
0.020
0.026
0.472 REF
5_
10_
0.005
0.007
0.016 BSC
2_
8_
0.005
0.012
0.638
0.654
0.008 REF
0_
0.638
0.654
0.043
0.051
Technical Data
Mechanical Data
253
Mechanical Data
12.6 52-Pin Thin Quad Flat Pack (Case 848D)
4X
4X TIPS
0.20 (0.008) H LM N
0.20 (0.008) T LM N
X
X=L, M, N
52
40
CL
39
AB
3X VIEW
AB
B
B1
13
BASE METAL
26
A1
VIEW Y
PLATING
V1
27
14
0.13 (0.005)
D
T LM
S1
SECTION ABAB
4X
2
0.10 (0.004) T
H
T
SEATING
PLANE
4X
3
VIEW AA
0.05 (0.002)
W
1
2XR
R1
0.25 (0.010)
C2
GAGE PLANE
K
C1
E
Z
VIEW AA
Technical Data
254
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS L, M AND N TO BE DETERMINED
AT DATUM PLANE H.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE T.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
1
2
3
MILLIMETERS
MIN
MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
1.70
0.05
0.20
1.30
1.50
0.20
0.40
0.45
0.75
0.22
0.35
0.65 BSC
0.07
0.20
0.50 REF
0.08
0.20
12.00 BSC
6.00 BSC
0.09
0.16
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0_
7_
0_
12 _ REF
5_
13 _
INCHES
MIN
MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
0.067
0.002
0.008
0.051
0.059
0.008
0.016
0.018
0.030
0.009
0.014
0.026 BSC
0.003
0.008
0.020 REF
0.003
0.008
0.472 BSC
0.236 BSC
0.004
0.006
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
0_
7_
0_
12 _ REF
5_
13 _
MOTOROLA
Mechanical Data
56-Pin Dual in-Line Package (Case #859)
56
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010)
29
B
1
28
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
L
H
SEATING
PLANE
F
D 56 PL
0.25 (0.010)
E
M
T A
M
56 PL
0.25 (0.010)
T B
INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014
0.022
0.035 BSC
0.032
0.046
0.070 BSC
0.300 BSC
0.008
0.015
0.115
0.135
0.600 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
0.89 BSC
0.81
1.17
1.778 BSC
7.62 BSC
0.20
0.38
2.92
3.43
15.24 BSC
0_
15 _
0.51
1.02
-A48
25
-B1
TIP TAPER
24
DETAIL X
-T-
SEATING
PLANE
DETAIL X
F
D 32 PL
0.51 (0.020)
G
M
T A
M 48 PL
N
J
INCHES
MIN
MAX
2.415
2.445
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.070 BSC
0.008
0.015
0.115
0.150
0.600 BSC
0
15
0.020
0.040
MILLIMETERS
MIN
MAX
61.34
62.10
13.72
14.22
3.94
5.08
0.36
0.55
1.02
1.52
2.54 BSC
1.79 BSC
0.20
0.38
2.92
3.81
15.24 BSC
0
15
0.51
1.01
48 PL
0.25 (0.010)
T B
DIM
A
B
C
D
F
G
H
J
K
L
M
N
Technical Data
Mechanical Data
255
Mechanical Data
Technical Data
256
MOTOROLA
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.3
13.4
13.5
13.2 Introduction
This section provides ordering information for the E-series devices.
Information is grouped by:
Standard devices
Technical Data
Ordering Information
257
Ordering Information
13.3 Standard Device Ordering Information
Description
CONFIG
Temperature
Frequency
MC Order Number
2 MHz
MC68HC11E9BCFN2
3 MHz
MC68HC11E9BCFN3
2 MHz
MC68HC11E1CFN2
3 MHz
MC68HC11E1CFN3
40C to +105C
2 MHz
MC68HC11E1VFN2
40C to +125C
2 MHz
MC68HC11E1MFN2
2 MHz
MC68HC11E0CFN2
3 MHz
MC68HC11E0CFN3
40C to +105C
2 MHz
MC68HC11E0VFN2
40C to +125C
2 MHz
MC68HC11E0MFN2
2 MHz
MC68HC711E9CFN2
3 MHz
MC68HC711E9CFN3
40C to +105C
2 MHz
MC68HC711E9VFN2
40C to +125C
2 MHz
MC68HC711E9MFN2
40C to +85C
2 MHz
MC68S711E9CFN2
0C to +70C
3 MHz
MC68HC711E20FN3
2 MHz
MC68HC711E20CFN2
3 MHz
MC68HC711E20CFN3
40C to +105C
2 MHz
MC68HC711E20VFN2
40C to +125C
2 MHz
MC68HC711E20MFN2
0C to +70C
2 MHz
MC68HC811E2FN2
40C to +85C
2 MHz
MC68HC811E2CFN2
40C to +105C
2 MHz
MC68HC811E2VFN2
40C to +125C
2 MHz
MC68HC811E2MFN2
$0F
40C to +85C
40C to +85C
No ROM
$0D
40C to +85C
No ROM, no EEPROM
$0C
40C to +85C
OTPROM
$0F
$0F
40C to +85C
20 Kbytes OTPROM
$0F
$FF
Technical Data
258
MOTOROLA
Ordering Information
Standard Device Ordering Information
Description
CONFIG
Temperature
Frequency
MC Order Number
$0F
40C to +85C
2 MHz
MC68HC11E9BCFU2
3 MHz
MC68HC11E9BCFU3
2 MHz
MC68HC11E1CFU2
3 MHz
MC68HC11E1CFU3
40C to +105C
2 MHz
MC68HC11E1VFU2
40C to +85C
2 MHz
MC68HC11E0CFU2
40C to +105C
2 MHz
MC68HC11E0VFU2
0C to +70C
3 MHz
MC68HC711E20FU3
2 MHz
MC68HC711E20CFU2
3 MHz
MC68HC711E20CFU3
40C to +105C
2 MHz
MC68HC711E20VFU2
40C to +125C
2 MHz
MC68HC711E20MFU2
2 MHz
MC68HC11E9BCPB2
3 MHz
MC68HC11E9BCPB3
2 MHz
MC68HC711E9CFS2
3 MHz
MC68HC711E9CFS3
40C to +105C
2 MHz
MC68HC711E9VFS2
40C to +125C
2 MHz
MC68HC711E9VFS2
0C o +70C
3 MHz
MC68HC711E20FS3
2 MHz
MC68HC711E20CFS2
3 MHz
MC68HC711E20CFS3
40C to +105C
2 MHz
MC68HC711E20VFS2
40C to +125C
2 MHz
MC68HC711E20MFS2
40C to +85C
No ROM
No ROM, no EEPROM
$0D
$0C
40C to +85C
20 Kbytes OTPROM
$0F
$0F
40C to +85C
$0F
40C to +85C
20 Kbytes EPROM
$0F
Technical Data
Ordering Information
259
Ordering Information
Description
CONFIG
Temperature
Frequency
MC Order Number
0C to +70C
2 MHz
MC68HC811E2P2
40C to +85C
2 MHz
MC68HC811E2CP2
40C to +105C
2 MHz
MC68HC811E2VP2
40C to +125C
2 MHz
MC68HC811E2MP2
2 MHz
MC68HC11E9BCB2
3 MHz
MC68HC11E9BCB3
2 MHz
MC68HC11E1CB2
3 MHz
MC68HC11E1CB3
40C to +105C
2 MHz
MC68HC11E1VB2
40C to +125C
2 MHz
MC68HC11E1MB2
2 MHz
MC68HC11E0CB2
3 MHz
MC68HC11E0CB3
40C to +105C
2 MHz
MC68HC11E0VB2
40C to +125C
2 MHz
MC68HC11E0MB2
$FF
$0F
40C to +85C
40C to +85C
No ROM
$0D
40C to +85C
No ROM, no EEPROM
$0C
Technical Data
260
MOTOROLA
Ordering Information
Custom ROM Device Ordering Information
Temperature
Frequency
MC Order Number
3 MHz
MC68HC11E9FN3
2 MHz
MC68HC11E9CFN2
3 MHz
MC68HC11E9CFN3
40C to +105C
2 MHz
MC68HC11E9VFN2
40C to +125C
2 MHz
MC68HC11E9MFN2
0C to +70C
3 MHz
MC68HC11E20FN3
2 MHz
MC68HC11E20CFN2
3 MHz
MC68HC11E20CFN3
40C to +105C
2 MHz
MC68HC11E20VFN2
40C to +125C
2 MHz
MC68HC11E20MFN2
0C to +70C
3 MHz
MC68HC11E9FU3
2 MHz
MC68HC11E9CFU2
3 MHz
MC68HC11E9CFU3
40C to +105C
2 MHz
MC68HC11E9VFU2
40C to +125C
2 MHz
MC68HC11E9MFU2
0C to +70C
3 MHz
MC68HC11E20FU3
2 MHz
MC68HC11E20CFU2
3 MHz
MC68HC11E20CFU3
40C to +105C
2 MHz
MC68HC11E20VFU2
40C to +125C
2 MHz
MC68HC11E20MFU2
40C to +85C
20 Kbytes custom ROM
40C to +85C
Custom ROM
40C to +85C
20 Kbytes Custom ROM
Technical Data
Ordering Information
261
Ordering Information
Description
Temperature
Frequency
MC Order Number
3 MHz
MC68HC11E9PB3
2 MHz
MC68HC11E9CPB2
3 MHz
MC68HC11E9CPB3
40C to +105C
2 MHz
MC68HC11E9VPB2
40C to +125C
2 MHz
MC68HC11E9MPB2
3 MHz
MC68HC11E9B3
2 MHz
MC68HC11E9CB2
3 MHz
MC68HC11E9CB3
40C to +105C
2 MHz
MC68HC11E9VB2
40C to +125C
2 MHz
MC68HC11E9MB2
Technical Data
262
MOTOROLA
Ordering Information
Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)
13.5 Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)
Description
Temperature
Frequency
MC Order Number
2 MHz
MC68L11E9FN2
2 MHz
MC68L11E1FN2
2 MHz
MC68L11E0FN2
2 MHz
MC68L11E9FU2
2 MHz
MC68L11E1FU2
2 MHz
MC68L11E0FU2
2 MHz
MC68L11E9PB2
2 MHz
MC68L11E1PB2
2 MHz
MC68L11E0PB2
2 MHz
MC68L11E9B2
2 MHz
MC68L11E1B2
2 MHz
MC68L11E0B2
20C to +70C
No ROM, no EEPROM
64-pin quad flat pack (QFP)
Custom ROM
No ROM
20C to +70C
No ROM, no EEPROM
52-pin thin quad flat pack (10 mm x 10 mm)
Custom ROM
No ROM
20C to +70C
No ROM, no EEPROM
56-pin dual in-line package with 0.70-inch lead spacing (SDIP)
Custom ROM
No ROM
20C to +70C
No ROM, no EEPROM
Technical Data
Ordering Information
263
Ordering Information
Technical Data
264
MOTOROLA
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
A.3
A.4
A.5
A.6
A.2 Introduction
This section provides information on the development support offered for
the E-series devices.
Technical Data
Development Support
265
Development Support
A.3 Motorola M68HC11 E-Series Development Tools
Device
MC68HC11E9
MC68HC711E9
MC68HC11E20
MC68HC711E20
MC68HC811E2
Package
Emulation
Module(1) (2)
Flex
Cable(1) (2)
MMDS11
Target Head(1) (2)
SPGMR
Programming
Adapter(3)
52 FN
M68EM11E20
M68CBL11C
M68TC11E20FN52
M68PA11E20FN52
52 PB
M68EM11E20
M68CBL11C
M68TC11E20PB52
M68PA11E20PB52
56 B
M68EM11E20
M68CBL11B
M68TC11E20B56
M68PA11E20B56
64 FU
M68EM11E20
M68CBL11C
M68TC11E20FU64
M68PA11E20FU64
52 FN
M68EM11E20
M68CBL11C
M68TC11E20FN52
M68PA11E20FN52
64 FU
M68EM11E20
M68CBL11C
M68TC11E20FU64
M68PA11E20FU64
48 P
M68EM11E20
M68CBL11B
M68TB11E20P48
M68PA11A8P48
52 FN
M68EM11E20
M68CBL11C
M68TC11E20FN52
M68PA11E20FN52
1. Each MMDS11 system consists of a system console (M68MMDS11), an emulation module, a flex cable, and a target head.
2. A complete EVS consists of a platform board (M68HC11PFB), an emulation module, a flex cable, and a target head.
3. Each SPGMR system consists of a universal serial programmer (M68SPGMR11) and a programming adapter. It can be
used alone or in conjunction with the MMDS11.
Monitor/debugger firmware
One-line assembler/disassembler
Technical Data
266
MOTOROLA
Development Support
Motorola Modular Development System (MMDS11)
Technical Data
Development Support
267
Development Support
Technical Data
268
MOTOROLA
Development Support
SPGMR11 Serial Programmer for M68HC11 MCUs
Technical Data
Development Support
269
Development Support
Technical Data
270
MOTOROLA
Technical Data
EVBU Schematic
271
EVBU Schematic
Technical Data
VCC
U3
25
C7
1 F
C8
0.1 F
VCC
1
J2
2
R4
47 K
MCU43
(PE0)
VCC
EVBU Schematic
R3
1K
MCU52 (VRH)
C9
0.1 F
MCU 34
MCU 33
MCU 32
MCU 31
MCU 30
MCU 29
MCU 28
MCU 27
34
33
32
31
30
29
28
27
MCU 20
MCU 21
MCU 22
MCU 23
MCU 24
MCU 25
20
21
22
23
24
25
MCU 43
MCU 45
MCU 47
MCU 49
MCU 44
MCU 46
MCU 48
MCU 50
43
45
47
49
44
46
48
50
MCU 52
MCU 51
52
51
1
NOTE 1
272
MCU [2 . . . 52]
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
PB5/A13
PB6/A14
PB7/A15
VDD
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5
PA4/OC4
PA5/OC3
PA6/OC2
PA7/OC1
PC0/AD0
PC1/AD1
PC2/AD2
PC3/AD3
PC4/AD4
PC5/AD5
PC6/AD6
PC7/AD7
PD0/RXD
PD1/TXD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
E
STRB/R/W
STRA/AS
RESET
IRQ
XIRQ
MODA/LIR
MODB/VSTBY
42
41
40
39
38
37
36
35
MCU42
MCU41
MCU40
MCU39
MCU38
MCU37
MCU36
MCU35
9
10
11
12
13
14
15
16
MCU9
MCU10
MCU11
MCU12
MCU13
MCU14
MCU15
MCU16
5
6
4
17
19
18
3
2
MCU5
MCU6
MCU4
MCU17
MCU19
MCU18
MCU3
MCU2
7
EXTAL
8
XTAL
VRH
VRL
VSS
MC68HC11E9FN
GND
MASTER RESET
VCC
VCC
VCC
2
RN1A
47 K
U2
INPUT
1
RESET
3
GND
MOTOROLA
MC34064P
RN1E
47 K
NOTE 1
MCU17 (RESET)
MCU21 (PD1/TXD)
J9
2
MCU18 (XIRQ)
MCU20 (PD0/RXD)
VCC
1
RN1D
47 K
5
VCC
1
RN1C
47 K
VCC
R1
47 K
RN1B
47 K
3
1
J7
2
MCU31 (PA3/OC5)
MCU19 (IRQ)
MCU3
(MODA/LIR)
MCU2
(MODB/VSTBY)
J6
MCU8
MCU7
1
1
J3
1
NOTE 1
R2
10 M
X1
8 MHz
NOTE 2
C5
27 pF
C6
27 pF
C12
6
+
C10
NOTE 1
VCC
VCC
NC
J4
J5
J8
SW1
VCC
1
20
18
1
3
15
16
13
14
11
12
19
CONNECTOR DB25
13
25
12
24
11
USERS TERMINAL OR PC
23
10
22
9
VCC
21
DCD
8
C14
DTR
20
10 F
7
20 V +
U4
19
17
V
DSR
6
DD
C1+
C13
18
C1
VSS 4
5
+
C2+
17
C2
CTS
6
4
TX1
DI1
16
J15
RX1 5
DD1
8
2
1 TXD 3
DI2
TX2
15
RX2 7
DD2
RXD 2
TX3 10
DI3
NOTE
1
14
RX3 9
DD3
1
2
VCC
GND
C11 MC145407
0.1 F
Notes:
1. Default cut traces installed from factory on bottom of the board.
2. X1 is shipped as a ceramic resonator with built-in capacitors. Holes are provided for a crystal and two capacitors.
P2
AN1060
Introduction
The M68HC11 Family of MCUs (microcontroller units) has a bootstrap
mode that allows a user-defined program to be loaded into the internal
random-access memory (RAM) by way of the serial communications
interface (SCI); the M68HC11 then executes this loaded program. The
loaded program can do anything a normal user program can do as well
as anything a factory test program can do because protected control bits
are accessible in bootstrap mode. Although the bootstrap mode is a
single-chip mode of operation, expanded mode resources are
accessible because the mode control bits can be changed while
operating in the bootstrap mode.
This application note explains the operation and application of the
M68HC11 bootstrap mode. Although basic concepts associated with
this mode are quite simple, the more subtle implications of these
functions require careful consideration. Useful applications of this mode
are overlooked due to an incomplete understanding of bootstrap mode.
Also, common problems associated with bootstrap mode could be
avoided by a more complete understanding of its operation and
implications.
Application Note
Topics discussed in this application note include:
MOTOROLA
Application Note
Basic Bootstrap Mode
Bootstrap mode is useful both at the component level and after the MCU
has been embedded into a finished user system.
At the component level, Motorola uses bootstrap mode to control a
monitored burn-in program for the on-chip electrically erasable
programmable read-only memory (EEPROM). Units to be tested are
loaded into special circuit boards that each hold many MCUS. These
boards are then placed in burn-in ovens. Driver boards outside the
ovens download an EEPROM exercise and diagnostic program to all
MCUs in parallel. The MCUs under test independently exercise their
internal EEPROM and monitor programming and erase operations. This
technique could be utilized by an end user to load program information
into the EPROM or EEPROM of an M68HC11 before it is installed into
an end product. As in the burn-in setup, many M68HC11s can be gang
programmed in parallel. This technique can also be used to program the
EPROM of finished products after final assembly.
Motorola also uses bootstrap mode for programming target devices on
the M68HC11 evaluation modules (EVM). Because bootstrap mode is a
privileged mode like special test, the EEPROM-based configuration
register (CONFIG) can be programmed using bootstrap mode on the
EVM.
The greatest benefits from bootstrap mode are realized by designing the
finished system so that bootstrap mode can be used after final
assembly. The finished system need not be a single-chip mode
application for the bootstrap mode to be useful because the expansion
bus can be enabled after resetting the MCU in bootstrap mode. Allowing
this capability requires almost no hardware or design cost and the
addition of this capability is invisible in the end product until it is needed.
The ability to control the embedded processor through downloaded
programs is achieved without the disassembly and chip-swapping
usually associated with such control. This mode provides an easy way
to load non-volatile memories such as EEPROM with calibration tables
or to program the application firmware into a one-time programmable
(OTP) MCU after final assembly.
Another powerful use of bootstrap mode in a finished assembly is for
final test. Short programs can be downloaded to check parts of the
AN1060 Rev. 1.0
MOTOROLA
275
Application Note
system, including components and circuitry external to the embedded
MCU. If any problems appear during product development, diagnostic
programs can be downloaded to find the problems, and corrected
routines can be downloaded and checked before incorporating them into
the main application program.
Bootstrap mode can also be used to interactively calibrate critical analog
sensors. Since this calibration is done in the final assembled system, it
can compensate for any errors in discrete interface circuitry and cabling
between the sensor and the analog inputs to the MCU. Note that this
calibration routine is a downloaded program that does not take up space
in the normal application program.
MOTOROLA
Application Note
Bootstrap Mode Logic
pins during reset, the selected mode, and the state of the MDA, SMOD,
and RBOOT control bits. Refer to the composite memory map and
information in Table 1 for the following discussion.
The MDA control bit is determined by the state of the MODA pin as the
MCU leaves reset. MDA selects between single-chip and expanded
operating modes. When MDA is 0, a single-chip mode is selected, either
normal single-chip mode or special bootstrap mode. When MDA is 1, an
expanded mode is selected, either normal expanded mode or special
test mode.
The SMOD control bit is determined by the inverted state of the MODB
pin as the MCU leaves reset. SMOD controls whether a normal mode or
a special mode is selected. When SMOD is 0, one of the two normal
modes is selected, either normal single-chip mode or normal expanded
mode. When SMOD is 1, one of the two special modes is selected, either
special bootstrap mode or special test mode. When either special mode
is in effect (SMOD = 1), certain privileges are in effect, for instance, the
ability to write to the mode control bits and fetching the reset and
interrupt vectors from $BFxx rather than $FFxx.
Table 1. Mode Selection Summary
Input Pins
MODB
MODA
RBOOT
SMOD
MDA
Normal expanded
Special bootstrap
Special test
The alternate vector locations are achieved by simply driving address bit
A14 low during all vector fetches if SMOD = 1. For special test mode, the
alternate vector locations assure that the reset vector can be fetched
from external memory space so the test system can control MCU
operation. In special bootstrap mode, the small boot ROM is enabled in
the memory map by RBOOT = 1 so the reset vector will be fetched from
this ROM and the bootloader firmware will control MCU operation.
277
Application Note
RBOOT is reset to 1 in bootstrap mode to enable the small boot ROM.
In the other three modes, RBOOT is reset to 0 to keep the boot ROM out
of the memory map. While in special test mode, SMOD = 1, which allows
the RBOOT control bit to be written to 1 by software to enable the boot
ROM for testing purposes.
MOTOROLA
Application Note
Automatic Selection of Baud Rate
NOTE:
Software can change some aspects of the memory map after reset.
Figure 2 shows how the bootloader program differentiates between the
default baud rate (7812 baud at a 2-MHz E-clock rate) and the alternate
baud rate (1200 baud at a 2-MHz E-clock rate). The host computer
sends an initial $FF character, which is used by the bootloader to
determine the baud rate that will be used for the downloading operation.
The top half of Figure 2 shows normal reception of $FF. Receive data
samples at [1] detect the falling edge of the start bit and then verify the
start bit by taking a sample at the center of the start bit time. Samples
are then taken at the middle of each bit time [2] to reconstruct the value
of the received character (all 1s in this case). A sample is then taken at
the middle of the stop bit time as a framing check (a 1 is expected) [3].
Unless another character immediately follows this $FF character, the
receive data line will idle in the high state as shown at [4].
The bottom half of Figure 2 shows how the receiver will incorrectly
receive the $FF character that is sent from the host at 1200 baud.
Because the receiver is set to 7812 baud, the receive data samples are
taken at the same times as in the upper half of Figure 2. The start bit at
1200 baud [5] is 6.5 times as long as the start bit at 7812 baud [6].
279
Application Note
$0000
512-BYTE
RAM
$01FF
EXTERNAL
(MAY BE REMAPPED
TO ANY 4K BOUNDARY)
EXTERNAL
$1000
64-BYTE
REGISTER
BLOCK
$103F
EXTERNAL
(MAY BE REMAPPED
TO ANY 4K BOUNDARY)
EXTERNAL
512-BYTE
EEPROM
$B600
(MAY BE DISABLED
BY AN EEPROM BIT)
$B7FF
$BFC0
EXTERNAL
EXTERNAL
$BF00
BOOT
ROM
SPECIAL
MODE
VECTORS
$BFC0
$BFFF
$BFFF
$D000
$FFC0
$FFFF
12K USER
EPROM
(or OTP)
(MAY BE DISABLED
BY AN EEPROM BIT)
$FFC0
NORMAL
MODE
VECTORS
SINGLE
CHIP
MODA = 0
MODB = 1
EXPANDED
MULTIPLEXED
MODA = 1
MODB = 1
SPECIAL
BOOTSTRAP
MODA = 0
MODB = 0
$FFFF
SPECIAL
TEST
MODA = 1
MODB = 0
OTE: Software can change some aspects of the memory map after reset.
$FF CHARACTER
@ 7812 BAUD
Rx DATA SAMPLES
[4]
[6]
START
BIT 0
BIT 1
BIT 2
BIT 3
S
[1]
$FF CHARACTER
@ 1200 BAUD
Rx DATA SAMPLES
( FOR 7812 BAUD )
START
0
[7]
[8]
BIT 4
[2] 1
$FF
BIT 5
BIT 6
BIT 7
STOP
[5]
[3]
BIT 0
? [9]
[11]
BIT 1
[12]
$C0
or $E0 [10]
MOTOROLA
Application Note
Main Bootloader Program
Samples taken at [7] detect the failing edge of the start bit and verify it is
a logic 0. Samples taken at the middle of what the receiver interprets as
the first five bit times [8] detect logic 0s. The sample taken at the middle
of what the receiver interprets as bit 5 [9] may detect either a 0 or a 1
because the receive data has a rising transition at about this time. The
samples for bits 6 and 7 detect 1s, causing the receiver to think the
received character was $C0 or $E0 [10] at 7812 baud instead of the $FF
which was sent at 1200 baud. The stop bit sample detects a 1 as
expected [11], but this detection is actually in the middle of bit 0 of the
1200 baud $FF character. The SCI receiver is not confused by the rest
of the 1200 baud $FF character because the receive data line is high
[12] just as it would be for the idle condition. If a character other than $FF
is sent as the first character, an SCI receive error could result.
281
Application Note
The SCI receiver and transmitter are enabled. The receiver is required
by the bootloading process, and the transmitter is used to transmit data
back to the host computer for optional verification. The last item in the
initialization is to set an intercharacter delay constant used to terminate
the download when the host computer stops sending data to the
MC68HC711E9. This delay constant is stored in the timer output
compare 1 (TOC1) register, but the on-chip timer is not used in the
bootloader program. This example illustrates the extreme measures
used in the bootloader firmware to minimize memory usage. However,
such measures are not usually considered good programming technique
because they are misleading to someone trying to understand the
program or use it as an example.
After initialization, a break character is transmitted [3] by the SCI. By
connecting the TxD pin to the RxD pin (with a pullup because of port D
wired-OR mode), this break will be received as a $00 character and
cause an immediate jump [4] to the start of the on-chip EEPROM ($B600
in the MC68HC711E9). This feature is useful to pass control to a
program in EEPROM essentially from reset. Refer to Common
Bootstrap Mode Problems before using this feature.
If the first character is received as $FF, the baud rate is assumed to be
the default rate (7812 baud at a 2-MHz E-clock rate). If $FF was sent at
1200 baud by the host, the SCI will receive the character as $E0 or $C0
because of the baud rate mismatch, and the bootloader will switch to
1200 baud [5] for the rest of the download operation. When the baud rate
is switched to 1200 baud, the delay constant used to monitor the
intercharacter delay also must be changed to reflect the new character
time.
At [6], the Y index register is initialized to $0000 to point to the start of
on-chip RAM. The index register Y is used to keep track of where the
next received data byte will be stored in RAM. The main loop for loading
begins at [7].
The number of data bytes in the downloaded program can be any
number between 0 and 512 bytes (the size of on-chip RAM). This
procedure is called "variable-length download" and is accomplished by
ending the download sequence when an idle time of at least four
character times occurs after the last character to be downloaded. In
AN1060 Rev. 1.0
282
MOTOROLA
Application Note
Main Bootloader Program
M68HC11 Family members which have 256 bytes of RAM, the download
length is fixed at exactly 256 bytes plus the leading $FF character.
The intercharacter delay counter is started [8] by loading the delay
constant from TOC1 into the X index register. The 19-E-cycle wait loop
is executed repeatedly until either a character is received [9] or the
allowed intercharacter delay time expires [10]. For 7812 baud, the delay
constant is 10,241 E cycles (539 x 19 E cycles per loop). Four character
times at 7812 baud is 10,240 E cycles (baud prescale of 4 x baud divider
of 4 x 16 internal SCI clocks/bit time x 10 bit times/character x 4
character times). The delay from reset to the initial $FF character is not
critical since the delay counter is not started until after the first character
($FF) is received.
To terminate the bootloading sequence and jump to the start of RAM
without downloading any data to the on-chip RAM, simply send $FF and
nothing else. This feature is similar to the jump to EEPROM at [4] except
the $FF causes a jump to the start of RAM. This procedure requires that
the RAM has been loaded with a valid program since it would make no
sense to jump to a location in uninitialized memory.
After receiving a character, the downloaded byte is stored in RAM [11].
The data is transmitted back to the host [12] as an indication that the
download is progressing normally. At [13], the RAM pointer is
incremented to the next RAM address. If the RAM pointer has not
passed the end of RAM, the main download loop (from [7] to [14]) is
repeated.
When all data has been downloaded, the bootloader goes to [16]
because of an intercharacter delay timeout [10] or because the entire
512-byte RAM has been filled [15]. At [16], the X and Y index registers
are set up for calling the PROGRAM utility routine, which saves the user
from having to do this in a downloaded program. The PROGRAM utility
is fully explained in EPROM Programming Utility. The final step of the
bootloader program is to jump to the start of RAM [17], which starts the
users downloaded program.
283
Application Note
[1]
START
FROM RESET
IN BOOT MODE
[2]
INITIALIZATION:
SP = TOP OF RAM ($01FF)
X = START OF REGS ($1000)
SPCR = $20 (SET DWOM BIT)
BAUD = $A2 ( 4; 4) (7812.5 BAUD @ 2 MHz)
SCCR2 = $C0 (Tx & Rx ON)
TOC1 = DELAY CONSTANT (539 = 4 SCI CHARACTER TIMES)
[3]
SEND BREAK
NO
[4]
YES
YES
N O T Z E R O
JUMP TO START
OF EEPROM ($B600)
NOTE THAT A BREAK
CHARACTER IS ALSO
RECEIVED AS $00
NO
[6]
W A IT
[8]
YES
[9]
NO
LOOP =
19
CYCLES
[11]
[12]
[13]
NO
[15]
JUMP TO START
OF RAM ($0000)
[14]
[16]
[17]
MOTOROLA
Application Note
UPLOAD Utility
UPLOAD Utility
The UPLOAD utility subroutine transfers data from the MCU to a host
computer system over the SCI serial data link.
NOTE:
285
Application Note
To understand the detailed operation of the EPROM programming utility,
refer to Figure 4 during the following discussion. Figure 4 is composed
of three interrelated parts. The upper-left portion shows the flowchart of
the PROGRAM utility running in the boot ROM of the MCU. The upperright portion shows the flowchart for the user-supplied driver program
running in the host computer. The lower portion of Figure 4 is a timing
sequence showing the relationship of operations between the MCU and
the host computer. Reference numbers in the flowcharts in the upper
half of Figure 4 have matching numbers in the lower half to help the
reader relate the three parts of the figure.
The shaded area [1] refers to the software and hardware latency in the
MCU leading to the transmission of a character (in this case, the $FF).
The shaded area [2] refers to a similar latency in the host computer (in
this case, leading to the transmission of the first data character to the
MCU).
The overall operation begins when the MCU sends the first character
($FF) to the host computer, indicating that it is ready for the first data
character. The host computer sends the first data byte [3] and enters its
main loop. The second data character is sent [4], and the host then waits
[5] for the first verify byte to come back from the MCU.
After the MCU sends $FF [8], it enters the WAIT1 loop [9] and waits for
the first data character from the host. When this character is received
[10], the MCU programs it into the address pointed to by the Y index
register. When the programming time delay is over, the MCU reads the
programmed data, transmits it to the host for verification [11], and
returns to the top of the WAIT1 loop to wait for the next data character
[12]. Because the host previously sent the second data character, it is
already waiting in the SCI receiver of the MCU. Steps [13], [14], and [15]
correspond to the second pass through the WAIT1 loop.
Back in the host, the first verify character is received, and the third data
character is sent [6]. The host then waits for the second verify character
[7] to come back from the MCU. The sequence continues as long as the
host continues to send data to the MCU. Since the WAIT1 loop in the
PROGRAM utility is an indefinite loop, reset is used to end the process
in the MCU after the host has finished sending data to be programmed.
MOTOROLA
Application Note
EPROM Programming Utility
INITIALIZE...
X = PROGRAM TIME
Y = FIRST ADDRESS
START
[8]
NO
$BF00 - PROGRAM
START
INDICATES READY
SEND $FF
TO HOST
[9]
WAIT1
[3]
YES
YES
SEND NEXT DATA
PROGRAM BYTE
[4] [6]
[10] [13]
[5] [7]
NO
[11] [14]
YES
[12] [15]
PROGRAM CONTINUES
AS LONG AS DATA
IS RECEIVED
AA
AA
$FF
[4]
[1]
EPROM PROGRAMMING
[3]
AA
AA
AAAA
AA
AA
AAAA
V1
[5]
[2]
[10]
$FF
D4
[13]
P1
[9]
P2
[11]
[12]
V1
[14]
[15]
V2
AA
A
AAA
AA
A
AAA
V3
[7]
D3
INDICATE ERROR
DONE
V2
D2
NO
MORE TO VERIFY ?
NO
[6]
D1
[8]
P3
V4
HOST SENDING
DATA FOR
MCU EPROM
D5
MC68HC711E9
EXECUTING
"PROGRAM" LOOP
P4
V3
V4
287
Application Note
Allowing for Bootstrap Mode
Since bootstrap mode requires few connections to the MCU, it is easy to
design systems that accommodate bootstrap mode.
Bootstrap mode is useful for diagnosing or repairing systems that have
failed due to changes in the CONFIG register or failures of the expansion
address/data buses, (rendering programs in external memory useless).
Bootstrap mode can also be used to load information into the EPROM or
EEPROM of an M68HC11 after final assembly of a module. Bootstrap
mode is also useful for performing system checks and calibration
routines. The following paragraphs explain system requirements for use
of bootstrap mode in a product.
It must be possible to force the MODA and MODB pins to logic 0, which
implies that these two pins should be pulled up to VDD through resistors
rather than being tied directly to VDD. If mode pins are connected directly
to VDD, it is not possible to force a mode other than the one the MCU is
hard wired for. It is also good practice to use pulldown resistors to VSS
rather than connecting mode pins directly to VSS because it is
sometimes a useful debug aid to attempt reset in modes other than the
one the system was primarily designed for. Physically, this requirement
sometimes calls for the addition of a test point or a wire connected to one
or both mode pins. Mode selection only uses the mode pins while
RESET is active.
RESET
It must be possible to initiate a reset while the mode select pins are held
low. In systems where there is no provision for manual reset, it is usually
possible to generate a reset by turning power off and back on.
RxD Pin
It must be possible to drive the PD0/RxD pin with serial data from a host
computer (or another MCU). In many systems, this pin is already used
for SCI communications; thus no changes are required.
In systems where the PD0/RxD pin is normally used as a generalpurpose output, a serial signal from the host can be connected to the pin
AN1060 Rev. 1.0
288
MOTOROLA
Application Note
Allowing for Bootstrap Mode
A
AAA
A
A
A
FROM
HOST
SYSTEM
RS232
LEVEL
SHIFTER
EXISTING
CONTROL
SIGNAL
EXISTING
DRIVER
SERIES
RESISTOR
MC68HC11
RxD/PD0
(BEING USED
AS INPUT)
The bootloader program uses the PD1/TxD pin to send verification data
back to the host computer. To minimize the possibility of conflicts with
circuitry connected to this pin, port D is configured for wire-OR mode by
the bootloader program during initialization. Since the wire-OR
configuration prevents the pin from driving active high levels, a pullup
resistor to VDD is needed if the TxD signal is used.
In systems where the PD1/TxD pin is normally used as a generalpurpose output, there are no output driver conflicts. It may be important
to consider what the existing logic will do with the SCI serial data instead
of the signals that would have been produced by the PD1 pin.
In systems where the PD1 pin is normally used as a general-purpose
input, the driver circuit that drives the PD1 pin must be designed so that
the PD1/TxD pin driver in the MCU can override this driver. A simple
series resistor between the driver and the PD1 pin can solve this
problem. The TxD pin can then be configured as an output, and the
289
Application Note
series resistor will prevent direct conflict between the internal TxD driver
and the external driver connected to PD1 through the series resistor.
Other
The bootloader firmware sets the DWOM control bit, which configures all
port D pins for wire-OR operation. During the bootloading process, all
port D pins except the PD1/TxD pin are configured as high-impedance
inputs. Any port D pin that normally is used as an output should have a
pullup resistor so it does not float during the bootloading process.
MOTOROLA
Application Note
Driving Boot Mode from Another M68HC11
291
Application Note
AAAAAAAAAAAAAAAAAA
AA
AAAAA
A
AA
AA
AA
A
AA
AA
AA
AA
A AAA
AA AAA
A AAA
A
COM
+12.25V
M68HC11EVBU
PREWIRED AREA
WIRE-WRAP AREA
P4
PE7
50
50
ON
R11
P5
R14
15K
50
V PP
+ 100
C18
20 F
OFF
S2
R15
10K
MASTER
MCU
U3
MC68HC711E9
18
PB7
35
35
R8
35
17
XIRQ/V PPE
RESET
3.3K
V DD
PB1
PB0
41
41
42
42
R12 1K
D5
RED
R13 1K
D6
GREEN
41
42
26
C17
0.1 F
VDD
VSS
J6
XTAL
MODB
V DD
TxD
21
21
R10
15K
21
[1]
RxD
V DD
35
J3
20
20
J9
R7
10K
20
PB7
RxD
R9
10K
20
21
[2]
J8
EXTAL
TARGET
MCU
U6
3
2
TxD
MODA
MODB
TO/FROM
RS232 LEVEL
TRANSLATOR
U4
MOTOROLA
Application Note
Driving Boot Mode from Another M68HC11
293
Application Note
R14Rl5. The PE7 input was chosen because the internal circuitry for
port E pins can tolerate voltages slightly higher than VDD; therefore,
resistors R14 and R15 are less critical. No data to be programmed is
passed to the target MCU until the master MCU senses that VPP has
been stable for about 200 ms.
When VPP is ready, the master MCU turns on the red LED (light-emitting
diode) and begins passing data to the target MCU. EPROM
Programming Utility explains the activity as data is sent from the
master MCU to the target MCU and programmed into the EPROM of the
target. The master MCU in the EVBU corresponds to the HOST in the
programming utility description and the "PROGRAM utility in MCU" is
running in the bootstrap ROM of the target MCU.
Each byte of data sent to the target is programmed and then the
programmed location is read and sent back to the master for verification.
If any byte fails, the red and green LEDs are turned off, and the
programming operation is aborted. If the entire 12 Kbytes are
programmed and verified successfully, the red LED is turned off, and the
green LED is turned on to indicate success. The programming of all 12
Kbytes takes about 30 seconds.
After a programming operation, the VPP switch (S2) should be turned off
before the EVBU power is turned off.
V
CUT TRACE
AS SHOWN
DD
RN1D
47K
TO
TOMCU
MCU
XIRQ/V
XIRQ/V
PPE
PPE
PIN
PIN
P5-18
REMOVE J7
JUMPER
J14
TO
MC68HC68T1
50
42
P4-18
J7
48
46
44
45
9
8
10
41
3
1
47
15
13
38
28
34
35 33
19
20
27
21
25
BE SURE NO
JUMPER IS
ON J14
MOTOROLA
Application Note
Listing 1. MCU-to-MCU Duplicator Program
**************************************************
* 68HC711E9 Duplicator Program for AN1060
**************************************************
103D
0028
0004
0080
0002
0001
000A
002E
0080
0020
002F
BF00
D000
B600
*****
* Equates - All reg addrs except INIT are 2-digit
*
for direct addressing
*****
INIT
EQU
$103D
RAM, Reg mapping
SPCR
EQU
$28
DWOM in bit-5
PORTB
EQU
$04
Red LED = bit-1, Grn = bit-0
* Reset of prog socket = bit-7
RESET
EQU
%10000000
RED
EQU
%00000010
GREEN
EQU
%00000001
PORTE
EQU
$0A
Vpp Sense in bit-7, 1=ON
SCSR
EQU
$2E
SCI status register
* TDRE, TC, RDRF, IDLE; OR, NF, FE, TDRE
EQU
%10000000
RDRF
EQU
%00100000
SCDR
EQU
$2F
SCI data register
PROGRAM
EQU
$BF00
EPROM prog utility in boot ROM
EPSTRT
EQU
$D000
Starting address of EPROM
ORG
$B600
Start of EEPROM
**************************************************
*
B600 7F103D
BEGIN
CLR
INIT
Moves Registers to $0000-3F
B603 8604
LDAA
#$04
Pattern for DWOM off, no SPI
B605 9728
STAA
SPCR
Turns off DWOM in EVBU MCU
B607 8680
LDAA
#RESET
B609 9704
STAA
PORTB
Release reset to target MCU
B60B 132E20FC WT4BRK
BRCLR SCSR RDRF WT4BRK Loop till char received
B60F 86FF
LDAA
#$FF
Leading char for bootload ...
B611 972F
STAA
SCDR
to target MCU
B613 CEB675
LDX
#BLPROG
Point at program for target
B616 8D53
BLLOOP
BSR
SEND1
Bootload to target
B618 8CB67D
CPX
#ENDBPR
Past end ?
B61B 26F9
BNE
BLLOOP
Continue till all sent
*****
* Delay for about 4 char times to allow boot related
* SCI communications to finish before clearing
* Rx related flags
B61D CE06A7
LDX
#1703
# of 6 cyc loops
B620 09
DLYLP
DEX
[3]
B621 26FD
BNE
DLYLP
[3] Total loop time = 6 cyc
B623 962E
LDAA
SCSR
Read status (RDRF will be set)
B625 962F
LDAA
SCDR
Read SCI data reg to clear RDRF
295
Application Note
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
*****
* Now wait for character from target to indicate its ready for
* data to be programmed into EPROM
B627 132E20FC WT4FF
BRCLR SCSR RDRF WT4FF Wait for RDRF
B62B 962F
LDAA
SCDR
Clear RDRF, dont need data
B62D CED000
LDX
#EPSTRT
Point at start of EPROM
* Handle turn-on of Vpp
B630 18CE523D WT4VPP
LDY
#21053
Delay counter (about 200ms)
B634 150402
BCLR
PORTB RED
Turn off RED LED
B637 960A
DLYLP2
LDAA
PORTE
[3] Wait for Vpp to be ON
B639 2AF5
BPL
WT4VPP
[3] Vpp sense is on port E MSB
B63B 140402
BSET
PORTB RED
[6] Turn on RED LED
B63E 1809
DEY
[4]
B640 26F5
BNE
DLYLP2
[3] Total loop time = 19 cyc
* Vpp has been stable for 200ms
B642
B646
B648
B64B
B64D
B64F
B653
B655
B658
B65A
B65D
B65F
B65F
B661
B663
B663
B666
B666
B669
B66B
18CED000
8D23
8C0000
DATALP
2702
8D1C
132E20FC VERF
962F
18A100
2705
150403
2007
LDY
BSR
CPX
BEQ
BSR
BRCLR
LDAA
CMPA
BEQ
BCLR
BRA
#EPSTRT
X=Tx pointer, Y=verify pointer
SEND1
Send first data to target
#0
X points at $0000 after last
VERF
Skip send if no more
SEND1
Send another data char
SCSR RDRF VERF
Wait for Rx ready
SCDR
Get char and clr RDRF
0,Y
Does char verify ?
VERFOK
Skip error if OK
PORTB (RED+GREEN) Turn off LEDs
DUNPRG
Done (programming failed)
1808
26E5
INY
BNE
DATALP
BSET
PORTB GREEN
Grn LED ON
BCLR
BRA
VERFOK
140401
150482
20FE
DUNPRG
**************************************************
* Subroutine to get & send an SCI char. Also
* advances pointer (X).
**************************************************
B66B A600
SEND1
LDAA
0,X
Get a character
B66D 132E80FC TRDYLP
BRCLR SCSR TDRE TRDYLP Wait for TDRE
B671 972F
STAA
SCDR
Send character
B673 08
INX
Advance pointer
B674 39
RTS
** Return **
MOTOROLA
Application Note
Listing 1. MCU-to-MCU Duplicator Program
96
97
98
99
100
101
102
103
104
B675 8604
B677 B71028
B67A 7EBF00
B67D
Symbol Table:
Symbol Name
BEGIN
BLLOOP
BLPROG
DATALP
DLYLP
DLYLP2
DUNPRG
ENDBPR
EPSTRT
GREEN
INIT
PORTB
PORTE
PROGRAM
RDRF
RED
RESET
SCDR
SCSR
SEND1
SPCR
TDRE
TRDYLP
VERF
VERFOK
WT4BRK
WT4FF
WT4VPP
**************************************************
* Program to be bootloaded to target 711E9
**************************************************
BLPROG
LDAA
#$04
Pattern for DWOM off, no SPI
STAA
$1028
Turns off DWOM in target MCU
* NOTE: Cant use direct addressing in target MCU because
*
regs are located at $1000.
JMP
PROGRAM
Jumps to EPROM prog routine
ENDBPR
EQU
*
Value
Def.#
B600
B616
B675
B648
B620
B637
B666
B67D
D000
0001
103D
0004
000A
BF00
0020
0002
0080
002F
002E
B66B
0028
0080
B66D
B64F
B65F
B60B
B627
B630
*00029
*00038
*00099
*00068
*00046
*00059
*00083
*00104
*00023
*00015
*00009
*00011
*00016
*00022
*00020
*00014
*00013
*00021
*00017
*00090
*00010
*00019
*00091
*00071
*00078
*00034
*00053
*00057
Errors:
Labels:
Last Program Address:
Last Storage Address:
Program Bytes:
Storage Bytes:
00040
00037
00079
00047
00063
00076
00039
00055
00075
00029
00033
00059
00103
00034
00058
00032
00036
00034
00038
00031
00091
00091
00069
00074
00034
00053
00060
None
28
$B67C
$0000
$007D
$0000
00066
00081
00058 00061 00075 00081 00083
00053
00061
00083
00049
00048
00067
00071
00075 00083
00054 00072 00092
00053 00071 00091
00070
00071
125
0
297
Application Note
Driving Boot Mode from a Personal Computer
In this example, a personal computer is used as the host to drive the
bootloader of an MC68HC711E9. An M68HC11 EVBU is used for the
target MC68HC711E9. A large program is transferred from the personal
computer into the EPROM of the target MC68HC711E9.
Hardware
Software
Macintosh
MOTOROLA
Application Note
Driving Boot Mode from a Personal Computer
47K
NORMAL EVBU
OPERATION
100
+12.25 V
+
PROGRAMMING
POWER
20 F
PROGRAM
EPROM
JUMPER
TO P5-18
(XIRQ/V
)
PPE
COMMON
PC0
P5-9
1K
LED
299
Application Note
This S-record translator only looks for the S1 records that contain the
actual object code. All other S-record types are ignored.
When an S1 record is found (lines 10001024), the next two characters
form the hex byte giving the number of hex bytes to follow. This byte is
converted to integer by the same subroutine that converted the
bootloaded code from the DATA statements. This BYTECOUNT is
adjusted by subtracting 3, which accounts for the address and checksum
bytes and leaves just the number of object-code bytes in the record.
Starting at line 1100, the 2-byte (4-character) starting address is
converted to decimal. This address is the starting address for the object
code bytes to follow. An index into the CODE% array is formed by
subtracting the base address initialized at the start of the program from
the starting address for this S record.
A FOR-NEXT loop starting at line 1130 converts the object code bytes
to decimal and saves them in the CODE% array. When all the object
code bytes have been converted from the current S record, the program
loops back to find the next S1 record.
A problem arose with the BASIC programming technique used. The draft
versions of this program tried saving the object code bytes directly as
binary in a string array. This caused "Out of Memory" or "Out of String
Space" errors on both a 2-Mbyte Macintosh and a 640-Kbyte PC. The
solution was to make the array an integer array and perform the integerto-binary conversion on each byte as it is sent to the target part.
The one compromise made to accommodate both Macintosh and PC
versions of BASIC is in lines 1500 and 1505. Use line 1500 and
comment out line 1505 if the program is to be run on a Macintosh, and,
conversely, use line 1505 and comment out line 1500 if a PC is used.
After the COM port is opened, the code to be bootloaded is modified by
adding the $FF to the start of the string. $FF synchronizes the
bootloader in the MC68HC711E9 to 1200 baud. The entire string is
simply sent to the COM port by PRINTing the string. This is possible
since the string is actually queued in BASICs COM buffer, and the
operating system takes care of sending the bytes out one at a time. The
M68HC11 echoes the data received for verification. No automatic
MOTOROLA
Application Note
Driving Boot Mode from a Personal Computer
301
Application Note
Modifications
This example programmed version 3.4 of the BUFFALO monitor into the
EPROM of an MC68HC711E9; the changes to the BASIC program to
download some other program are minor.
The necessary changes are:
1.
Operation
Configure the EVBU for boot mode operation by putting a jumper at J3.
Ensure that the trace command jumper at J7 is not installed because this
would connect the 12-V programming voltage to the OC5 output of the
MCU.
Connect the EVBU to its dc power supply. When it is time to program the
MCU EPROM, turn on the 12-volt programming power supply to the new
circuitry in the wire-wrap area.
Connect the EVBU serial port to the appropriate serial port on the host
system. For the Macintosh, this is the modem port with a modem cable.
For the MS-DOS computer, it is connected to COM1 with a straight
through or modem cable. Power up the host system and start the BASIC
program. If the program has not been compiled, this is accomplished
from within the appropriate BASIC compiler or interpreter. Power up the
EVBU.
Answer the prompt for filename with either a [RETURN] to accept the
default shown or by typing in a new filename and pressing [RETURN].
MS-DOS is a registered trademark of Microsoft Corporation in the United States and other
countries.
MOTOROLA
Application Note
Driving Boot Mode from a Personal Computer
The program will inform the user that it is working on converting the file
from S records to binary. This process will take from 30 seconds to a few
minutes, depending on the computer.
A prompt reading, "Comm port open?" will appear at the end of the file
conversion. This is the last chance to ensure that everything is properly
configured on the EVBU. Pressing [RETURN] will send the bootcode to
the target MC68HC711E9. The program then informs the user that the
bootload code is being sent to the target, and the results of the echoing
of this code are displayed on the screen.
Another prompt reading "Programming is ready to begin. Are you?" will
appear. Turn on the 12-volt programming power supply and press
[RETURN] to start the actual programming of the target EPROM.
A count of the byte being verified will be updated continually on the
screen as the programming progresses. Any failures will be flagged as
they occur.
When programming is complete, a message will be displayed as well as
a prompt requesting the user to press [RETURN] to quit.
Turn off the 12-volt programming power supply before turning off 5 volts
to the EVBU.
303
Application Note
Listing 2. BASIC Program for Personal Computer
1 ***********************************************************************
2 *
3 *
E9BUF.BAS - A PROGRAM TO DEMONSTRATE THE USE OF THE BOOT MODE
4 *
ON THE HC11 BY PROGRAMMING AN HC711E9 WITH
5 *
BUFFALO 3.4
6 *
7 *
REQUIRES THAT THE S-RECORDS FOR BUFFALO (BUF34.S19)
8 *
BE AVAILABLE IN THE SAME DIRECTORY OR FOLDER
9 *
10 *
THIS PROGRAM HAS BEEN RUN BOTH ON A MS-DOS COMPUTER
11 *
USING QUICKBASIC 4.5 AND ON A MACINTOSH USING
12 *
QUICKBASIC 1.0.
14 *
15 ************************************************************************
25 H$ = "0123456789ABCDEF"
STRING TO USE FOR HEX CONVERSIONS
30 DEFINT B, I: CODESIZE% = 8192: ADRSTART= 57344!
35 BOOTCOUNT = 25
NUMBER OF BYTES IN BOOT CODE
40 DIM CODE%(CODESIZE%)
BUFFALO 3.4 IS 8K BYTES LONG
45 BOOTCODE$ = ""
INITIALIZE BOOTCODE$ TO NULL
49 REM ***** READ IN AND SAVE THE CODE TO BE BOOT LOADED *****
50 FOR I = 1 TO BOOTCOUNT
# OF BYTES IN BOOT CODE
55 READ Q$
60 A$ = MID$(Q$, 1, 1)
65 GOSUB 7000
CONVERTS HEX DIGIT TO DECIMAL
70 TEMP = 16 * X
HANG ON TO UPPER DIGIT
75 A$ = MID$(Q$, 2, 1)
80 GOSUB 7000
85 TEMP = TEMP + X
90 BOOTCODE$ = BOOTCODE$ + CHR$(TEMP)
BUILD BOOT CODE
95 NEXT I
96 REM ***** S-RECORD CONVERSION STARTS HERE *****
97 FILNAM$="BUF34.S19"
DEFAULT FILE NAME FOR S-RECORDS
100 CLS
105 PRINT "Filename.ext of S-record file to be downloaded (";FILNAM$;") ";
107 INPUT Q$
110 IF Q$<>"" THEN FILNAM$=Q$
120 OPEN FILNAM$ FOR INPUT AS #1
130 PRINT : PRINT "Converting "; FILNAM$; " to binary..."
999 REM ***** SCANS FOR S1 RECORDS *****
1000 GOSUB 6000
GET 1 CHARACTER FROM INPUT FILE
1010 IF FLAG THEN 1250
FLAG IS EOF FLAG FROM SUBROUTINE
1020 IF A$ <> "S" THEN 1000
1022 GOSUB 6000
1024 IF A$ <> "1" THEN 1000
1029 REM ***** S1 RECORD FOUND, NEXT 2 HEX DIGITS ARE THE BYTE COUNT *****
1030 GOSUB 6000
1040 GOSUB 7000
RETURNS DECIMAL IN X
MOTOROLA
Application Note
Listing 2. BASIC Program for Personal Computer
1050
1060
1070
1080
1090
1099
1100
1102
1104
1106
1108
1110
1112
1114
1116
1118
1120
1122
1124
1129
1130
1140
1150
1160
1170
1180
1190
1200
1210
1220
1230
1250
1499
1500
1505
1510
1512
1513
1514
1515
1520
1530
1540
1550
1560
1564
1565
1570
1590
1595
1597
BYTECOUNT = 16 * X
ADJUST FOR HIGH NIBBLE
GOSUB 6000
GOSUB 7000
BYTECOUNT = BYTECOUNT + X
ADD LOW NIBBLE
BYTECOUNT = BYTECOUNT - 3
ADJUST FOR ADDRESS + CHECKSUM
REM ***** NEXT 4 HEX DIGITS BECOME THE STARTING ADDRESS FOR THE DATA *****
GOSUB 6000
GET FIRST NIBBLE OF ADDRESS
GOSUB 7000
CONVERT TO DECIMAL
ADDRESS= 4096 * X
GOSUB 6000
GET NEXT NIBBLE
GOSUB 7000
ADDRESS= ADDRESS+ 256 * X
GOSUB 6000
GOSUB 7000
ADDRESS= ADDRESS+ 16 * X
GOSUB 6000
GOSUB 7000
ADDRESS= ADDRESS+ X
ARRAYCNT = ADDRESS-ADRSTART
INDEX INTO ARRAY
REM ***** CONVERT THE DATA DIGITS TO BINARY AND SAVE IN THE ARRAY *****
FOR I = 1 TO BYTECOUNT
GOSUB 6000
GOSUB 7000
Y = 16 * X
SAVE UPPER NIBBLE OF BYTE
GOSUB 6000
GOSUB 7000
Y = Y + X
ADD LOWER NIBBLE
CODE%(ARRAYCNT) = Y
SAVE BYTE IN ARRAY
ARRAYCNT = ARRAYCNT + 1
INCREMENT ARRAY INDEX
NEXT I
GOTO 1000
CLOSE 1
REM ***** DUMP BOOTLOAD CODE TO PART *****
OPEN "R",#2,"COM1:1200,N,8,1" Macintosh COM statement
OPEN "COM1:1200,N,8,1,CD0,CS0,DS0,RS" FOR RANDOM AS #2 DOS COM statement
INPUT "Comm port open"; Q$
WHILE LOC(2) >0
FLUSH INPUT BUFFER
GOSUB 8020
WEND
PRINT : PRINT "Sending bootload code to target part..."
A$ = CHR$(255) + BOOTCODE$ ADD HEX FF TO SET BAUD RATE ON TARGET HC11
GOSUB 6500
PRINT
FOR I = 1 TO BOOTCOUNT
# OF BYTES IN BOOT CODE BEING ECHOED
GOSUB 8000
K=ASC(B$):GOSUB 8500
PRINT "Character #"; I; " received = "; HX$
NEXT I
PRINT "Programming is ready to begin.": INPUT "Are you ready"; Q$
CLS
WHILE LOC(2) > 0
FLUSH INPUT BUFFER
305
Application Note
1598
1599
1600
1610
1620
1625
1630
1635
1640
1650
1660
1664
1665
1666
1668
1669
1670
1680
1690
1700
1710
1713
1714
1715
1716
1720
4900
4910
5000
5900
5910
5930
5940
6000
6010
6020
6030
6490
6492
6494
6496
6500
6510
6590
6594
6596
7000
7010
7020
7030
GOSUB 8020
WEND
XMT = 0: RCV = 0
POINTERS TO XMIT AND RECEIVE BYTES
A$ = CHR$(CODE%(XMT))
GOSUB 6500
SEND FIRST BYTE
FOR I = 1 TO CODESIZE% - 1
ZERO BASED ARRAY 0 -> CODESIZE-1
A$ = CHR$(CODE%(I))
SEND SECOND BYTE TO GET ONE IN QUEUE
GOSUB 6500
SEND IT
GOSUB 8000
GET BYTE FOR VERIFICATION
RCV = I - 1
LOCATE 10,1:PRINT "Verifying byte #"; I; "
"
IF CHR$(CODE%(RCV)) = B$ THEN 1670
K=CODE%(RCV):GOSUB 8500
LOCATE 1,1:PRINT "Byte #"; I; "
", " - Sent "; HX$;
K=ASC(B$):GOSUB 8500
PRINT " Received "; HX$;
NEXT I
GOSUB 8000
GET BYTE FOR VERIFICATION
RCV = CODESIZE% - 1
LOCATE 10,1:PRINT "Verifying byte #"; CODESIZE%; "
"
IF CHR$(CODE%(RCV)) = B$ THEN 1720
K=CODE(RCV):GOSUB 8500
LOCATE 1,1:PRINT "Byte #"; CODESIZE%; "
", " - Sent "; HX$;
K=ASC(B$):GOSUB 8500
PRINT " Received "; HX$;
LOCATE 8, 1: PRINT : PRINT "Done!!!!"
CLOSE
INPUT "Press [RETURN] to quit...", Q$
END
***********************************************************************
*
SUBROUTINE TO READ IN ONE BYTE FROM A DISK FILE
*
RETURNS BYTE IN A$
***********************************************************************
FLAG = 0
IF EOF(1) THEN FLAG = 1: RETURN
A$ = INPUT$(1, #1)
RETURN
***********************************************************************
*
SUBROUTINE TO SEND THE STRING IN A$ OUT TO THE DEVICE
*
OPENED AS FILE #2.
***********************************************************************
PRINT #2, A$;
RETURN
***********************************************************************
*
SUBROUTINE THAT CONVERTS THE HEX DIGIT IN A$ TO AN INTEGER
***********************************************************************
X = INSTR(H$, A$)
IF X = 0 THEN FLAG = 1
X = X - 1
RETURN
MOTOROLA
Application Note
Common Bootstrap Mode Problems
7990
7992
7994
7996
7998
7999
8000
8005
8010
8020
8030
8490
8491
8492
8493
8494
8500
8510
8520
8530
9499
9500
9510
9520
9530
9540
9550
9560
9570
9580
9590
**********************************************************************
*
SUBROUTINE TO READ IN ONE BYTE THROUGH THE COMM PORT OPENED
*
AS FILE #2. WAITS INDEFINITELY FOR THE BYTE TO BE
*
RECEIVED. SUBROUTINE WILL BE ABORTED BY ANY
*
KEYBOARD INPUT. RETURNS BYTE IN B$. USES Q$.
**********************************************************************
WHILE LOC(2) = 0
WAIT FOR COMM PORT INPUT
Q$ = INKEY$: IF Q$ <> "" THEN 4900 IF ANY KEY PRESSED, THEN ABORT
WEND
B$ = INPUT$(1, #2)
RETURN
************************************************************************
*
DECIMAL TO HEX CONVERSION
*
INPUT: K - INTEGER TO BE CONVERTED
*
OUTPUT: HX$ - TWO CHARACTER STRING WITH HEX CONVERSION
************************************************************************
IF K > 255 THEN HX$="Too big":GOTO 8530
HX$=MID$(H$,K\16+1,1)
UPPER NIBBLE
HX$=HX$+MID$(H$,(K MOD 16)+1,1) LOWER NIBBLE
RETURN
******************** BOOT CODE ****************************************
DATA 86, 23
LDAA
#$23
DATA B7, 10, 02
STAA
OPT2
make port C wire or
DATA 86, FE
LDAA
#$FE
DATA B7, 10, 03
STAA
PORTC
light 1 LED on port C bit 0
DATA C6, FF
LDAB
#$FF
DATA F7, 10, 07
STAB
DDRC
make port C outputs
DATA CE, 0F, A0
LDX
#4000
2msec at 2MHz
DATA 18, CE, E0, 00
LDY
#$E000 Start of BUFFALO 3.4
DATA 7E, BF, 00
JMP
$BF00
EPROM routine start address
***********************************************************************
Reset Conditions
vs. Conditions
as Bootloaded
Program Starts
It is common to confuse the reset state of systems and control bits with
the state of these systems and control bits when a bootloaded program
in RAM starts.
307
Application Note
Between these times, the bootloader program is executed, which
changes the states of some systems and control bits:
The SCI system has control of the PD0 and PD1 pins.
Connecting RxD
to VSS Does Not
Cause the SCI
to Receive a Break
$FF Character Is
Required before
Loading into RAM
The initial character (usually $FF) that sets the download baud rate is
often forgotten.
MOTOROLA
MOTOROLA
MCU Part
BOOT
MCU Type
Mask Set
ROM
I.D.
Security
I.D.
Revision
(@$BFD2,3) (@$BFD4,5)
(@$BFD1)
Download
Length
JMP on
BRK or $00(1)
JMP
to RAM (2)
Default
RAM
Location
PROGRAM(3)
and UPLOAD(4) Notes
Utility
MC68HC11A0
MC68HC11A1
MC68HC11A8
MC68SEC11A8
Mask set #
Mask set #
Mask set #
Mask set #
Yes
256
256
256
256
$B600
$B600
$B600
$B600
$0000
$0000
$0000
$0000
$0000FF
$0000FF
$0000FF
$0000FF
(5)
MC68HC11D3
MC68HC711D3
$00
$42(B)
ROM I.D. #
$0000
$11D3
$71D3
0192
0192
$F000ROM
$F000EPROM
$0040FF
$0040FF
Yes
(6)
MC68HC811E2
MC68SEC811E2
$0000
$E2E2
$E25C
Yes
256
256
$B600
$B600
$0000
$0000
$0000FF
$0000FF
(5)
(5)
MC68HC11E0
MC68HC11E1
MC68HC11E9
MC68SEC11E9
ROM I.D. #
ROM I.D. #
ROM I.D. #
ROM I.D. #
$E9E9
$E9E9
$E9E9
$E95C
Yes
0512
0512
0512
0512
$B600
$B600
$B600
$B600
$00001FF
$00001FF
$00001FF
$00001FF
(5)
(5)
(5)
(5)
MC68HC711E9
$41(A)
$0000
$71E9
0512
$B600
$00001FF
Yes
MC68HC11F1
$42(B)
$0000
$F1F1
01024
$FE00
$00003FF
(6), (7)
MC68HC11K4
MC68HC711K4
$30(0)
$42(B)
ROM I.D. #
$0000
$044B
$744B
0768
0768
$0D80
$0D80
$008037F
$008037F
Yes
(6), (8)
(5)
(5)
(5)
(6)
(6), (8)
Application Note
Common Bootstrap Mode Problems
309
1. By sending $00 or a break as the first SCI character after reset in bootstrap mode, a jump (JMP) is executed to the address in this table rather than doing
a download. Unless otherwise noted, this address is the start of EEPROM. Tying RxD to TxD and using a pullup resistor from TxD to VDD will cause the
SCI to see a break as the first received character.
2. If $55 is received as the first character after reset in bootstrap mode, a jump (JMP) is executed to the start of on-chip RAM rather than doing a download.
This $55 character must be sent at the default baud rate (7812 baud @ E = 2 MHz). For devices with variable-length download, the same effect can be
achieved by sending $FF and no other SCI characters. After four SCI character times, the download terminates, and a jump (JMP) to the start of RAM is
executed.
The jump to RAM feature is only useful if the RAM was previously loaded with a meaningful program.
3. A callable utility subroutine is included in the bootstrap ROM of the indicated versions to program bytes of on-chip EPROM with data received via the SCI.
4. A callable utility subroutine is included in the bootstrap ROM of the indicated versions to upload contents of on-chip memory to a host computer via the SCI.
5. The complete listing for this bootstrap ROM may be found in the M68HC11 Reference Manual, Motorola document order number M68HC11RM/AD.
6. The complete listing for this bootstrap ROM is available in the freeware area of the Motorola Web site.
7. Due to the extra program space needed for EEPROM security on this device, there are no pseudo-vectors for SCI, SPI, PAIF, PAOVF, TOF, OC5F,
or OC4F interrupts.
8. This bootloader extends the automatic software detection of baud rates to include 9600 baud at 2-MHz E-clock rate.
Application Note
Original M68HC11
Versions Required
Exactly 256 Bytes
to be Downloaded
to RAM
Even users that know about the 256 bytes of download data sometimes
forget the initial $FF that makes the total number of bytes required for
the entire download operation equal to 256 + 1 or 257 bytes.
Variable-Length
Download
When on-chip RAM surpassed 256 bytes, the time required to serially
load this many characters became more significant. The variable-length
download feature allows shorter programs to be loaded without
sacrificing compatibility with earlier fixed-length download versions of
the bootloader. The end of a download is indicated by an idle RxD line
for at least four character times. If a personal computer is being used to
send the download data to the MCU, there can be problems keeping
characters close enough together to avoid tripping the end-of-download
detect mechanism. Using 1200 as the baud rate rather than the faster
default rate may help this problem.
Assemblers often produce S-record encoded programs which must be
converted to binary before bootloading them to the MCU. The process
of reading S-record data from a file and translating it to binary can be
slow, depending on the personal computer and the programming
language used for the translation. One strategy that can be used to
overcome this problem is to translate the file into binary and store it into
a RAM array before starting the download process. Data can then be
read and downloaded without the translation or file-read delays.
The end-of-download mechanism goes into effect when the initial $FF is
received to set the baud rate. Any amount of time may pass between
reset and when the $FF is sent to start the download process.
EPROM/OTP
Versions
of M68HC11
Have an EPROM
Emulation Mode
The conditions that configure the MCU for EPROM emulation mode are
essentially the same as those for resetting the MCU in bootstrap mode.
While RESET is low and mode select pins are configured for bootstrap
mode (low), the MCU is configured for EPROM emulation mode.
MOTOROLA
Application Note
Common Bootstrap Mode Problems
The port pins that are used for EPROM data I/O lines may be inputs or
outputs, depending on the pin that is emulating the EPROM output
enable pin (OE). To make these data pins appear as high-impedance
inputs as they would on a non-EPROM part in reset, connect the
PB7/(OE) pin to a pullup resistor.
Bootloading
a Program
to Perform
a ROM Checksum
Inherent Delays
Caused
by Double
Buffering
of SCI Data
311
Application Note
Boot ROM Variations
Different versions of the M68HC11 have different versions of the
bootstrap ROM program. Table 3 summarizes the features of the boot
ROMs in 16 members of the M68HC11 Family.
The boot ROMs for the MC68HC11F1, the MC68HC711K4, and the
MC68HC11K4 allow additional choices of baud rates for bootloader
communications. For the three new baud rates, the first character used
to determine the baud rate is not $FF as it was in earlier M68HC11s. The
intercharacter delay that terminates the variable-length download is also
different for these new baud rates. Table 3 shows the synchronization
characters, delay times, and baud rates as they relate to E-clock
frequency.
Sync
Character
Timeout
Delay
$FF
4 characters
7812
8192
11,718
12,288
15,624
16,838
$FF
4 characters
1200
1260
1800
1890
2400
2520
$F0
4.9 characters
9600
10,080
14,400
15,120
19,200
20,160
$FD
17.3 characters
5208
5461
7812
8192
10,416
10,922
$FD
13 characters
3906
4096
5859
6144
7812
8192
MOTOROLA
Application Note
Listing 3. MC68HC711E9 Bootloader ROM
****************************************************
* BOOTLOADER FIRMWARE FOR 68HC711E9 - 21 Aug 89
****************************************************
* Features of this bootloader are...
*
* Auto baud select between 7812.5 and 1200 (8 MHz)
* 0 - 512 byte variable length download
* Jump to EEPROM at $B600 if 1st download byte = $00
* PROGRAM - Utility subroutine to program EPROM
* UPLOAD - Utility subroutine to dump memory to host
* Mask I.D. at $BFD4 = $71E9
****************************************************
* Revision A *
* Fixed bug in PROGRAM routine where the first byte
* programmed into the EPROM was not transmitted for
* verify.
* Also added to PROGRAM routine a skip of bytes
* which were already programmed to the value desired.
*
* This new version allows variable length download
* by quitting reception of characters when an idle
* of at least four character times occurs
*
****************************************************
0008
000E
0016
0023
0080
0028
002B
002D
002E
002F
003B
0020
0001
313
Application Note
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
B600
B7FF
D000
FFFF
0000
01FF
0DB0
021B
1068
BF00
BF00 7EBF13
BF03
* MEMORY
*
EEPMSTR
EEPMEND
*
EPRMSTR
EPRMEND
*
RAMSTR
RAMEND
CONFIGURATION EQUATES
EQU
EQU
$B600
$B7FF
Start of EEPROM
End of EEPROM
EQU
EQU
$D000
$FFFF
Start of EPROM
End of EPROM
EQU
EQU
$0000
$01FF
* DELAY CONSTANTS
*
DELAYS
EQU
3504
DELAYF
EQU
539
*
PROGDEL EQU
4200
*
****************************************************
ORG
$BF00
****************************************************
* Next two instructions provide a predictable place
* to call PROGRAM and UPLOAD even if the routines
* change size in future versions.
*
PROGRAM JMP
PRGROUT
EPROM programming utility
UPLOAD
EQU
*
Upload utility
****************************************************
* UPLOAD - Utility subroutine to send data from
* inside the MCU to the host via the SCI interface.
* Prior to calling UPLOAD set baud rate, turn on SCI
* and set Y=first address to upload.
* Bootloader leaves baud set, SCI enabled, and
* Y pointing at EPROM start ($D000) so these default
* values do not have to be changed typically.
* Consecutive locations are sent via SCI in an
* infinite loop. Reset stops the upload process.
****************************************************
BF03 CE1000
LDX
#$1000
Point to internal registers
BF06 18A600
UPLOOP
LDAA
0,Y
Read byte
BF09 1F2E80FC
BRCLR SCSR,X $80 *
Wait for TDRE
BF0D A72F
STAA
SCDAT,X
Send it
BF0F 1808
INY
BF11 20F3
BRA
UPLOOP
Next...
MOTOROLA
Application Note
Listing 3. MC68HC711E9 Bootloader ROM
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
BF13
BF13 3C
BF14 CE1000
BF17
****************************************************
* PROGRAM - Utility subroutine to program EPROM.
* Prior to calling PROGRAM set baud rate, turn on SCI
* set X=2ms prog delay constant, and set Y=first
* address to program. SP must point to RAM.
* Bootloader leaves baud set, SCI enabled, X=4200
* and Y pointing at EPROM start ($D000) so these
* default values dont have to be changed typically.
* Delay constant in X should be equivalent to 2 ms
* at 2.1 MHz X=4200; at 1 MHz X=2000.
* An external voltage source is required for EPROM
* programming.
* This routine uses 2 bytes of stack space
* Routine does not return. Reset to exit.
****************************************************
PRGROUT EQU
*
PSHX
Save program delay constant
LDX
#$1000
Point to internal registers
* Send $FF to indicate ready for program data
BF17 1F2E80FC
BF1B 86FF
BF1D A72F
BRCLR
LDAA
STAA
SCSR,X $80 *
#$FF
SCDAT,X
1F2E20FC
E62F
18E100
271D
8620
A73B
18E700
8621
A73B
32
33
37
36
E30E
ED16
8680
A723
EQU
BRCLR
LDAB
CMPB
BEQ
LDAA
STAA
STAB
LDAA
STAA
PULA
PULB
PSHB
PSHA
ADDD
STD
LDAA
STAA
*
SCSR,X $20 *
SCDAT,X
$0,Y
DONEIT
#ELAT
PPROG,X
0,Y
#ELAT+EPGM
PPROG,X
BF41 1F2380FC
BF45 6F3B
BRCLR
CLR
BF1F
BF1F
BF23
BF25
BF28
BF2A
BF2C
BF2E
BF31
BF33
BF35
BF36
BF37
BF38
BF39
BF3B
BF3D
BF3F
BF47
BF47
BF4B
BF4E
BF50
BF52
WAIT1
TCNT,X
TOC1,X
#OC1F
TFLG1,X
*
DONEIT
1F2E80FC
18A600
A72F
1808
20CB
EQU
*
BRCLR SCSR,X $80 *
Wait for TDRE
LDAA
$0,Y
Read from EPROM and...
STAA
SCDAT,X
Xmit for verify
INY
Point at next location
BRA
WAIT1
Back to top for next
* Loops indefinitely as long as more data sent.
315
Application Note
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
****************************************************
* Main bootloader starts here
****************************************************
* RESET vector points to here
BF54
BF54
BF57
BF5A
BF5D
BF60
BEGIN
8E01FF
CE1000
1C2820
CCA20C
A72B
BF62 E72D
BF64 CC021B
BF67 ED16
BF69
BF6C
BF70
BF73
BF73
BF77
BF79
BF7B
BF7E
BF7E
BF80
BF82
BF85
BF88
BF8A
BF8A
BF8E
BF8E
BF90
BF90
BF94
BF95
BF96
BF97
BF99
BF9B
BF9B
BF9D
BFA0
BFA2
BFA4
BFA8
1C2D01
1E0801FC
1D2D01
EQU
*
LDS
#RAMEND
Initialize stack pntr
LDX
#$1000
Point at internal regs
BSET
SPCR,X $20
Select port D wire-OR mode
LDD
#$A20C
BAUD in A, SCCR2 in B
STAA
BAUD,X
SCPx = 4, SCRx = 4
* Writing 1 to MSB of BAUD resets count chain
STAB
SCCR2,X
Rx and Tx Enabled
LDD
#DELAYF
Delay for fast baud rate
STD
TOC1,X
Set as default delay
* Send BREAK to
BSET
BRSET
BCLR
1F2E20FC
A62F
EQU
LDD
EQU
BRSET
XGDX
DEX
XGDX
BNE
BRA
*
TOC1,X
Move delay constant to D
*
SCSR,X $20 NEWONE Exit loop if RDRF set
Swap delay count to X
Decrement count
Swap back to D
WTLOOP
Loop if not timed out
STAR
Quit download on timeout
EQU
LDAA
STAA
STAA
INY
CPY
BNE
*
SCDAT,X
$00,Y
SCDAT,X
#RAMEND+1
WAIT
316
MOTOROLA
Application Note
Listing 3. MC68HC711E9 Bootloader ROM
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
BFAA
STAR
EQU
*
BFAA CE1068
LDX
#PROGDEL
Init X with programming delay
BFAD 18CED000
LDY
#EPRMSTR
Init Y with EPROM start addr
BFB1 7E0000
JMP
RAMSTR
** EXIT to start of RAM **
BFB4
****************************************************
* Block fill unused bytes with zeros
BFB4 000000000000
000000000000
000000000000
000000000000
0000000000
BFD1 41
BFD2 0000
BFD4 71E9
BSZ
$BFD1-*
****************************************************
* Boot ROM revision level in ASCII
*
(ORG
$BFD1)
FCC
"A"
****************************************************
* Mask set I.D. ($0000 FOR EPROM PARTS)
*
(ORG
$BFD2)
FDB
$0000
****************************************************
* 711E9 I.D. - Can be used to determine MCU type
*
(ORG
$BFD4)
FDB
$71E9
****************************************************
* VECTORS - point to RAM for pseudo-vector JUMPs
BFD6
BFD8
BFDA
BFDC
BFDE
BFE0
BFE2
BFE4
BFE6
BFE8
BFEA
BFEC
BFEE
BFF0
BFF2
BFF4
BFF6
BFF8
BFFA
BFFC
BFFE
C000
00C4
00C7
00CA
00CD
00D0
00D3
00D6
00D9
00DC
00DF
00E2
00E5
00E8
00EB
00EE
00F1
00F4
00F7
00FA
00FD
BF54
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
END
$100-60
$100-57
$100-54
$100-51
$100-48
$100-45
$100-42
$100-39
$100-36
$100-33
$100-30
$100-27
$100-24
$100-21
$100-18
$100-15
$100-12
$100-9
$100-6
$100-3
BEGIN
SCI
SPI
PULSE ACCUM INPUT EDGE
PULSE ACCUM OVERFLOW
TIMER OVERFLOW
TIMER OUTPUT COMPARE 5
TIMER OUTPUT COMPARE 4
TIMER OUTPUT COMPARE 3
TIMER OUTPUT COMPARE 2
TIMER OUTPUT COMPARE 1
TIMER INPUT CAPTURE 3
TIMER INPUT CAPTURE 2
TIMER INPUT CAPTURE 1
REAL TIME INT
IRQ
XIRQ
SWI
ILLEGAL OP-CODE
COP FAIL
CLOCK MONITOR
RESET
317
Application Note
Symbol Table:
Symbol Name
BAUD
BAUDOK
BEGIN
DELAYF
DELAYS
DONEIT
EEPMEND
EEPMSTR
ELAT
EPGM
EPRMEND
EPRMSTR
NEWONE
NOTZERO
OC1F
PORTD
PPROG
PRGROUT
PROGDEL
PROGRAM
RAMEND
RAMSTR
SCCR2
SCDAT
SCSR
SPCR
STAR
TCNT
TFLG1
TOC1
UPLOAD
UPLOOP
WAIT
WAIT1
WTLOOP
Value
Def.#
002B
BF8A
BF54
021B
0DB0
BF47
B7FF
B600
0020
0001
FFFF
D000
BF9B
BF7E
0080
0008
003B
BF13
1068
BF00
01FF
0000
002D
002F
002E
0028
BFAA
000E
0023
0016
BF03
BF06
BF8E
BF1F
BF90
*00037
*00183
*00155
*00061
*00060
*00142
*00050
*00049
*00043
*00044
*00053
*00052
*00196
*00176
*00034
*00029
*00041
*00110
*00063
*00074
*00056
*00055
*00038
*00040
*00039
*00036
*00204
*00030
*00032
*00031
*00075
*00089
*00186
*00120
*00188
Errors:
Labels:
Last Program Address:
Last Storage Address:
Program Bytes:
Storage Bytes:
00201
00207
00167 00169
00118 00122 00145 00172 00197 00199
00116 00121 00143 00171 00189
00139
00164 00182 00187
00093
00202
00147
00193
None
35
$BFFF
$0000
$0100
$0000
256
0
MOTOROLA
EB184
Introduction
The PCbug11 software, needed along with the M68HC711E9PGMR to
program MC68HC711E9 devices, is available from the download
section of the Microcontroller Worldwide Web site
http://www.motorola.com/semiconductors/.
Retrieve the file pcbug342.exe (a self-extracting archive) from the
MCU11 directory.
Some Motorola evaluation board products also are shipped with
PCbug11.
NOTE:
For specific information about any of the PCbug11 commands, see the
appropriate sections in the PCbug11 Users Manual (part number
M68PCBUG11/D2), which is available from the Motorola Literature
Distribution Center, as well as the Worldwide Web at
http://www.motorola.com/semiconductors/. The file is also on the
software download system and is called pcbug11.pdf.
EB184
Engineering Bulletin
To Execute the Program
Use this step-by-step procedure to program the MC68HC711E9 device.
Step 1
Step 2
Insert the part upside down with the notched corner pointing
toward the red power LED.
Apply +5 volts to +5-V, +12 volts (at most +12.5 volts) to VPP, and
ground to GND on your programmer boards power connector, P1.
The remaining TXD/PD1 and RXD/PD0 connections are not used
in this procedure. They are for gang programming MC68HC711E9
devices, which is discussed in the M68HC711E9PGMR Manual.
You cannot gang program with PCbug11.
Apply power to the programmer board by moving the +5-V switch to the
ON position. From a DOS command line prompt, start PCbug11this way:
C:\PCBUG11\ > PCBUG11 E PORT = 1
with the E9PGMR connected to COM1
or
C:\PCBUG11\ > PCBUG11 E PORT = 2
with the E9PGMR connected to COM2
PCbug11 only supports COM ports 1 and 2. If the proper connections
are made and you have a high-quality cable, you should quickly get a
EB184
320
MOTOROLA
Engineering Bulletin
To Execute the Program
Step 3
Step 4
Step 5
Step 6
Step 7
You are now ready to download the program into the EEPROM and
EPROM.
At the PCbug11command prompt, type:
LOADSC:\MYPROG\MYPROG.S19.
For more details on programming the EPROM, read the engineering
bulletin Programming MC68HC711E9 Devices with PCbug11 and the
M68HC11EVB, Motorola document number EB187.
EB184
MOTOROLA
321
Engineering Bulletin
Step 8
You are now ready to enable the security feature on the MCHC711E9.
At the PCbug11 command prompt type: MS 103F 05.
Step 9
Step 10
The part is now in secure mode and whatever code you loaded into
EEPROM will be erased if you tried to bring the microcontroller up in
either expanded mode or bootstrap mode.
NOTE:
NOTE:
EB184
322
MOTOROLA
EB188
Introduction
The PCbug11 software, needed along with the M68HC711E9PGMR to
program MC68HC811E2 devices, is available from the download
section of the Microcontroller Worldwide Web site
http://www.motorola.com/semiconductors/.
Retrieve the file pcbug342.exe (a self-extracting archive) from the
MCU11 directory.
Some Motorola evaluation board products also are shipped with
PCbug11.
NOTE:
For specific information about any of the PCbug11 commands, see the
appropriate sections in the PCbug11 Users Manual (part number
M68PCBUG11/D2), which is available from the Motorola Literature
Distribution Center, as well as the Worldwide Web at
http://www.motorola.com/semiconductors/. The file is also on the
software download system and is called pcbug11.pdf.
EB188
Engineering Bulletin
To Execute the Program
Once you have obtained PCbug11, use this step-by-step procedure.
Step 1
Step 2
Insert the part upside down with the notched corner pointing
toward the red power LED.
Step 3
324
MOTOROLA
Engineering Bulletin
To Execute the Program
Step 4
Step 5
Step 6
Erase the CONFIG to allow programming of NOSEC bit (bit 3). It is also
recommended to program the EEPROM at this point before
programming the CONFIG register. Refer to the engineering bulletin
Programming MC68HC811E2 Devices with PCbug11 and the
M68HC711E9PGMR, Motorola document number EB184.
At the PCbug11command prompt, type
EEPROM ERASE BULK 103F
EB188
MOTOROLA
325
Engineering Bulletin
Step 7
You are now ready to enable the security feature on the MCHC811E2.
At the PCbug11 command prompt, type
MS 103F 05
The value $05 assumes the EEPROM is to be mapped from $0800 to
$0FFF.
Step 8
Step 9
The part is now in secure mode and whatever code you loaded into
EEPROM will be erased if you tried to bring the microcontroller up in
either expanded mode or bootstrap mode. The microcontroller will work
properly in the secure mode only in single chip mode.
NOTE:
EB188
326
MOTOROLA
EB296
Introduction
The PCbug1software, needed along with the M68HC11EVBU to
program MC68HC711E9 devices, is available from the download
section of the Microcontroller Worldwide Web site
http://www.motorola.com/semiconductors/.
Retrieve the file pcbug342.exe (a self-extracting archive) from the
MCU11 directory.
Some Motorola evaluation board products also are shipped with
PCbug11.
For specific information about any of the PCbug11 commands, see the
appropriate sections in the PCbug11 Users Manual (part number
M68PCBUG11/D2), which is available from the Motorola Literature
Distribution Center, as well as the Worldwide Web at
http://www.motorola.com/semiconductors/. The file is also on the
software download system and is called pcbug11.pdf.
EB296
Engineering Bulletin
Programming Procedure
Once you have obtained PCbug11, use this step-by-step procedure to
program your MC68HC711E9 part.
Step 1
Place a jumper across J4 to ground the MODA pin. This will force
the EVBU into special bootstrap mode on power up.
Also take note of P4 connector pin 18. In step 5, you will connect a +12volt (at most +12.5 volts) programming voltage through a 100- current
limiting resistor to the XIRQ pin. Do not connect this programming
voltage until you are instructed to do so in step 5.
Step 2
EB296
328
MOTOROLA
Engineering Bulletin
Programming Procedure
Step 3
Step 4
Step 5
You are now ready to download your program into the EPROM.
Connect +12 volts (at most +12.5 volts) through a 100- current
limiting resistor to P4 connector pin 18, the XIRQ* pin.
Step 8
EB296
MOTOROLA
329
Engineering Bulletin
EB296
330
MOTOROLA
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE:
http://www.motorola.com/semiconductors/
M68HC11E/D
REV 3
Q4/00
REV 1